Re: [CRTC:24] vblank wait timed out

From: Philipp Zabel <p.zabel@pengutronix.de>
To: Martyn Welch <martyn.welch@collabora.co.uk>
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [CRTC:24] vblank wait timed out
Date: Wed, 29 Mar 2017 10:07:45 +0200	[thread overview]
Message-ID: <1490774865.2274.26.camel@pengutronix.de> (raw)
In-Reply-To: <20170328175247.GS25206@hermes.home>

On Tue, 2017-03-28 at 18:52 +0100, Martyn Welch wrote:
> On Tue, Mar 28, 2017 at 06:44:50PM +0200, Philipp Zabel wrote:
[...] 
> > It is the ipu1_di0_pre_sel and ipu2_di0_pre_sel setup that is important
> > here (and you have to pin LVDS and HDMI to separate IPUs). The LDB
> > driver will switch the ipu1_di0_sel from ipu1_di0_pre to ldb_di1 if IPU1
> > DI0 drives LVDS (imx_ldb_set_clock), so in that case it would be
> > ipu2_di0_pre_sel that had to be switched away from pll5_video_div, to
> > pll2_pfd2_396m.
> > In short, the IPU that drives HDMI must have its pre_sel set to
> > pll2_pfd_396m in your case, to avoid stepping on the LVDS output's toes,
> > as the PLL can't be clocked to the pixel clock and to the LVDS serial
> > clock (3.5*pixel clock) at the same time. The pre_sel setup for the LVDS
> > IPU shouldn't matter as that will be switched to the ldb_di clocks. So
> > just switching both ipu1/2_di0_pre_sel to pll2_pfd2_396m could do the
> > trick?
> > 
> 
> As you can probably tell by how much I got in a muddle with my explanation
> above, this isn't territory I'm familiar with.

Well, the i.MX6 display clock setup is a bit convoluted.

> It sounds good, not sure I 100% understand how to do this yet. :-)
> I'll look into this more.

Have a look at how arch/arm/boot/dts/imx6q-b850v3.dts assigns the
clocks. I'd propose trying this setup:

&clks {
        assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
                          <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
                          <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
                          <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
        assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
                                 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
                                 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
                                 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
};

I hope that way, whichever IPU1/2 DI0 is chosen for HDMI will use PLL2,
while the IPU1/2 DI0 chosen for LVDS will be undisturbed in using PLL5.

regards
Philipp

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