From mboxrd@z Thu Jan 1 00:00:00 1970 From: vathsala nagaraju Subject: [PATCH 1/2] drm/dp: Add defines for latency in sink Date: Sat, 23 Sep 2017 06:04:42 +0530 Message-ID: <1506126883-22800-1-git-send-email-vathsala.nagaraju@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: rodrigo.vivi@intel.com, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Puthikorn Voravootivat , vathsala nagaraju List-Id: dri-devel@lists.freedesktop.org QWRkIGRlZmluZXMgZm9yIGRwY2QgcmVnaXN0ZXIgMjAwOSAoc3luY2hyb25pemF0aW9uIGxhdGVu Y3kKaW4gc2luaykuCgpDYzogUm9kcmlnbyBWaXZpIDxyb2RyaWdvLnZpdmlAaW50ZWwuY29tPgpD QzogUHV0aGlrb3JuIFZvcmF2b290aXZhdCA8cHV0aGlrQGNocm9taXVtLm9yZz4KUmV2aWV3ZWQt Ynk6IFJvZHJpZ28gVml2aSA8cm9kcmlnby52aXZpQGludGVsLmNvbT4KU2lnbmVkLW9mZi1ieTog VmF0aHNhbGEgTmFnYXJhanUgPHZhdGhzYWxhLm5hZ2FyYWp1QGludGVsLmNvbT4KLS0tCiBpbmNs dWRlL2RybS9kcm1fZHBfaGVscGVyLmggfCAzICsrKwogMSBmaWxlIGNoYW5nZWQsIDMgaW5zZXJ0 aW9ucygrKQoKZGlmZiAtLWdpdCBhL2luY2x1ZGUvZHJtL2RybV9kcF9oZWxwZXIuaCBiL2luY2x1 ZGUvZHJtL2RybV9kcF9oZWxwZXIuaAppbmRleCAxMWMzOWYxLi44NDYwMDRlNiAxMDA2NDQKLS0t IGEvaW5jbHVkZS9kcm0vZHJtX2RwX2hlbHBlci5oCisrKyBiL2luY2x1ZGUvZHJtL2RybV9kcF9o ZWxwZXIuaApAQCAtNzM1LDYgKzczNSw5IEBACiAjIGRlZmluZSBEUF9QU1JfU0lOS19JTlRFUk5B TF9FUlJPUiAgICAgICAgIDcKICMgZGVmaW5lIERQX1BTUl9TSU5LX1NUQVRFX01BU0sgICAgICAg ICAgICAgMHgwNwogCisjZGVmaW5lIERQX1NJTktfU1lOQ0hST05JWkFUSU9OX0xBVEVOQ1kJICAg IDB4MjAwOQorIyBkZWZpbmUgRFBfTUFYX1JFU1lOQ19GUkFNRV9DTlRfTUFTSwkgICAgMHhmCisK ICNkZWZpbmUgRFBfUkVDRUlWRVJfQUxQTV9TVEFUVVMJCSAgICAweDIwMGIgIC8qIGVEUCAxLjQg Ki8KICMgZGVmaW5lIERQX0FMUE1fTE9DS19USU1FT1VUX0VSUk9SCSAgICAoMSA8PCAwKQogCi0t IAoxLjkuMQoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18K ZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0 dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg==