* [PATCH 1/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 00h-0fh) Processors
@ 2017-11-03 13:52 Christian König
2017-11-03 13:52 ` [PATCH 3/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 60h-6fh) Processors Christian König
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Christian König @ 2017-11-03 13:52 UTC (permalink / raw)
To: linux-pci, dri-devel, platform-driver-x86, linux-kernel, amd-gfx,
helgaas
Just add the extra PCI-ID to the existing fixup.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
arch/x86/pci/fixup.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index 7b6bd76..1d2238d 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -639,7 +639,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff);
* configuring host bridge windows using the _PRS and _SRS methods.
*
* But this is rarely implemented, so we manually enable a large 64bit BAR for
- * PCIe device on AMD Family 15h (Models 30h-3fh) Processors here.
+ * PCIe device on AMD Family 15h (Models 00h-0fh, 30h-3fh) Processors here.
*/
static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
{
@@ -696,5 +696,6 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
pci_bus_add_resource(dev->bus, res, 0);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
#endif
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 60h-6fh) Processors
2017-11-03 13:52 [PATCH 1/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 00h-0fh) Processors Christian König
@ 2017-11-03 13:52 ` Christian König
[not found] ` <1509717164-1946-1-git-send-email-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2017-11-08 20:48 ` [PATCH 1/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 00h-0fh) Processors Bjorn Helgaas
2 siblings, 0 replies; 5+ messages in thread
From: Christian König @ 2017-11-03 13:52 UTC (permalink / raw)
To: linux-pci, dri-devel, platform-driver-x86, linux-kernel, amd-gfx,
helgaas
Just add the extra PCI-ID to the existing fixup.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
arch/x86/pci/fixup.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index aa8b20e..3eebb0e 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -639,7 +639,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff);
* configuring host bridge windows using the _PRS and _SRS methods.
*
* But this is rarely implemented, so we manually enable a large 64bit BAR for
- * PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh) Processors here.
+ * PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh, 60h-6fh) Processors
+ * here.
*/
static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
{
@@ -697,6 +698,7 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
#endif
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 5+ messages in thread[parent not found: <1509717164-1946-1-git-send-email-christian.koenig-5C7GfCeVMHo@public.gmane.org>]
* [PATCH 2/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 10h-1fh) Processors
[not found] ` <1509717164-1946-1-git-send-email-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2017-11-03 13:52 ` Christian König
2017-11-03 13:52 ` [PATCH 4/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 70h-7fh) Processors Christian König
1 sibling, 0 replies; 5+ messages in thread
From: Christian König @ 2017-11-03 13:52 UTC (permalink / raw)
To: linux-pci-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
platform-driver-x86-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
helgaas-DgEjT+Ai2ygdnm+yROfE0A
Just add the extra PCI-ID to the existing fixup.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
arch/x86/pci/fixup.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index 1d2238d..aa8b20e 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -639,7 +639,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff);
* configuring host bridge windows using the _PRS and _SRS methods.
*
* But this is rarely implemented, so we manually enable a large 64bit BAR for
- * PCIe device on AMD Family 15h (Models 00h-0fh, 30h-3fh) Processors here.
+ * PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh) Processors here.
*/
static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
{
@@ -695,6 +695,7 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
pci_bus_add_resource(dev->bus, res, 0);
}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 4/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 70h-7fh) Processors
[not found] ` <1509717164-1946-1-git-send-email-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2017-11-03 13:52 ` [PATCH 2/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 10h-1fh) Processors Christian König
@ 2017-11-03 13:52 ` Christian König
1 sibling, 0 replies; 5+ messages in thread
From: Christian König @ 2017-11-03 13:52 UTC (permalink / raw)
To: linux-pci-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
platform-driver-x86-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
helgaas-DgEjT+Ai2ygdnm+yROfE0A
Just add the extra PCI-ID to the existing fixup.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
arch/x86/pci/fixup.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index 3eebb0e..894d73d 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -639,7 +639,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff);
* configuring host bridge windows using the _PRS and _SRS methods.
*
* But this is rarely implemented, so we manually enable a large 64bit BAR for
- * PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh, 60h-6fh) Processors
+ * PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh, 60h-7fh) Processors
* here.
*/
static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
@@ -699,6 +699,7 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
#endif
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 00h-0fh) Processors
2017-11-03 13:52 [PATCH 1/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 00h-0fh) Processors Christian König
2017-11-03 13:52 ` [PATCH 3/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 60h-6fh) Processors Christian König
[not found] ` <1509717164-1946-1-git-send-email-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2017-11-08 20:48 ` Bjorn Helgaas
2 siblings, 0 replies; 5+ messages in thread
From: Bjorn Helgaas @ 2017-11-08 20:48 UTC (permalink / raw)
To: Christian König
Cc: linux-pci, dri-devel, platform-driver-x86, linux-kernel, amd-gfx,
Andy Shevchenko
[+cc Andy]
On Fri, Nov 03, 2017 at 02:52:41PM +0100, Christian König wrote:
> Just add the extra PCI-ID to the existing fixup.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
I folded all these additional devices into the original quirk.
> ---
> arch/x86/pci/fixup.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
> index 7b6bd76..1d2238d 100644
> --- a/arch/x86/pci/fixup.c
> +++ b/arch/x86/pci/fixup.c
> @@ -639,7 +639,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff);
> * configuring host bridge windows using the _PRS and _SRS methods.
> *
> * But this is rarely implemented, so we manually enable a large 64bit BAR for
> - * PCIe device on AMD Family 15h (Models 30h-3fh) Processors here.
> + * PCIe device on AMD Family 15h (Models 00h-0fh, 30h-3fh) Processors here.
> */
> static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
> {
> @@ -696,5 +696,6 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
> pci_bus_add_resource(dev->bus, res, 0);
> }
> DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
>
> #endif
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-11-08 20:48 UTC | newest]
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2017-11-03 13:52 ` [PATCH 3/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 60h-6fh) Processors Christian König
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