From: Sharat Masetty <smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Sharat Masetty <smasetty-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: [PATCH] rnndb/adreno: Add more PM4 opcodes
Date: Fri, 2 Mar 2018 13:39:47 +0530 [thread overview]
Message-ID: <1519978187-1573-1-git-send-email-smasetty@codeaurora.org> (raw)
Add CP_SECURE_MODE and CP_SET_PSEUDO_REG opcodes needed for A6xx
hardware features.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
rnndb/adreno/adreno_pm4.xml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/rnndb/adreno/adreno_pm4.xml b/rnndb/adreno/adreno_pm4.xml
index 3621f07..c1a82da 100644
--- a/rnndb/adreno/adreno_pm4.xml
+++ b/rnndb/adreno/adreno_pm4.xml
@@ -288,6 +288,11 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<!-- switches SMMU pagetable, used on a5xx only -->
<value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
<value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX"/>
+ <!-- for a6xx -->
+ <doc>Tells CP the current mode of GPU operation</doc>
+ <value name="CP_SET_MARKER" value="0x65" variants="A6XX"/>
+ <doc>Instruct CP to set a few inernal CP registers</doc>
+ <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/>
<!--
pairs of regid and value.. seems to be used to program some TF
related regs:
--
1.9.1
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