[DPU PATCH v3 2/7] drm/msm/dpu: clean up dpu plane custom properties

Jeykumar Sankaran
2018-06-11T21:13:19Z

This change removes all the dpu plane custom properties
and its handlers.

changes in v2:
- remove stale code in blend config(Sean Paul)
- Makefile changes to remove warning flags(Sean Paul)
changes in v3:
- rebased on https://gitlab.freedesktop.org/seanpaul/
dpu-staging/commit/481d29d31cd629fd216381b53de5695f645465d5

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
drivers/gpu/drm/msm/Makefile | 8 -
drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h | 99 --
.../gpu/drm/msm/disp/dpu1/dpu_color_processing.c | 1521 --------------------
.../gpu/drm/msm/disp/dpu1/dpu_color_processing.h | 120 --
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 205 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c | 1443 -------------------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 72 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 89 --
.../msm/disp/dpu1/dpu_hw_color_proc_common_v4.h | 69 -
.../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c | 242 ----
.../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h | 40 -
.../drm/msm/disp/dpu1/dpu_hw_color_processing.h | 20 -
.../msm/disp/dpu1/dpu_hw_color_processing_v1_7.c | 565 --------
.../msm/disp/dpu1/dpu_hw_color_processing_v1_7.h | 92 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 44 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 15 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 209 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h | 220 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 44 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 68 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 6 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c | 757 ----------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h | 27 -
.../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c | 943 ------------
.../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h | 75 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 220 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 73 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 156 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 -
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 1269 +---------------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 31 -
drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c | 139 --
drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h | 310 ----
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 102 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 -
drivers/gpu/drm/msm/msm_drv.h | 28 -
include/uapi/drm/dpu_drm.h | 187 ---
include/uapi/drm/msm_drm.h | 1 -
42 files changed, 282 insertions(+), 9247 deletions(-)
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.h
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_common_v4.h
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing.h
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.c
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.h
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 9d1d52c..8ec0bff 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -46,7 +46,6 @@ msm-y := \
disp/mdp5/mdp5_mixer.o \
disp/mdp5/mdp5_plane.o \
disp/mdp5/mdp5_smp.o \
- disp/dpu1/dpu_color_processing.o \
disp/dpu1/dpu_core_irq.o \
disp/dpu1/dpu_core_perf.o \
disp/dpu1/dpu_crtc.o \
@@ -54,21 +53,15 @@ msm-y := \
disp/dpu1/dpu_encoder_phys_cmd.o \
disp/dpu1/dpu_encoder_phys_vid.o \
disp/dpu1/dpu_formats.o \
- disp/dpu1/dpu_hw_ad4.o \
disp/dpu1/dpu_hw_blk.o \
disp/dpu1/dpu_hw_catalog.o \
disp/dpu1/dpu_hw_cdm.o \
- disp/dpu1/dpu_hw_color_proc_v4.o \
- disp/dpu1/dpu_hw_color_processing_v1_7.o \
disp/dpu1/dpu_hw_ctl.o \
disp/dpu1/dpu_hw_ds.o \
- disp/dpu1/dpu_hw_dspp.o \
disp/dpu1/dpu_hw_interrupts.o \
disp/dpu1/dpu_hw_intf.o \
disp/dpu1/dpu_hw_lm.o \
disp/dpu1/dpu_hw_pingpong.o \
- disp/dpu1/dpu_hw_reg_dma_v1.o \
- disp/dpu1/dpu_hw_reg_dma_v1_color_proc.o \
disp/dpu1/dpu_hw_sspp.o \
disp/dpu1/dpu_hw_top.o \
disp/dpu1/dpu_hw_util.o \
@@ -78,7 +71,6 @@ msm-y := \
disp/dpu1/dpu_kms.o \
disp/dpu1/dpu_kms_utils.o \
disp/dpu1/dpu_plane.o \
- disp/dpu1/dpu_reg_dma.o \
disp/dpu1/dpu_rm.o \
disp/dpu1/dpu_vbif.o \
disp/dpu1/dpu_mdss.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h
deleted file mode 100644
index 5b70c4a..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef _DPU_AD4_H_
-#define _DPU_AD4_H_
-
-#include <drm/drm_mode.h>
-#include <drm/drm_property.h>
-#include "dpu_hw_dspp.h"
-
-/**
- * enum ad4_modes - ad4 modes supported by driver
- */
-enum ad4_modes {
- AD4_OFF,
- AD4_AUTO_STRENGTH,
- AD4_CALIBRATION,
- AD4_MANUAL,
-};
-
-/**
- * struct drm_prop_enum_list - drm structure for creating enum property and
- * enumerating values
- */
-static const struct drm_prop_enum_list ad4_modes[] = {
- {AD4_OFF, "off"},
- {AD4_AUTO_STRENGTH, "auto_strength_mode"},
- {AD4_CALIBRATION, "calibration_mode"},
- {AD4_MANUAL, "manual_mode"},
-};
-
-/**
- * enum ad_property - properties that can be set for ad
- */
-enum ad_property {
- AD_MODE,
- AD_INIT,
- AD_CFG,
- AD_INPUT,
- AD_SUSPEND,
- AD_ASSERTIVE,
- AD_BACKLIGHT,
- AD_IPC_SUSPEND,
- AD_IPC_RESUME,
- AD_IPC_RESET,
- AD_PROPMAX,
-};
-
-/**
- * enum ad_intr_resp_property - ad4 interrupt response enum
- */
-enum ad_intr_resp_property {
- AD4_BACKLIGHT,
- AD4_RESPMAX,
-};
-
-/**
- * struct dpu_ad_hw_cfg - structure for setting the ad properties
- * @prop: enum of ad property
- * @hw_cfg: payload for the prop being set.
- */
-struct dpu_ad_hw_cfg {
- enum ad_property prop;
- struct dpu_hw_cp_cfg *hw_cfg;
-};
-
-/**
- * dpu_validate_dspp_ad4() - api to validate if ad property is allowed for
- * the display with allocated dspp/mixers.
- * @dspp: pointer to dspp info structure.
- * @prop: pointer to u32 pointing to ad property
- */
-int dpu_validate_dspp_ad4(struct dpu_hw_dspp *dspp, u32 *prop);
-
-/**
- * dpu_setup_dspp_ad4 - api to apply the ad property, dpu_validate_dspp_ad4
- * should be called before call this function
- * @dspp: pointer to dspp info structure.
- * @cfg: pointer to struct dpu_ad_hw_cfg
- */
-void dpu_setup_dspp_ad4(struct dpu_hw_dspp *dspp, void *cfg);
-
-/**
- * dpu_read_intr_resp_ad4 - api to get ad4 interrupt status for event
- * @dspp: pointer to dspp object
- * @event: event for which response is needed
- * @resp: value of event requested
- */
-void dpu_read_intr_resp_ad4(struct dpu_hw_dspp *dspp, u32 event, u32 *resp);
-
-#endif /* _DPU_AD4_H_ */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
deleted file mode 100644
index f13d1cc..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
+++ /dev/null
@@ -1,1521 +0,0 @@
-/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#define pr_fmt(fmt) "%s: " fmt, __func__
-
-#include <drm/msm_drm_pp.h>
-#include "dpu_color_processing.h"
-#include "dpu_kms.h"
-#include "dpu_crtc.h"
-#include "dpu_hw_dspp.h"
-#include "dpu_hw_lm.h"
-#include "dpu_ad4.h"
-#include "dpu_hw_interrupts.h"
-#include "dpu_core_irq.h"
-
-struct dpu_cp_node {
- u32 property_id;
- u32 prop_flags;
- u32 feature;
- void *blob_ptr;
- uint64_t prop_val;
- const struct dpu_pp_blk *pp_blk;
- struct list_head feature_list;
- struct list_head active_list;
- struct list_head dirty_list;
- bool is_dspp_feature;
- u32 prop_blob_sz;
- struct dpu_irq_callback *irq;
-};
-
-struct dpu_cp_prop_attach {
- struct drm_crtc *crtc;
- struct drm_property *prop;
- struct dpu_cp_node *prop_node;
- u32 feature;
- uint64_t val;
-};
-
-static void dspp_pcc_install_property(struct drm_crtc *crtc);
-
-static void dspp_hsic_install_property(struct drm_crtc *crtc);
-
-static void dspp_ad_install_property(struct drm_crtc *crtc);
-
-static void dspp_vlut_install_property(struct drm_crtc *crtc);
-
-static void dspp_gamut_install_property(struct drm_crtc *crtc);
-
-static void dspp_gc_install_property(struct drm_crtc *crtc);
-
-static void dspp_igc_install_property(struct drm_crtc *crtc);
-
-typedef void (*dspp_prop_install_func_t)(struct drm_crtc *crtc);
-
-static dspp_prop_install_func_t dspp_prop_install_func[DPU_DSPP_MAX];
-
-static void dpu_cp_update_list(struct dpu_cp_node *prop_node,
- struct dpu_crtc *crtc, bool dirty_list);
-
-static int dpu_cp_ad_validate_prop(struct dpu_cp_node *prop_node,
- struct dpu_crtc *crtc);
-
-static void dpu_cp_notify_ad_event(struct drm_crtc *crtc_drm, void *arg);
-
-static void dpu_cp_ad_set_prop(struct dpu_crtc *dpu_crtc,
- enum ad_property ad_prop);
-
-#define setup_dspp_prop_install_funcs(func) \
-do { \
- func[DPU_DSPP_PCC] = dspp_pcc_install_property; \
- func[DPU_DSPP_HSIC] = dspp_hsic_install_property; \
- func[DPU_DSPP_AD] = dspp_ad_install_property; \
- func[DPU_DSPP_VLUT] = dspp_vlut_install_property; \
- func[DPU_DSPP_GAMUT] = dspp_gamut_install_property; \
- func[DPU_DSPP_GC] = dspp_gc_install_property; \
- func[DPU_DSPP_IGC] = dspp_igc_install_property; \
-} while (0)
-
-typedef void (*lm_prop_install_func_t)(struct drm_crtc *crtc);
-
-static lm_prop_install_func_t lm_prop_install_func[DPU_MIXER_MAX];
-
-static void lm_gc_install_property(struct drm_crtc *crtc);
-
-#define setup_lm_prop_install_funcs(func) \
- (func[DPU_MIXER_GC] = lm_gc_install_property)
-
-enum {
- /* Append new DSPP features before DPU_CP_CRTC_DSPP_MAX */
- /* DSPP Features start */
- DPU_CP_CRTC_DSPP_IGC,
- DPU_CP_CRTC_DSPP_PCC,
- DPU_CP_CRTC_DSPP_GC,
- DPU_CP_CRTC_DSPP_HUE,
- DPU_CP_CRTC_DSPP_SAT,
- DPU_CP_CRTC_DSPP_VAL,
- DPU_CP_CRTC_DSPP_CONT,
- DPU_CP_CRTC_DSPP_MEMCOLOR,
- DPU_CP_CRTC_DSPP_SIXZONE,
- DPU_CP_CRTC_DSPP_GAMUT,
- DPU_CP_CRTC_DSPP_DITHER,
- DPU_CP_CRTC_DSPP_HIST,
- DPU_CP_CRTC_DSPP_AD,
- DPU_CP_CRTC_DSPP_VLUT,
- DPU_CP_CRTC_DSPP_AD_MODE,
- DPU_CP_CRTC_DSPP_AD_INIT,
- DPU_CP_CRTC_DSPP_AD_CFG,
- DPU_CP_CRTC_DSPP_AD_INPUT,
- DPU_CP_CRTC_DSPP_AD_ASSERTIVENESS,
- DPU_CP_CRTC_DSPP_AD_BACKLIGHT,
- DPU_CP_CRTC_DSPP_MAX,
- /* DSPP features end */
-
- /* Append new LM features before DPU_CP_CRTC_MAX_FEATURES */
- /* LM feature start*/
- DPU_CP_CRTC_LM_GC,
- /* LM feature end*/
-
- DPU_CP_CRTC_MAX_FEATURES,
-};
-
-#define INIT_PROP_ATTACH(p, crtc, prop, node, feature, val) \
- do { \
- (p)->crtc = crtc; \
- (p)->prop = prop; \
- (p)->prop_node = node; \
- (p)->feature = feature; \
- (p)->val = val; \
- } while (0)
-
-static void dpu_cp_get_hw_payload(struct dpu_cp_node *prop_node,
- struct dpu_hw_cp_cfg *hw_cfg,
- bool *feature_enabled)
-{
-
- struct drm_property_blob *blob = NULL;
-
- memset(hw_cfg, 0, sizeof(*hw_cfg));
- *feature_enabled = false;
-
- blob = prop_node->blob_ptr;
- if (prop_node->prop_flags & DRM_MODE_PROP_BLOB) {
- if (blob) {
- hw_cfg->len = blob->length;
- hw_cfg->payload = blob->data;
- *feature_enabled = true;
- }
- } else if (prop_node->prop_flags & DRM_MODE_PROP_RANGE) {
- /* Check if local blob is Set */
- if (!blob) {
- if (prop_node->prop_val) {
- hw_cfg->len = sizeof(prop_node->prop_val);
- hw_cfg->payload = &prop_node->prop_val;
- }
- } else {
- hw_cfg->len = (prop_node->prop_val) ? blob->length :
- 0;
- hw_cfg->payload = (prop_node->prop_val) ? blob->data
- : NULL;
- }
- if (prop_node->prop_val)
- *feature_enabled = true;
- } else if (prop_node->prop_flags & DRM_MODE_PROP_ENUM) {
- *feature_enabled = (prop_node->prop_val != 0);
- hw_cfg->len = sizeof(prop_node->prop_val);
- hw_cfg->payload = &prop_node->prop_val;
- } else {
- DRM_ERROR("property type is not supported\n");
- }
-}
-
-static int dpu_cp_disable_crtc_blob_property(struct dpu_cp_node *prop_node)
-{
- struct drm_property_blob *blob = prop_node->blob_ptr;
-
- if (!blob)
- return 0;
- drm_property_blob_put(blob);
- prop_node->blob_ptr = NULL;
- return 0;
-}
-
-static int dpu_cp_create_local_blob(struct drm_crtc *crtc, u32 feature, int len)
-{
- int ret = -EINVAL;
- bool found = false;
- struct dpu_cp_node *prop_node = NULL;
- struct drm_property_blob *blob_ptr;
- struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
-
- list_for_each_entry(prop_node, &dpu_crtc->feature_list, feature_list) {
- if (prop_node->feature == feature) {
- found = true;
- break;
- }
- }
-
- if (!found || !(prop_node->prop_flags & DRM_MODE_PROP_RANGE)) {
- DRM_ERROR("local blob create failed prop found %d flags %d\n",
- found, prop_node->prop_flags);
- return ret;
- }
-
- blob_ptr = drm_property_create_blob(crtc->dev, len, NULL);
- ret = (IS_ERR_OR_NULL(blob_ptr)) ? PTR_ERR(blob_ptr) : 0;
- if (!ret)
- prop_node->blob_ptr = blob_ptr;
-
- return ret;
-}
-
-static void dpu_cp_destroy_local_blob(struct dpu_cp_node *prop_node)
-{
- if (!(prop_node->prop_flags & DRM_MODE_PROP_BLOB) &&
- prop_node->blob_ptr)
- drm_property_blob_put(prop_node->blob_ptr);
-}
-
-static int dpu_cp_handle_range_property(struct dpu_cp_node *prop_node,
- uint64_t val)
-{
- int ret = 0;
- struct drm_property_blob *blob_ptr = prop_node->blob_ptr;
-
- if (!blob_ptr) {
- prop_node->prop_val = val;
- return 0;
- }
-
- if (!val) {
- prop_node->prop_val = 0;
- return 0;
- }
-
- ret = copy_from_user(blob_ptr->data, u64_to_user_ptr(val),
- blob_ptr->length);
- if (ret) {
- DRM_ERROR("failed to get the property info ret %d", ret);
- ret = -EFAULT;
- } else {
- prop_node->prop_val = val;
- }
-
- return ret;
-}
-
-static int dpu_cp_disable_crtc_property(struct drm_crtc *crtc,
- struct drm_property *property,
- struct dpu_cp_node *prop_node)
-{
- int ret = -EINVAL;
-
- if (property->flags & DRM_MODE_PROP_BLOB) {
- ret = dpu_cp_disable_crtc_blob_property(prop_node);
- } else if (property->flags & DRM_MODE_PROP_RANGE) {
- ret = dpu_cp_handle_range_property(prop_node, 0);
- } else if (property->flags & DRM_MODE_PROP_ENUM) {
- ret = 0;
- prop_node->prop_val = 0;
- }
- return ret;
-}
-
-static int dpu_cp_enable_crtc_blob_property(struct drm_crtc *crtc,
- struct dpu_cp_node *prop_node,
- uint64_t val)
-{
- struct drm_property_blob *blob = NULL;
-
- /**
- * For non-blob based properties add support to create a blob
- * using the val and store the blob_ptr in prop_node.
- */
- blob = drm_property_lookup_blob(crtc->dev, val);
- if (!blob) {
- DRM_ERROR("invalid blob id %lld\n", val);
- return -EINVAL;
- }
- if (blob->length != prop_node->prop_blob_sz) {
- DRM_ERROR("invalid blob len %zd exp %d feature %d\n",
- blob->length, prop_node->prop_blob_sz, prop_node->feature);
- drm_property_blob_put(blob);
- return -EINVAL;
- }
- /* Release refernce to existing payload of the property */
- if (prop_node->blob_ptr)
- drm_property_blob_put(prop_node->blob_ptr);
-
- prop_node->blob_ptr = blob;
- return 0;
-}
-
-static int dpu_cp_enable_crtc_property(struct drm_crtc *crtc,
- struct drm_property *property,
- struct dpu_cp_node *prop_node,
- uint64_t val)
-{
- int ret = -EINVAL;
-
- if (property->flags & DRM_MODE_PROP_BLOB) {
- ret = dpu_cp_enable_crtc_blob_property(crtc, prop_node, val);
- } else if (property->flags & DRM_MODE_PROP_RANGE) {
- ret = dpu_cp_handle_range_property(prop_node, val);
- } else if (property->flags & DRM_MODE_PROP_ENUM) {
- ret = 0;
- prop_node->prop_val = val;
- }
- return ret;
-}
-
-static struct dpu_kms *get_kms(struct drm_crtc *crtc)
-{
- struct msm_drm_private *priv = crtc->dev->dev_private;
-
- return to_dpu_kms(priv->kms);
-}
-
-static void dpu_cp_crtc_prop_attach(struct dpu_cp_prop_attach *prop_attach)
-{
-
- struct dpu_crtc *dpu_crtc = to_dpu_crtc(prop_attach->crtc);
-
- drm_object_attach_property(&prop_attach->crtc->base,
- prop_attach->prop, prop_attach->val);
-
- INIT_LIST_HEAD(&prop_attach->prop_node->active_list);
- INIT_LIST_HEAD(&prop_attach->prop_node->dirty_list);
-
- prop_attach->prop_node->property_id = prop_attach->prop->base.id;
- prop_attach->prop_node->prop_flags = prop_attach->prop->flags;
- prop_attach->prop_node->feature = prop_attach->feature;
-
- if (prop_attach->feature < DPU_CP_CRTC_DSPP_MAX)
- prop_attach->prop_node->is_dspp_feature = true;
- else
- prop_attach->prop_node->is_dspp_feature = false;
-
- list_add(&prop_attach->prop_node->feature_list,
- &dpu_crtc->feature_list);
-}
-
-void dpu_cp_crtc_init(struct drm_crtc *crtc)
-{
- struct dpu_crtc *dpu_crtc = NULL;
-
- if (!crtc) {
- DRM_ERROR("invalid crtc %pK\n", crtc);
- return;
- }
-
- dpu_crtc = to_dpu_crtc(crtc);
- if (!dpu_crtc) {
- DRM_ERROR("invalid dpu_crtc %pK\n", dpu_crtc);
- return;
- }
-
- INIT_LIST_HEAD(&dpu_crtc->active_list);
- INIT_LIST_HEAD(&dpu_crtc->dirty_list);
- INIT_LIST_HEAD(&dpu_crtc->feature_list);
- INIT_LIST_HEAD(&dpu_crtc->ad_dirty);
- INIT_LIST_HEAD(&dpu_crtc->ad_active);
-}
-
-static void dpu_cp_crtc_install_immutable_property(struct drm_crtc *crtc,
- char *name,
- u32 feature)
-{
- struct drm_property *prop;
- struct dpu_cp_node *prop_node = NULL;
- struct msm_drm_private *priv;
- struct dpu_cp_prop_attach prop_attach;
- uint64_t val = 0;
-
- if (feature >= DPU_CP_CRTC_MAX_FEATURES) {
- DRM_ERROR("invalid feature %d max %d\n", feature,
- DPU_CP_CRTC_MAX_FEATURES);
- return;
- }
-
- prop_node = kzalloc(sizeof(*prop_node), GFP_KERNEL);
- if (!prop_node)
- return;
-
- priv = crtc->dev->dev_private;
- prop = priv->cp_property[feature];
-
- if (!prop) {
- prop = drm_property_create_range(crtc->dev,
- DRM_MODE_PROP_IMMUTABLE, name, 0, 1);
- if (!prop) {
- DRM_ERROR("property create failed: %s\n", name);
- kfree(prop_node);
- return;
- }
- priv->cp_property[feature] = prop;
- }
-
- INIT_PROP_ATTACH(&prop_attach, crtc, prop, prop_node,
- feature, val);
- dpu_cp_crtc_prop_attach(&prop_attach);
-}
-
-static void dpu_cp_crtc_install_range_property(struct drm_crtc *crtc,
- char *name,
- u32 feature,
- uint64_t min, uint64_t max,
- uint64_t val)
-{
- struct drm_property *prop;
- struct dpu_cp_node *prop_node = NULL;
- struct msm_drm_private *priv;
- struct dpu_cp_prop_attach prop_attach;
-
- if (feature >= DPU_CP_CRTC_MAX_FEATURES) {
- DRM_ERROR("invalid feature %d max %d\n", feature,
- DPU_CP_CRTC_MAX_FEATURES);
- return;
- }
-
- prop_node = kzalloc(sizeof(*prop_node), GFP_KERNEL);
- if (!prop_node)
- return;
-
- priv = crtc->dev->dev_private;
- prop = priv->cp_property[feature];
-
- if (!prop) {
- prop = drm_property_create_range(crtc->dev, 0, name, min, max);
- if (!prop) {
- DRM_ERROR("property create failed: %s\n", name);
- kfree(prop_node);
- return;
- }
- priv->cp_property[feature] = prop;
- }
-
- INIT_PROP_ATTACH(&prop_attach, crtc, prop, prop_node,
- feature, val);
-
- dpu_cp_crtc_prop_attach(&prop_attach);
-}
-
-static void dpu_cp_crtc_install_blob_property(struct drm_crtc *crtc, char *name,
- u32 feature, u32 blob_sz)
-{
- struct drm_property *prop;
- struct dpu_cp_node *prop_node = NULL;
- struct msm_drm_private *priv;
- uint64_t val = 0;
- struct dpu_cp_prop_attach prop_attach;
-
- if (feature >= DPU_CP_CRTC_MAX_FEATURES) {
- DRM_ERROR("invalid feature %d max %d\n", feature,
- DPU_CP_CRTC_MAX_FEATURES);
- return;
- }
-
- prop_node = kzalloc(sizeof(*prop_node), GFP_KERNEL);
- if (!prop_node)
- return;
-
- priv = crtc->dev->dev_private;
- prop = priv->cp_property[feature];
-
- if (!prop) {
- prop = drm_property_create(crtc->dev,
- DRM_MODE_PROP_BLOB, name, 0);
- if (!prop) {
- DRM_ERROR("property create failed: %s\n", name);
- kfree(prop_node);
- return;
- }
- priv->cp_property[feature] = prop;
- }
-
- INIT_PROP_ATTACH(&prop_attach, crtc, prop, prop_node,
- feature, val);
- prop_node->prop_blob_sz = blob_sz;
-
- dpu_cp_crtc_prop_attach(&prop_attach);
-}
-
-static void dpu_cp_crtc_install_enum_property(struct drm_crtc *crtc,
- u32 feature, const struct drm_prop_enum_list *list, u32 enum_sz,
- char *name)
-{
- struct drm_property *prop;
- struct dpu_cp_node *prop_node = NULL;
- struct msm_drm_private *priv;
- uint64_t val = 0;
- struct dpu_cp_prop_attach prop_attach;
-
- if (feature >= DPU_CP_CRTC_MAX_FEATURES) {
- DRM_ERROR("invalid feature %d max %d\n", feature,
- DPU_CP_CRTC_MAX_FEATURES);
- return;
- }
-
- prop_node = kzalloc(sizeof(*prop_node), GFP_KERNEL);
- if (!prop_node)
- return;
-
- priv = crtc->dev->dev_private;
- prop = priv->cp_property[feature];
-
- if (!prop) {
- prop = drm_property_create_enum(crtc->dev, 0, name,
- list, enum_sz);
- if (!prop) {
- DRM_ERROR("property create failed: %s\n", name);
- kfree(prop_node);
- return;
- }
- priv->cp_property[feature] = prop;
- }
-
- INIT_PROP_ATTACH(&prop_attach, crtc, prop, prop_node,
- feature, val);
-
- dpu_cp_crtc_prop_attach(&prop_attach);
-}
-
-static void dpu_cp_crtc_setfeature(struct dpu_cp_node *prop_node,
- struct dpu_crtc *dpu_crtc)
-{
- struct dpu_hw_cp_cfg hw_cfg;
- struct dpu_hw_mixer *hw_lm;
- struct dpu_hw_dspp *hw_dspp;
- u32 num_mixers = dpu_crtc->num_mixers;
- int i = 0;
- bool feature_enabled = false;
- int ret = 0;
- struct dpu_ad_hw_cfg ad_cfg;
-
- dpu_cp_get_hw_payload(prop_node, &hw_cfg, &feature_enabled);
- hw_cfg.num_of_mixers = dpu_crtc->num_mixers;
- hw_cfg.displayh = dpu_crtc->base.mode.hdisplay;
- hw_cfg.displayv = dpu_crtc->base.mode.vdisplay;
- hw_cfg.last_feature = 0;
-
- for (i = 0; i < num_mixers && !ret; i++) {
- hw_lm = dpu_crtc->mixers[i].hw_lm;
- hw_dspp = dpu_crtc->mixers[i].hw_dspp;
- hw_cfg.ctl = dpu_crtc->mixers[i].hw_ctl;
- hw_cfg.mixer_info = hw_lm;
- switch (prop_node->feature) {
- case DPU_CP_CRTC_DSPP_VLUT:
- if (!hw_dspp || !hw_dspp->ops.setup_vlut) {
- ret = -EINVAL;
- continue;
- }
- hw_dspp->ops.setup_vlut(hw_dspp, &hw_cfg);
- break;
- case DPU_CP_CRTC_DSPP_PCC:
- if (!hw_dspp || !hw_dspp->ops.setup_pcc) {
- ret = -EINVAL;
- continue;
- }
- hw_dspp->ops.setup_pcc(hw_dspp, &hw_cfg);
- break;
- case DPU_CP_CRTC_DSPP_IGC:
- if (!hw_dspp || !hw_dspp->ops.setup_igc) {
- ret = -EINVAL;
- continue;
- }
- hw_dspp->ops.setup_igc(hw_dspp, &hw_cfg);
- break;
- case DPU_CP_CRTC_DSPP_GC:
- if (!hw_dspp || !hw_dspp->ops.setup_gc) {
- ret = -EINVAL;
- continue;
- }
- hw_dspp->ops.setup_gc(hw_dspp, &hw_cfg);
- break;
- case DPU_CP_CRTC_DSPP_HUE:
- if (!hw_dspp || !hw_dspp->ops.setup_hue) {
- ret = -EINVAL;
- continue;
- }
- hw_dspp->ops.setup_hue(hw_dspp, &hw_cfg);
- break;
- case DPU_CP_CRTC_DSPP_SAT:
- if (!hw_dspp || !hw_dspp->ops.setup_sat) {
- ret = -EINVAL;
- continue;
- }
- hw_dspp->ops.setup_sat(hw_dspp, &hw_cfg);
- break;
- case DPU_CP_CRTC_DSPP_VAL:
- if (!hw_dspp || !hw_dspp->ops.setup_val) {
- ret = -EINVAL;
- continue;
- }
- hw_dspp->ops.setup_val(hw_dspp, &hw_cfg);
- break;
- case DPU_CP_CRTC_DSPP_CONT:
- if (!hw_dspp || !hw_dspp->ops.setup_cont) {
- ret = -EINVAL;
- continue;
- }
- hw_dspp->ops.setup_cont(hw_dspp, &hw_cfg);
- break;
- case DPU_CP_CRTC_DSPP_MEMCOLOR:
- if (!hw_dspp || !hw_dspp->ops.setup_pa_memcolor) {
- ret = -EINVAL;
- continue;
- }
- hw_dspp->ops.setup_pa_memcolor(hw_dspp, &hw_cfg);
- break;
- case DPU_CP_CRTC_DSPP_SIXZONE:
- if (!hw_dspp || !hw_dspp->ops.setup_sixzone) {
- ret = -EINVAL;
- continue;
- }
- hw_dspp->ops.setup_sixzone(hw_dspp, &hw_cfg);
- break;
- case DPU_CP_CRTC_DSPP_GAMUT:
- if (!hw_dspp || !hw_dspp->ops.setup_gamut) {
- ret = -EINVAL;
- continue;
- }
- hw_dspp->ops.setup_gamut(hw_dspp, &hw_cfg);
- break;
- case DPU_CP_CRTC_LM_GC:
- if (!hw_lm || !hw_lm->ops.setup_gc) {
- ret = -EINVAL;
- continue;
- }
- hw_lm->ops.setup_gc(hw_lm, &hw_cfg);
- break;
- case DPU_CP_CRTC_DSPP_AD_MODE:
- if (!hw_dspp || !hw_dspp->ops.setup_ad) {
- ret = -EINVAL;
- continue;
- }
- ad_cfg.prop = AD_MODE;
- ad_cfg.hw_cfg = &hw_cfg;
- hw_dspp->ops.setup_ad(hw_dspp, &ad_cfg);
- break;
- case DPU_CP_CRTC_DSPP_AD_INIT:
- if (!hw_dspp || !hw_dspp->ops.setup_ad) {
- ret = -EINVAL;
- continue;
- }
- ad_cfg.prop = AD_INIT;
- ad_cfg.hw_cfg = &hw_cfg;
- hw_dspp->ops.setup_ad(hw_dspp, &ad_cfg);
- break;
- case DPU_CP_CRTC_DSPP_AD_CFG:
- if (!hw_dspp || !hw_dspp->ops.setup_ad) {
- ret = -EINVAL;
- continue;
- }
- ad_cfg.prop = AD_CFG;
- ad_cfg.hw_cfg = &hw_cfg;
- hw_dspp->ops.setup_ad(hw_dspp, &ad_cfg);
- break;
- case DPU_CP_CRTC_DSPP_AD_INPUT:
- if (!hw_dspp || !hw_dspp->ops.setup_ad) {
- ret = -EINVAL;
- continue;
- }
- ad_cfg.prop = AD_INPUT;
- ad_cfg.hw_cfg = &hw_cfg;
- hw_dspp->ops.setup_ad(hw_dspp, &ad_cfg);
- break;
- case DPU_CP_CRTC_DSPP_AD_ASSERTIVENESS:
- if (!hw_dspp || !hw_dspp->ops.setup_ad) {
- ret = -EINVAL;
- continue;
- }
- ad_cfg.prop = AD_ASSERTIVE;
- ad_cfg.hw_cfg = &hw_cfg;
- hw_dspp->ops.setup_ad(hw_dspp, &ad_cfg);
- break;
- case DPU_CP_CRTC_DSPP_AD_BACKLIGHT:
- if (!hw_dspp || !hw_dspp->ops.setup_ad) {
- ret = -EINVAL;
- continue;
- }
- ad_cfg.prop = AD_BACKLIGHT;
- ad_cfg.hw_cfg = &hw_cfg;
- hw_dspp->ops.setup_ad(hw_dspp, &ad_cfg);
- break;
- default:
- ret = -EINVAL;
- break;
- }
- }
-
- if (ret) {
- DRM_ERROR("failed to %s feature %d\n",
- ((feature_enabled) ? "enable" : "disable"),
- prop_node->feature);
- return;
- }
-
- if (feature_enabled) {
- DRM_DEBUG_DRIVER("Add feature to active list %d\n",
- prop_node->property_id);
- dpu_cp_update_list(prop_node, dpu_crtc, false);
- } else {
- DRM_DEBUG_DRIVER("remove feature from active list %d\n",
- prop_node->property_id);
- list_del_init(&prop_node->active_list);
- }
- /* Programming of feature done remove from dirty list */
- list_del_init(&prop_node->dirty_list);
-}
-
-void dpu_cp_crtc_apply_properties(struct drm_crtc *crtc)
-{
- struct dpu_crtc *dpu_crtc = NULL;
- bool set_dspp_flush = false, set_lm_flush = false;
- struct dpu_cp_node *prop_node = NULL, *n = NULL;
- struct dpu_hw_ctl *ctl;
- uint32_t flush_mask = 0;
- u32 num_mixers = 0, i = 0;
-
- if (!crtc || !crtc->dev) {
- DRM_ERROR("invalid crtc %pK dev %pK\n", crtc,
- (crtc ? crtc->dev : NULL));
- return;
- }
-
- dpu_crtc = to_dpu_crtc(crtc);
- if (!dpu_crtc) {
- DRM_ERROR("invalid dpu_crtc %pK\n", dpu_crtc);
- return;
- }
-
- num_mixers = dpu_crtc->num_mixers;
- if (!num_mixers) {
- DRM_DEBUG_DRIVER("no mixers for this crtc\n");
- return;
- }
-
- /* Check if dirty lists are empty and ad features are disabled for
- * early return. If ad properties are active then we need to issue
- * dspp flush.
- **/
- if (list_empty(&dpu_crtc->dirty_list) &&
- list_empty(&dpu_crtc->ad_dirty)) {
- if (list_empty(&dpu_crtc->ad_active)) {
- DRM_DEBUG_DRIVER("Dirty list is empty\n");
- return;
- }
- dpu_cp_ad_set_prop(dpu_crtc, AD_IPC_RESET);
- set_dspp_flush = true;
- }
-
- list_for_each_entry_safe(prop_node, n, &dpu_crtc->dirty_list,
- dirty_list) {
- dpu_cp_crtc_setfeature(prop_node, dpu_crtc);
- /* Set the flush flag to true */
- if (prop_node->is_dspp_feature)
- set_dspp_flush = true;
- else
- set_lm_flush = true;
- }
-
- list_for_each_entry_safe(prop_node, n, &dpu_crtc->ad_dirty,
- dirty_list) {
- set_dspp_flush = true;
- dpu_cp_crtc_setfeature(prop_node, dpu_crtc);
- }
-
- for (i = 0; i < num_mixers; i++) {
- ctl = dpu_crtc->mixers[i].hw_ctl;
- if (!ctl)
- continue;
- if (set_dspp_flush && ctl->ops.get_bitmask_dspp
- && dpu_crtc->mixers[i].hw_dspp) {
- ctl->ops.get_bitmask_dspp(ctl,
- &flush_mask,
- dpu_crtc->mixers[i].hw_dspp->idx);
- ctl->ops.update_pending_flush(ctl, flush_mask);
- }
- if (set_lm_flush && ctl->ops.get_bitmask_mixer
- && dpu_crtc->mixers[i].hw_lm) {
- flush_mask = ctl->ops.get_bitmask_mixer(ctl,
- dpu_crtc->mixers[i].hw_lm->idx);
- ctl->ops.update_pending_flush(ctl, flush_mask);
- }
- }
-}
-
-void dpu_cp_crtc_install_properties(struct drm_crtc *crtc)
-{
- struct dpu_kms *kms = NULL;
- struct dpu_crtc *dpu_crtc = NULL;
- struct dpu_mdss_cfg *catalog = NULL;
- unsigned long features = 0;
- int i = 0;
- struct msm_drm_private *priv;
-
- if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
- DRM_ERROR("invalid crtc %pK dev %pK\n",
- crtc, ((crtc) ? crtc->dev : NULL));
- return;
- }
-
- dpu_crtc = to_dpu_crtc(crtc);
- if (!dpu_crtc) {
- DRM_ERROR("dpu_crtc %pK\n", dpu_crtc);
- return;
- }
-
- kms = get_kms(crtc);
- if (!kms || !kms->catalog) {
- DRM_ERROR("invalid dpu kms %pK catalog %pK dpu_crtc %pK\n",
- kms, ((kms) ? kms->catalog : NULL), dpu_crtc);
- return;
- }
-
- /**
- * Function can be called during the atomic_check with test_only flag
- * and actual commit. Allocate properties only if feature list is
- * empty during the atomic_check with test_only flag.
- */
- if (!list_empty(&dpu_crtc->feature_list))
- return;
-
- catalog = kms->catalog;
- priv = crtc->dev->dev_private;
- /**
- * DSPP/LM properties are global to all the CRTCS.
- * Properties are created for first CRTC and re-used for later
- * crtcs.
- */
- if (!priv->cp_property) {
- priv->cp_property = kzalloc((sizeof(priv->cp_property) *
- DPU_CP_CRTC_MAX_FEATURES), GFP_KERNEL);
- setup_dspp_prop_install_funcs(dspp_prop_install_func);
- setup_lm_prop_install_funcs(lm_prop_install_func);
- }
- if (!priv->cp_property)
- return;
-
- if (!catalog->dspp_count)
- goto lm_property;
-
- /* Check for all the DSPP properties and attach it to CRTC */
- features = catalog->dspp[0].features;
- for (i = 0; i < DPU_DSPP_MAX; i++) {
- if (!test_bit(i, &features))
- continue;
- if (dspp_prop_install_func[i])
- dspp_prop_install_func[i](crtc);
- }
-
-lm_property:
- if (!catalog->mixer_count)
- return;
-
- /* Check for all the LM properties and attach it to CRTC */
- features = catalog->mixer[0].features;
- for (i = 0; i < DPU_MIXER_MAX; i++) {
- if (!test_bit(i, &features))
- continue;
- if (lm_prop_install_func[i])
- lm_prop_install_func[i](crtc);
- }
-}
-
-int dpu_cp_crtc_set_property(struct drm_crtc *crtc,
- struct drm_property *property,
- uint64_t val)
-{
- struct dpu_cp_node *prop_node = NULL;
- struct dpu_crtc *dpu_crtc = NULL;
- int ret = 0, i = 0, dspp_cnt, lm_cnt;
- u8 found = 0;
-
- if (!crtc || !property) {
- DRM_ERROR("invalid crtc %pK property %pK\n", crtc, property);
- return -EINVAL;
- }
-
- dpu_crtc = to_dpu_crtc(crtc);
- if (!dpu_crtc) {
- DRM_ERROR("invalid dpu_crtc %pK\n", dpu_crtc);
- return -EINVAL;
- }
-
- list_for_each_entry(prop_node, &dpu_crtc->feature_list, feature_list) {
- if (property->base.id == prop_node->property_id) {
- found = 1;
- break;
- }
- }
-
- if (!found)
- return 0;
- /**
- * dpu_crtc is virtual ensure that hardware has been attached to the
- * crtc. Check LM and dspp counts based on whether feature is a
- * dspp/lm feature.
- */
- if (!dpu_crtc->num_mixers ||
- dpu_crtc->num_mixers > ARRAY_SIZE(dpu_crtc->mixers)) {
- DRM_ERROR("Invalid mixer config act cnt %d max cnt %zd\n",
- dpu_crtc->num_mixers, ARRAY_SIZE(dpu_crtc->mixers));
- return -EINVAL;
- }
-
- dspp_cnt = 0;
- lm_cnt = 0;
- for (i = 0; i < dpu_crtc->num_mixers; i++) {
- if (dpu_crtc->mixers[i].hw_dspp)
- dspp_cnt++;
- if (dpu_crtc->mixers[i].hw_lm)
- lm_cnt++;
- }
-
- if (prop_node->is_dspp_feature && dspp_cnt < dpu_crtc->num_mixers) {
- DRM_ERROR("invalid dspp cnt %d mixer cnt %d\n", dspp_cnt,
- dpu_crtc->num_mixers);
- return -EINVAL;
- } else if (lm_cnt < dpu_crtc->num_mixers) {
- DRM_ERROR("invalid lm cnt %d mixer cnt %d\n", lm_cnt,
- dpu_crtc->num_mixers);
- return -EINVAL;
- }
-
- ret = dpu_cp_ad_validate_prop(prop_node, dpu_crtc);
- if (ret) {
- DRM_ERROR("ad property validation failed ret %d\n", ret);
- return ret;
- }
-
- /* remove the property from dirty list */
- list_del_init(&prop_node->dirty_list);
-
- if (!val)
- ret = dpu_cp_disable_crtc_property(crtc, property, prop_node);
- else
- ret = dpu_cp_enable_crtc_property(crtc, property,
- prop_node, val);
-
- if (!ret) {
- /* remove the property from active list */
- list_del_init(&prop_node->active_list);
- /* Mark the feature as dirty */
- dpu_cp_update_list(prop_node, dpu_crtc, true);
- }
- return ret;
-}
-
-int dpu_cp_crtc_get_property(struct drm_crtc *crtc,
- struct drm_property *property, uint64_t *val)
-{
- struct dpu_cp_node *prop_node = NULL;
- struct dpu_crtc *dpu_crtc = NULL;
-
- if (!crtc || !property || !val) {
- DRM_ERROR("invalid crtc %pK property %pK val %pK\n",
- crtc, property, val);
- return -EINVAL;
- }
-
- dpu_crtc = to_dpu_crtc(crtc);
- if (!dpu_crtc) {
- DRM_ERROR("invalid dpu_crtc %pK\n", dpu_crtc);
- return -EINVAL;
- }
- /* Return 0 if property is not supported */
- *val = 0;
- list_for_each_entry(prop_node, &dpu_crtc->feature_list, feature_list) {
- if (property->base.id == prop_node->property_id) {
- *val = prop_node->prop_val;
- break;
- }
- }
- return 0;
-}
-
-void dpu_cp_crtc_destroy_properties(struct drm_crtc *crtc)
-{
- struct dpu_crtc *dpu_crtc = NULL;
- struct dpu_cp_node *prop_node = NULL, *n = NULL;
-
- if (!crtc) {
- DRM_ERROR("invalid crtc %pK\n", crtc);
- return;
- }
-
- dpu_crtc = to_dpu_crtc(crtc);
- if (!dpu_crtc) {
- DRM_ERROR("invalid dpu_crtc %pK\n", dpu_crtc);
- return;
- }
-
- list_for_each_entry_safe(prop_node, n, &dpu_crtc->feature_list,
- feature_list) {
- if (prop_node->prop_flags & DRM_MODE_PROP_BLOB
- && prop_node->blob_ptr)
- drm_property_blob_put(prop_node->blob_ptr);
-
- list_del_init(&prop_node->active_list);
- list_del_init(&prop_node->dirty_list);
- list_del_init(&prop_node->feature_list);
- dpu_cp_destroy_local_blob(prop_node);
- kfree(prop_node);
- }
-
- INIT_LIST_HEAD(&dpu_crtc->active_list);
- INIT_LIST_HEAD(&dpu_crtc->dirty_list);
- INIT_LIST_HEAD(&dpu_crtc->feature_list);
-}
-
-void dpu_cp_crtc_suspend(struct drm_crtc *crtc)
-{
- struct dpu_crtc *dpu_crtc = NULL;
- struct dpu_cp_node *prop_node = NULL, *n = NULL;
-
- if (!crtc) {
- DRM_ERROR("crtc %pK\n", crtc);
- return;
- }
- dpu_crtc = to_dpu_crtc(crtc);
- if (!dpu_crtc) {
- DRM_ERROR("dpu_crtc %pK\n", dpu_crtc);
- return;
- }
-
- list_for_each_entry_safe(prop_node, n, &dpu_crtc->active_list,
- active_list) {
- dpu_cp_update_list(prop_node, dpu_crtc, true);
- list_del_init(&prop_node->active_list);
- }
-
- list_for_each_entry_safe(prop_node, n, &dpu_crtc->ad_active,
- active_list) {
- dpu_cp_update_list(prop_node, dpu_crtc, true);
- list_del_init(&prop_node->active_list);
- }
-}
-
-void dpu_cp_crtc_resume(struct drm_crtc *crtc)
-{
- /* placeholder for operations needed during resume */
-}
-
-static void dspp_pcc_install_property(struct drm_crtc *crtc)
-{
- char feature_name[256];
- struct dpu_kms *kms = NULL;
- struct dpu_mdss_cfg *catalog = NULL;
- u32 version;
-
- kms = get_kms(crtc);
- catalog = kms->catalog;
-
- version = catalog->dspp[0].sblk->pcc.version >> 16;
- snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
- "DPU_DSPP_PCC_V", version);
- switch (version) {
- case 1:
- case 4:
- dpu_cp_crtc_install_blob_property(crtc, feature_name,
- DPU_CP_CRTC_DSPP_PCC, sizeof(struct drm_msm_pcc));
- break;
- default:
- DRM_ERROR("version %d not supported\n", version);
- break;
- }
-}
-
-static void dspp_hsic_install_property(struct drm_crtc *crtc)
-{
- char feature_name[256];
- struct dpu_kms *kms = NULL;
- struct dpu_mdss_cfg *catalog = NULL;
- u32 version;
-
- kms = get_kms(crtc);
- catalog = kms->catalog;
- version = catalog->dspp[0].sblk->hsic.version >> 16;
- switch (version) {
- case 1:
- snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
- "DPU_DSPP_HUE_V", version);
- dpu_cp_crtc_install_range_property(crtc, feature_name,
- DPU_CP_CRTC_DSPP_HUE, 0, U32_MAX, 0);
- break;
- default:
- DRM_ERROR("version %d not supported\n", version);
- break;
- }
-}
-
-static void dspp_vlut_install_property(struct drm_crtc *crtc)
-{
- char feature_name[256];
- struct dpu_kms *kms = NULL;
- struct dpu_mdss_cfg *catalog = NULL;
- u32 version;
-
- kms = get_kms(crtc);
- catalog = kms->catalog;
- version = catalog->dspp[0].sblk->vlut.version >> 16;
- snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
- "DPU_DSPP_VLUT_V", version);
- switch (version) {
- case 1:
- dpu_cp_crtc_install_range_property(crtc, feature_name,
- DPU_CP_CRTC_DSPP_VLUT, 0, U64_MAX, 0);
- dpu_cp_create_local_blob(crtc,
- DPU_CP_CRTC_DSPP_VLUT,
- sizeof(struct drm_msm_pa_vlut));
- break;
- default:
- DRM_ERROR("version %d not supported\n", version);
- break;
- }
-}
-
-static void dspp_ad_install_property(struct drm_crtc *crtc)
-{
- char feature_name[256];
- struct dpu_kms *kms = NULL;
- struct dpu_mdss_cfg *catalog = NULL;
- u32 version;
-
- kms = get_kms(crtc);
- catalog = kms->catalog;
- version = catalog->dspp[0].sblk->ad.version >> 16;
- snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
- "DPU_DSPP_AD_V", version);
- switch (version) {
- case 3:
- dpu_cp_crtc_install_immutable_property(crtc,
- feature_name, DPU_CP_CRTC_DSPP_AD);
- break;
- case 4:
- dpu_cp_crtc_install_immutable_property(crtc,
- feature_name, DPU_CP_CRTC_DSPP_AD);
-
- dpu_cp_crtc_install_enum_property(crtc,
- DPU_CP_CRTC_DSPP_AD_MODE, ad4_modes,
- ARRAY_SIZE(ad4_modes), "DPU_DSPP_AD_V4_MODE");
-
- dpu_cp_crtc_install_range_property(crtc, "DPU_DSPP_AD_V4_INIT",
- DPU_CP_CRTC_DSPP_AD_INIT, 0, U64_MAX, 0);
- dpu_cp_create_local_blob(crtc, DPU_CP_CRTC_DSPP_AD_INIT,
- sizeof(struct drm_msm_ad4_init));
-
- dpu_cp_crtc_install_range_property(crtc, "DPU_DSPP_AD_V4_CFG",
- DPU_CP_CRTC_DSPP_AD_CFG, 0, U64_MAX, 0);
- dpu_cp_create_local_blob(crtc, DPU_CP_CRTC_DSPP_AD_CFG,
- sizeof(struct drm_msm_ad4_cfg));
- dpu_cp_crtc_install_range_property(crtc,
- "DPU_DSPP_AD_V4_ASSERTIVENESS",
- DPU_CP_CRTC_DSPP_AD_ASSERTIVENESS, 0, (BIT(8) - 1), 0);
- dpu_cp_crtc_install_range_property(crtc, "DPU_DSPP_AD_V4_INPUT",
- DPU_CP_CRTC_DSPP_AD_INPUT, 0, U16_MAX, 0);
- dpu_cp_crtc_install_range_property(crtc,
- "DPU_DSPP_AD_V4_BACKLIGHT",
- DPU_CP_CRTC_DSPP_AD_BACKLIGHT, 0, (BIT(16) - 1),
- 0);
- break;
- default:
- DRM_ERROR("version %d not supported\n", version);
- break;
- }
-}
-
-static void lm_gc_install_property(struct drm_crtc *crtc)
-{
- char feature_name[256];
- struct dpu_kms *kms = NULL;
- struct dpu_mdss_cfg *catalog = NULL;
- u32 version;
-
- kms = get_kms(crtc);
- catalog = kms->catalog;
- version = catalog->mixer[0].sblk->gc.version >> 16;
- snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
- "DPU_LM_GC_V", version);
- switch (version) {
- case 1:
- dpu_cp_crtc_install_blob_property(crtc, feature_name,
- DPU_CP_CRTC_LM_GC, sizeof(struct drm_msm_pgc_lut));
- break;
- default:
- DRM_ERROR("version %d not supported\n", version);
- break;
- }
-}
-
-static void dspp_gamut_install_property(struct drm_crtc *crtc)
-{
- char feature_name[256];
- struct dpu_kms *kms = NULL;
- struct dpu_mdss_cfg *catalog = NULL;
- u32 version;
-
- kms = get_kms(crtc);
- catalog = kms->catalog;
-
- version = catalog->dspp[0].sblk->gamut.version >> 16;
- snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
- "DPU_DSPP_GAMUT_V", version);
- switch (version) {
- case 4:
- dpu_cp_crtc_install_blob_property(crtc, feature_name,
- DPU_CP_CRTC_DSPP_GAMUT,
- sizeof(struct drm_msm_3d_gamut));
- break;
- default:
- DRM_ERROR("version %d not supported\n", version);
- break;
- }
-}
-
-static void dspp_gc_install_property(struct drm_crtc *crtc)
-{
- char feature_name[256];
- struct dpu_kms *kms = NULL;
- struct dpu_mdss_cfg *catalog = NULL;
- u32 version;
-
- kms = get_kms(crtc);
- catalog = kms->catalog;
-
- version = catalog->dspp[0].sblk->gc.version >> 16;
- snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
- "DPU_DSPP_GC_V", version);
- switch (version) {
- case 1:
- dpu_cp_crtc_install_blob_property(crtc, feature_name,
- DPU_CP_CRTC_DSPP_GC, sizeof(struct drm_msm_pgc_lut));
- break;
- default:
- DRM_ERROR("version %d not supported\n", version);
- break;
- }
-}
-
-static void dspp_igc_install_property(struct drm_crtc *crtc)
-{
- char feature_name[256];
- struct dpu_kms *kms = NULL;
- struct dpu_mdss_cfg *catalog = NULL;
- u32 version;
-
- kms = get_kms(crtc);
- catalog = kms->catalog;
-
- version = catalog->dspp[0].sblk->igc.version >> 16;
- snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
- "DPU_DSPP_IGC_V", version);
- switch (version) {
- case 3:
- dpu_cp_crtc_install_blob_property(crtc, feature_name,
- DPU_CP_CRTC_DSPP_IGC, sizeof(struct drm_msm_igc_lut));
- break;
- default:
- DRM_ERROR("version %d not supported\n", version);
- break;
- }
-}
-
-static void dpu_cp_update_list(struct dpu_cp_node *prop_node,
- struct dpu_crtc *crtc, bool dirty_list)
-{
- switch (prop_node->feature) {
- case DPU_CP_CRTC_DSPP_AD_MODE:
- case DPU_CP_CRTC_DSPP_AD_INIT:
- case DPU_CP_CRTC_DSPP_AD_CFG:
- case DPU_CP_CRTC_DSPP_AD_INPUT:
- case DPU_CP_CRTC_DSPP_AD_ASSERTIVENESS:
- case DPU_CP_CRTC_DSPP_AD_BACKLIGHT:
- if (dirty_list)
- list_add_tail(&prop_node->dirty_list, &crtc->ad_dirty);
- else
- list_add_tail(&prop_node->active_list,
- &crtc->ad_active);
- break;
- default:
- /* color processing properties handle here */
- if (dirty_list)
- list_add_tail(&prop_node->dirty_list,
- &crtc->dirty_list);
- else
- list_add_tail(&prop_node->active_list,
- &crtc->active_list);
- break;
- };
-}
-
-static int dpu_cp_ad_validate_prop(struct dpu_cp_node *prop_node,
- struct dpu_crtc *crtc)
-{
- int i = 0, ret = 0;
- u32 ad_prop;
-
- for (i = 0; i < crtc->num_mixers && !ret; i++) {
- if (!crtc->mixers[i].hw_dspp) {
- ret = -EINVAL;
- continue;
- }
- switch (prop_node->feature) {
- case DPU_CP_CRTC_DSPP_AD_MODE:
- ad_prop = AD_MODE;
- break;
- case DPU_CP_CRTC_DSPP_AD_INIT:
- ad_prop = AD_INIT;
- break;
- case DPU_CP_CRTC_DSPP_AD_CFG:
- ad_prop = AD_CFG;
- break;
- case DPU_CP_CRTC_DSPP_AD_INPUT:
- ad_prop = AD_INPUT;
- break;
- case DPU_CP_CRTC_DSPP_AD_ASSERTIVENESS:
- ad_prop = AD_ASSERTIVE;
- break;
- case DPU_CP_CRTC_DSPP_AD_BACKLIGHT:
- ad_prop = AD_BACKLIGHT;
- break;
- default:
- /* Not an AD property */
- return 0;
- }
- if (!crtc->mixers[i].hw_dspp->ops.validate_ad)
- ret = -EINVAL;
- else
- ret = crtc->mixers[i].hw_dspp->ops.validate_ad(
- crtc->mixers[i].hw_dspp, &ad_prop);
- }
- return ret;
-}
-
-static void dpu_cp_ad_interrupt_cb(void *arg, int irq_idx)
-{
- struct dpu_crtc *crtc = arg;
-
- dpu_crtc_event_queue(&crtc->base, dpu_cp_notify_ad_event, NULL);
-}
-
-static void dpu_cp_notify_ad_event(struct drm_crtc *crtc_drm, void *arg)
-{
- uint32_t bl = 0;
- struct dpu_hw_mixer *hw_lm = NULL;
- struct dpu_hw_dspp *hw_dspp = NULL;
- u32 num_mixers;
- struct dpu_crtc *crtc;
- struct drm_event event;
- int i;
-
- crtc = to_dpu_crtc(crtc_drm);
- num_mixers = crtc->num_mixers;
- if (!num_mixers)
- return;
-
- for (i = 0; i < num_mixers; i++) {
- hw_lm = crtc->mixers[i].hw_lm;
- hw_dspp = crtc->mixers[i].hw_dspp;
- if (!hw_lm->cfg.right_mixer)
- break;
- }
-
- if (!hw_dspp)
- return;
-
- hw_dspp->ops.ad_read_intr_resp(hw_dspp, AD4_BACKLIGHT, &bl);
- event.length = sizeof(u32);
- event.type = DRM_EVENT_AD_BACKLIGHT;
- msm_mode_object_event_notify(&crtc_drm->base, crtc_drm->dev,
- &event, (u8 *)&bl);
-}
-
-int dpu_cp_ad_interrupt(struct drm_crtc *crtc_drm, bool en,
- struct dpu_irq_callback *ad_irq)
-{
- struct dpu_kms *kms = NULL;
- u32 num_mixers;
- struct dpu_hw_mixer *hw_lm;
- struct dpu_hw_dspp *hw_dspp = NULL;
- struct dpu_crtc *crtc;
- int i;
- int irq_idx, ret;
- struct dpu_cp_node prop_node;
-
- if (!crtc_drm || !ad_irq) {
- DRM_ERROR("invalid crtc %pK irq %pK\n", crtc_drm, ad_irq);
- return -EINVAL;
- }
-
- crtc = to_dpu_crtc(crtc_drm);
- if (!crtc) {
- DRM_ERROR("invalid dpu_crtc %pK\n", crtc);
- return -EINVAL;
- }
-
- kms = get_kms(crtc_drm);
- num_mixers = crtc->num_mixers;
-
- memset(&prop_node, 0, sizeof(prop_node));
- prop_node.feature = DPU_CP_CRTC_DSPP_AD_BACKLIGHT;
- ret = dpu_cp_ad_validate_prop(&prop_node, crtc);
- if (ret) {
- DRM_ERROR("Ad not supported ret %d\n", ret);
- goto exit;
- }
-
- for (i = 0; i < num_mixers; i++) {
- hw_lm = crtc->mixers[i].hw_lm;
- hw_dspp = crtc->mixers[i].hw_dspp;
- if (!hw_lm->cfg.right_mixer)
- break;
- }
-
- if (!hw_dspp) {
- DRM_ERROR("invalid dspp\n");
- ret = -EINVAL;
- goto exit;
- }
-
- irq_idx = dpu_core_irq_idx_lookup(kms, DPU_IRQ_TYPE_AD4_BL_DONE,
- hw_dspp->idx);
- if (irq_idx < 0) {
- DRM_ERROR("failed to get the irq idx ret %d\n", irq_idx);
- ret = irq_idx;
- goto exit;
- }
-
- if (!en) {
- dpu_core_irq_disable(kms, &irq_idx, 1);
- dpu_core_irq_unregister_callback(kms, irq_idx, ad_irq);
- ret = 0;
- goto exit;
- }
-
- ad_irq->arg = crtc;
- ad_irq->func = dpu_cp_ad_interrupt_cb;
- ret = dpu_core_irq_register_callback(kms, irq_idx, ad_irq);
- if (ret) {
- DRM_ERROR("failed to register the callback ret %d\n", ret);
- goto exit;
- }
- ret = dpu_core_irq_enable(kms, &irq_idx, 1);
- if (ret) {
- DRM_ERROR("failed to enable irq ret %d\n", ret);
- dpu_core_irq_unregister_callback(kms, irq_idx, ad_irq);
- }
-exit:
- return ret;
-}
-
-static void dpu_cp_ad_set_prop(struct dpu_crtc *dpu_crtc,
- enum ad_property ad_prop)
-{
- struct dpu_ad_hw_cfg ad_cfg;
- struct dpu_hw_cp_cfg hw_cfg;
- struct dpu_hw_dspp *hw_dspp = NULL;
- struct dpu_hw_mixer *hw_lm = NULL;
- u32 num_mixers = dpu_crtc->num_mixers;
- int i = 0, ret = 0;
-
- hw_cfg.num_of_mixers = dpu_crtc->num_mixers;
- hw_cfg.displayh = dpu_crtc->base.mode.hdisplay;
- hw_cfg.displayv = dpu_crtc->base.mode.vdisplay;
-
- for (i = 0; i < num_mixers && !ret; i++) {
- hw_lm = dpu_crtc->mixers[i].hw_lm;
- hw_dspp = dpu_crtc->mixers[i].hw_dspp;
- if (!hw_lm || !hw_dspp || !hw_dspp->ops.validate_ad ||
- !hw_dspp->ops.setup_ad) {
- ret = -EINVAL;
- continue;
- }
-
- hw_cfg.mixer_info = hw_lm;
- ad_cfg.prop = ad_prop;
- ad_cfg.hw_cfg = &hw_cfg;
- ret = hw_dspp->ops.validate_ad(hw_dspp, (u32 *)&ad_prop);
- if (!ret)
- hw_dspp->ops.setup_ad(hw_dspp, &ad_cfg);
- }
-}
-
-void dpu_cp_crtc_pre_ipc(struct drm_crtc *drm_crtc)
-{
- struct dpu_crtc *dpu_crtc;
-
- dpu_crtc = to_dpu_crtc(drm_crtc);
- if (!dpu_crtc) {
- DRM_ERROR("invalid dpu_crtc %pK\n", dpu_crtc);
- return;
- }
-
- dpu_cp_ad_set_prop(dpu_crtc, AD_IPC_SUSPEND);
-}
-
-void dpu_cp_crtc_post_ipc(struct drm_crtc *drm_crtc)
-{
- struct dpu_crtc *dpu_crtc;
-
- dpu_crtc = to_dpu_crtc(drm_crtc);
- if (!dpu_crtc) {
- DRM_ERROR("invalid dpu_crtc %pK\n", dpu_crtc);
- return;
- }
-
- dpu_cp_ad_set_prop(dpu_crtc, AD_IPC_RESUME);
-}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.h
deleted file mode 100644
index 0fa546c..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _DPU_COLOR_PROCESSING_H
-#define _DPU_COLOR_PROCESSING_H
-#include <drm/drm_crtc.h>
-
-struct dpu_irq_callback;
-
-/*
- * PA MEMORY COLOR types
- * @MEMCOLOR_SKIN Skin memory color type
- * @MEMCOLOR_SKY Sky memory color type
- * @MEMCOLOR_FOLIAGE Foliage memory color type
- */
-enum dpu_memcolor_type {
- MEMCOLOR_SKIN = 0,
- MEMCOLOR_SKY,
- MEMCOLOR_FOLIAGE
-};
-
-/**
- * dpu_cp_crtc_init(): Initialize color processing lists for a crtc.
- * Should be called during crtc initialization.
- * @crtc: Pointer to dpu_crtc.
- */
-void dpu_cp_crtc_init(struct drm_crtc *crtc);
-
-/**
- * dpu_cp_crtc_install_properties(): Installs the color processing
- * properties for a crtc.
- * Should be called during crtc initialization.
- * @crtc: Pointer to crtc.
- */
-void dpu_cp_crtc_install_properties(struct drm_crtc *crtc);
-
-/**
- * dpu_cp_crtc_destroy_properties: Destroys color processing
- * properties for a crtc.
- * should be called during crtc de-initialization.
- * @crtc: Pointer to crtc.
- */
-void dpu_cp_crtc_destroy_properties(struct drm_crtc *crtc);
-
-/**
- * dpu_cp_crtc_set_property: Set a color processing property
- * for a crtc.
- * Should be during atomic set property.
- * @crtc: Pointer to crtc.
- * @property: Property that needs to enabled/disabled.
- * @val: Value of property.
- */
-int dpu_cp_crtc_set_property(struct drm_crtc *crtc,
- struct drm_property *property, uint64_t val);
-
-/**
- * dpu_cp_crtc_apply_properties: Enable/disable properties
- * for a crtc.
- * Should be called during atomic commit call.
- * @crtc: Pointer to crtc.
- */
-void dpu_cp_crtc_apply_properties(struct drm_crtc *crtc);
-
-/**
- * dpu_cp_crtc_get_property: Get value of color processing property
- * for a crtc.
- * Should be during atomic get property.
- * @crtc: Pointer to crtc.
- * @property: Property that needs to enabled/disabled.
- * @val: Value of property.
- *
- */
-int dpu_cp_crtc_get_property(struct drm_crtc *crtc,
- struct drm_property *property, uint64_t *val);
-
-/**
- * dpu_cp_crtc_suspend: Suspend the crtc features
- * @crtc: Pointer to crtc.
- */
-void dpu_cp_crtc_suspend(struct drm_crtc *crtc);
-
-/**
- * dpu_cp_crtc_resume: Resume the crtc features
- * @crtc: Pointer to crtc.
- */
-void dpu_cp_crtc_resume(struct drm_crtc *crtc);
-
-/**
- * dpu_cp_ad_interrupt: Api to enable/disable ad interrupt
- * @crtc: Pointer to crtc.
- * @en: Variable to enable/disable interrupt.
- * @irq: Pointer to irq callback
- */
-int dpu_cp_ad_interrupt(struct drm_crtc *crtc, bool en,
- struct dpu_irq_callback *irq);
-
-/**
- * dpu_cp_crtc_pre_ipc: Handle color processing features
- * before entering IPC
- * @crtc: Pointer to crtc.
- */
-void dpu_cp_crtc_pre_ipc(struct drm_crtc *crtc);
-
-/**
- * dpu_cp_crtc_post_ipc: Handle color processing features
- * after exiting IPC
- * @crtc: Pointer to crtc.
- */
-void dpu_cp_crtc_post_ipc(struct drm_crtc *crtc);
-#endif /*_DPU_COLOR_PROCESSING_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 99c5e75..7cf5a7a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -20,7 +20,6 @@
#include <linux/sort.h>
#include <linux/debugfs.h>
#include <linux/ktime.h>
-#include <uapi/drm/dpu_drm.h>
#include <drm/drm_mode.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
@@ -31,13 +30,18 @@
#include "dpu_hw_ctl.h"
#include "dpu_crtc.h"
#include "dpu_plane.h"
-#include "dpu_color_processing.h"
#include "dpu_encoder.h"
#include "dpu_vbif.h"
#include "dpu_power_handle.h"
#include "dpu_core_perf.h"
#include "dpu_trace.h"

+#define DPU_DRM_BLEND_OP_NOT_DEFINED 0
+#define DPU_DRM_BLEND_OP_OPAQUE 1
+#define DPU_DRM_BLEND_OP_PREMULTIPLIED 2
+#define DPU_DRM_BLEND_OP_COVERAGE 3
+#define DPU_DRM_BLEND_OP_MAX 4
+
/* layer mixer index on dpu_crtc */
#define LEFT_MIXER 0
#define RIGHT_MIXER 1
@@ -594,7 +598,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
if (dpu_crtc->blob_info)
drm_property_blob_put(dpu_crtc->blob_info);
msm_property_destroy(&dpu_crtc->property_info);
- dpu_cp_crtc_destroy_properties(crtc);
_dpu_crtc_destroy_dest_scaler(dpu_crtc);

_dpu_crtc_deinit_events(dpu_crtc);
@@ -622,67 +625,14 @@ static bool dpu_crtc_mode_fixup(struct drm_crtc *crtc,
}

static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
- struct dpu_plane_state *pstate, struct dpu_format *format)
+ struct dpu_plane_state *pstate)
{
- uint32_t blend_op, fg_alpha, bg_alpha;
- uint32_t blend_type;
struct dpu_hw_mixer *lm = mixer->hw_lm;

/* default to opaque blending */
- fg_alpha = dpu_plane_get_property(pstate, PLANE_PROP_ALPHA);
- bg_alpha = 0xFF - fg_alpha;
- blend_op = DPU_BLEND_FG_ALPHA_FG_CONST | DPU_BLEND_BG_ALPHA_BG_CONST;
- blend_type = dpu_plane_get_property(pstate, PLANE_PROP_BLEND_OP);
-
- DPU_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha);
-
- switch (blend_type) {
-
- case DPU_DRM_BLEND_OP_OPAQUE:
- blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
- DPU_BLEND_BG_ALPHA_BG_CONST;
- break;
-
- case DPU_DRM_BLEND_OP_PREMULTIPLIED:
- if (format->alpha_enable) {
- blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
- DPU_BLEND_BG_ALPHA_FG_PIXEL;
- if (fg_alpha != 0xff) {
- bg_alpha = fg_alpha;
- blend_op |= DPU_BLEND_BG_MOD_ALPHA |
- DPU_BLEND_BG_INV_MOD_ALPHA;
- } else {
- blend_op |= DPU_BLEND_BG_INV_ALPHA;
- }
- }
- break;
-
- case DPU_DRM_BLEND_OP_COVERAGE:
- if (format->alpha_enable) {
- blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
- DPU_BLEND_BG_ALPHA_FG_PIXEL;
- if (fg_alpha != 0xff) {
- bg_alpha = fg_alpha;
- blend_op |= DPU_BLEND_FG_MOD_ALPHA |
- DPU_BLEND_FG_INV_MOD_ALPHA |
- DPU_BLEND_BG_MOD_ALPHA |
- DPU_BLEND_BG_INV_MOD_ALPHA;
- } else {
- blend_op |= DPU_BLEND_BG_INV_ALPHA;
- }
- }
- break;
- default:
- /* do nothing */
- break;
- }
-
- lm->ops.setup_blend_config(lm, pstate->stage, fg_alpha,
- bg_alpha, blend_op);
- DPU_DEBUG(
- "format: %4.4s, alpha_enable %u fg alpha:0x%x bg alpha:0x%x blend_op:0x%x\n",
- (char *) &format->base.pixel_format,
- format->alpha_enable, fg_alpha, bg_alpha, blend_op);
+ lm->ops.setup_blend_config(lm, pstate->stage, 0XFF, 0,
+ DPU_BLEND_FG_ALPHA_FG_CONST |
+ DPU_BLEND_BG_ALPHA_BG_CONST);
}

static void _dpu_crtc_setup_dim_layer_cfg(struct drm_crtc *crtc,
@@ -857,8 +807,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,

/* blend config update */
for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
- _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate,
- format);
+ _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate);
+
mixer[lm_idx].flush_mask |= flush_mask;

if (bg_alpha_enable && !format->alpha_enable)
@@ -1819,11 +1769,10 @@ static void _dpu_crtc_setup_mixer_for_encoder(
struct dpu_crtc_mixer *mixer;
struct dpu_hw_ctl *last_valid_ctl = NULL;
int i;
- struct dpu_rm_hw_iter lm_iter, ctl_iter, dspp_iter, ds_iter;
+ struct dpu_rm_hw_iter lm_iter, ctl_iter, ds_iter;

dpu_rm_init_hw_iter(&lm_iter, enc->base.id, DPU_HW_BLK_LM);
dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL);
- dpu_rm_init_hw_iter(&dspp_iter, enc->base.id, DPU_HW_BLK_DSPP);
dpu_rm_init_hw_iter(&ds_iter, enc->base.id, DPU_HW_BLK_DS);

/* Set up all the mixers and ctls reserved by this encoder */
@@ -1851,10 +1800,6 @@ static void _dpu_crtc_setup_mixer_for_encoder(
return;
}

- /* Dspp may be null */
- (void) dpu_rm_get_hw(rm, &dspp_iter);
- mixer->hw_dspp = (struct dpu_hw_dspp *)dspp_iter.hw;
-
/* DS may be null */
(void) dpu_rm_get_hw(rm, &ds_iter);
mixer->hw_ds = (struct dpu_hw_ds *)ds_iter.hw;
@@ -1987,17 +1932,6 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
_dpu_crtc_dest_scaler_setup(crtc);

/*
- * Since CP properties use AXI buffer to program the
- * HW, check if context bank is in attached
- * state,
- * apply color processing properties only if
- * smmu state is attached,
- */
- if ((smmu_state->state != DETACHED) &&
- (smmu_state->state != DETACH_ALL_REQ))
- dpu_cp_crtc_apply_properties(crtc);
-
- /*
* PP_DONE irq is only used by command mode for now.
* It is better to request pending before FLUSH and START trigger
* to make sure no pp_done irq missed.
@@ -2429,7 +2363,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
{
struct drm_crtc *crtc = arg;
struct dpu_crtc *dpu_crtc;
- struct drm_plane *plane;
struct drm_encoder *encoder;
struct dpu_crtc_mixer *m;
u32 i, misr_status;
@@ -2454,8 +2387,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
dpu_encoder_virt_restore(encoder);
}

- dpu_cp_crtc_post_ipc(crtc);
-
for (i = 0; i < dpu_crtc->num_mixers; ++i) {
m = &dpu_crtc->mixers[i];
if (!m->hw_lm || !m->hw_lm->ops.setup_misr ||
@@ -2477,18 +2408,12 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
dpu_crtc->misr_data[i] = misr_status ? misr_status :
dpu_crtc->misr_data[i];
}
-
- dpu_cp_crtc_pre_ipc(crtc);
break;
case DPU_POWER_EVENT_POST_DISABLE:
- /*
- * set revalidate flag in planes, so it will be re-programmed
- * in the next frame update
+ /**
+ * Nothing to do. All the planes on the CRTC will be
+ * programmed for every frame
*/
- drm_atomic_crtc_for_each_plane(plane, crtc)
- dpu_plane_set_revalidate(plane, true);
-
- dpu_cp_crtc_suspend(crtc);
break;
default:
DPU_DEBUG("event:%d not handled\n", event_type);
@@ -2535,7 +2460,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
/* update color processing on suspend */
event.type = DRM_EVENT_CRTC_POWER;
event.length = sizeof(u32);
- dpu_cp_crtc_suspend(crtc);
power_on = 0;
msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
(u8 *)&power_on);
@@ -2636,7 +2560,6 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
/* update color processing on resume */
event.type = DRM_EVENT_CRTC_POWER;
event.length = sizeof(u32);
- dpu_cp_crtc_resume(crtc);
power_on = 1;
msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
(u8 *)&power_on);
@@ -2678,82 +2601,6 @@ static int pstate_cmp(const void *a, const void *b)
return rc;
}

-static int _dpu_crtc_excl_rect_overlap_check(struct plane_state pstates[],
- int cnt, int curr_cnt, struct dpu_rect *excl_rect, int z_pos)
-{
- struct dpu_rect dst_rect, intersect;
- int i, rc = -EINVAL;
- const struct drm_plane_state *pstate;
-
- /* start checking from next plane */
- for (i = curr_cnt; i < cnt; i++) {
- pstate = pstates[i].drm_pstate;
- POPULATE_RECT(&dst_rect, pstate->crtc_x, pstate->crtc_y,
- pstate->crtc_w, pstate->crtc_h, false);
- dpu_kms_rect_intersect(&dst_rect, excl_rect, &intersect);
-
- if (intersect.w == excl_rect->w && intersect.h == excl_rect->h
- /* next plane may be on same z-order */
- && z_pos != pstates[i].stage) {
- rc = 0;
- goto end;
- }
- }
-
- DPU_ERROR("excl rect does not find top overlapping rect\n");
-end:
- return rc;
-}
-
-/* no input validation - caller API has all the checks */
-static int _dpu_crtc_excl_dim_layer_check(struct drm_crtc_state *state,
- struct plane_state pstates[], int cnt)
-{
- struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
- struct drm_display_mode *mode = &state->adjusted_mode;
- const struct drm_plane_state *pstate;
- struct dpu_plane_state *dpu_pstate;
- int rc = 0, i;
-
- /* Check dim layer rect bounds and stage */
- for (i = 0; i < cstate->num_dim_layers; i++) {
- if ((CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.y,
- cstate->dim_layer[i].rect.h, mode->vdisplay)) ||
- (CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.x,
- cstate->dim_layer[i].rect.w, mode->hdisplay)) ||
- (cstate->dim_layer[i].stage >= DPU_STAGE_MAX) ||
- (!cstate->dim_layer[i].rect.w) ||
- (!cstate->dim_layer[i].rect.h)) {
- DPU_ERROR("invalid dim_layer:{%d,%d,%d,%d}, stage:%d\n",
- cstate->dim_layer[i].rect.x,
- cstate->dim_layer[i].rect.y,
- cstate->dim_layer[i].rect.w,
- cstate->dim_layer[i].rect.h,
- cstate->dim_layer[i].stage);
- DPU_ERROR("display: %dx%d\n", mode->hdisplay,
- mode->vdisplay);
- rc = -E2BIG;
- goto end;
- }
- }
-
- /* this is traversing on sorted z-order pstates */
- for (i = 0; i < cnt; i++) {
- pstate = pstates[i].drm_pstate;
- dpu_pstate = to_dpu_plane_state(pstate);
- if (dpu_pstate->excl_rect.w && dpu_pstate->excl_rect.h) {
- /* check overlap on all top z-order */
- rc = _dpu_crtc_excl_rect_overlap_check(pstates, cnt,
- i + 1, &dpu_pstate->excl_rect, pstates[i].stage);
- if (rc)
- goto end;
- }
- }
-
-end:
- return rc;
-}
-
static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
@@ -2879,10 +2726,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
/* assign mixer stages based on sorted zpos property */
sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);

- rc = _dpu_crtc_excl_dim_layer_check(state, pstates, cnt);
- if (rc)
- goto end;
-
if (!dpu_is_custom_client()) {
int stage_old = pstates[0].stage;

@@ -3302,11 +3145,8 @@ static int dpu_crtc_atomic_set_property(struct drm_crtc *crtc,
break;
}
} else {
- ret = dpu_cp_crtc_set_property(crtc,
- property, val);
- }
- if (ret)
DRM_ERROR("failed to set the property\n");
+ }

DPU_DEBUG("crtc%d %s[%d] <= 0x%llx ret=%d\n", crtc->base.id,
property->name, property->base.id, val, ret);
@@ -3371,9 +3211,6 @@ static int dpu_crtc_atomic_get_property(struct drm_crtc *crtc,
&cstate->property_state,
property, val);
if (ret)
- ret = dpu_cp_crtc_get_property(crtc,
- property, val);
- if (ret)
DRM_ERROR("get property failed\n");
}
return ret;
@@ -3488,10 +3325,6 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
seq_printf(s, "\tmultirect: mode: %d index: %d\n",
pstate->multirect_mode, pstate->multirect_index);

- seq_printf(s, "\texcl_rect: x:%4d y:%4d w:%4d h:%4d\n",
- pstate->excl_rect.x, pstate->excl_rect.y,
- pstate->excl_rect.w, pstate->excl_rect.h);
-
seq_puts(s, "\n");
}
if (dpu_crtc->vblank_cb_count) {
@@ -3935,10 +3768,6 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane)
/* Init dest scaler */
_dpu_crtc_dest_scaler_init(dpu_crtc, kms->catalog);

- /* Install color processing properties */
- dpu_cp_crtc_init(crtc);
- dpu_cp_crtc_install_properties(crtc);
-
dpu_crtc->phandle = &kms->phandle;

DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 678bf12..763dd0c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -20,6 +20,7 @@
#define _DPU_CRTC_H_

#include <linux/kthread.h>
+#include <uapi/drm/dpu_drm.h>
#include <drm/drm_crtc.h>
#include "msm_prop.h"
#include "dpu_kms.h"
@@ -86,7 +87,6 @@ struct dpu_crtc_smmu_state_data {
* struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
* @hw_lm: LM HW Driver context
* @hw_ctl: CTL Path HW driver context
- * @hw_dspp: DSPP HW driver context
* @hw_ds: DS HW driver context
* @encoder: Encoder attached to this lm & ctl
* @mixer_op_mode: mixer blending operation mode
@@ -95,7 +95,6 @@ struct dpu_crtc_smmu_state_data {
struct dpu_crtc_mixer {
struct dpu_hw_mixer *hw_lm;
struct dpu_hw_ctl *hw_ctl;
- struct dpu_hw_dspp *hw_dspp;
struct dpu_hw_ds *hw_ds;
struct drm_encoder *encoder;
u32 mixer_op_mode;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 823e9d2..713540e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1738,8 +1738,6 @@ static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)

if (phys->split_role != ENC_ROLE_SLAVE)
set_bit(i, dpu_enc->frame_busy_mask);
- if (phys->hw_ctl->ops.reg_dma_flush)
- phys->hw_ctl->ops.reg_dma_flush(phys->hw_ctl);
if (!phys->ops.needs_single_flush ||
!phys->ops.needs_single_flush(phys))
_dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c
deleted file mode 100644
index 7f81c9a..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c
+++ /dev/null
@@ -1,1443 +0,0 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <drm/msm_drm_pp.h>
-#include "dpu_hw_catalog.h"
-#include "dpu_hw_util.h"
-#include "dpu_hw_mdss.h"
-#include "dpu_hw_lm.h"
-#include "dpu_ad4.h"
-
-#define AD_STATE_READY(x) ((x) == (ad4_init | ad4_cfg | ad4_mode | ad4_input))
-#define MERGE_WIDTH_RIGHT 6
-#define MERGE_WIDTH_LEFT 5
-#define AD_IPC_FRAME_COUNT 2
-
-enum ad4_ops_bitmask {
- ad4_init = BIT(AD_INIT),
- ad4_cfg = BIT(AD_CFG),
- ad4_mode = BIT(AD_MODE),
- ad4_input = BIT(AD_INPUT),
- ad4_ops_max = BIT(31),
-};
-
-enum ad4_state {
- ad4_state_idle,
- ad4_state_startup,
- ad4_state_run,
- /* idle power collapse suspend state */
- ad4_state_ipcs,
- /* idle power collapse resume state */
- ad4_state_ipcr,
- ad4_state_max,
-};
-
-typedef int (*ad4_prop_setup)(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *ad);
-
-static int ad4_params_check(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-
-static int ad4_no_op_setup(struct dpu_hw_dspp *dspp, struct dpu_ad_hw_cfg *cfg);
-static int ad4_setup_debug(struct dpu_hw_dspp *dspp, struct dpu_ad_hw_cfg *cfg);
-static int ad4_mode_setup(struct dpu_hw_dspp *dspp, enum ad4_modes mode);
-static int ad4_mode_setup_common(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_init_setup(struct dpu_hw_dspp *dspp, struct dpu_ad_hw_cfg *cfg);
-static int ad4_init_setup_idle(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_init_setup_run(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_init_setup_ipcr(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_cfg_setup(struct dpu_hw_dspp *dspp, struct dpu_ad_hw_cfg *cfg);
-static int ad4_cfg_setup_idle(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_cfg_setup_run(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_cfg_setup_ipcr(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_input_setup(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_input_setup_idle(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_input_setup_ipcr(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_suspend_setup(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_assertive_setup(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_assertive_setup_ipcr(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_backlight_setup(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_backlight_setup_ipcr(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-
-static int ad4_ipc_suspend_setup_run(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_ipc_suspend_setup_ipcr(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_ipc_resume_setup_ipcs(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_ipc_reset_setup_startup(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_ipc_reset_setup_ipcr(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-static int ad4_cfg_ipc_reset(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg);
-
-static ad4_prop_setup prop_set_func[ad4_state_max][AD_PROPMAX] = {
- [ad4_state_idle][AD_MODE] = ad4_mode_setup_common,
- [ad4_state_idle][AD_INIT] = ad4_init_setup_idle,
- [ad4_state_idle][AD_CFG] = ad4_cfg_setup_idle,
- [ad4_state_idle][AD_INPUT] = ad4_input_setup_idle,
- [ad4_state_idle][AD_SUSPEND] = ad4_suspend_setup,
- [ad4_state_idle][AD_ASSERTIVE] = ad4_assertive_setup,
- [ad4_state_idle][AD_BACKLIGHT] = ad4_backlight_setup,
- [ad4_state_idle][AD_IPC_SUSPEND] = ad4_no_op_setup,
- [ad4_state_idle][AD_IPC_RESUME] = ad4_no_op_setup,
- [ad4_state_idle][AD_IPC_RESET] = ad4_no_op_setup,
-
- [ad4_state_startup][AD_MODE] = ad4_mode_setup_common,
- [ad4_state_startup][AD_INIT] = ad4_init_setup,
- [ad4_state_startup][AD_CFG] = ad4_cfg_setup,
- [ad4_state_startup][AD_INPUT] = ad4_input_setup,
- [ad4_state_startup][AD_SUSPEND] = ad4_suspend_setup,
- [ad4_state_startup][AD_ASSERTIVE] = ad4_assertive_setup,
- [ad4_state_startup][AD_BACKLIGHT] = ad4_backlight_setup,
- [ad4_state_startup][AD_IPC_SUSPEND] = ad4_no_op_setup,
- [ad4_state_startup][AD_IPC_RESUME] = ad4_no_op_setup,
- [ad4_state_startup][AD_IPC_RESET] = ad4_ipc_reset_setup_startup,
-
- [ad4_state_run][AD_MODE] = ad4_mode_setup_common,
- [ad4_state_run][AD_INIT] = ad4_init_setup_run,
- [ad4_state_run][AD_CFG] = ad4_cfg_setup_run,
- [ad4_state_run][AD_INPUT] = ad4_input_setup,
- [ad4_state_run][AD_SUSPEND] = ad4_suspend_setup,
- [ad4_state_run][AD_ASSERTIVE] = ad4_assertive_setup,
- [ad4_state_run][AD_BACKLIGHT] = ad4_backlight_setup,
- [ad4_state_run][AD_IPC_SUSPEND] = ad4_ipc_suspend_setup_run,
- [ad4_state_run][AD_IPC_RESUME] = ad4_no_op_setup,
- [ad4_state_run][AD_IPC_RESET] = ad4_setup_debug,
-
- [ad4_state_ipcs][AD_MODE] = ad4_no_op_setup,
- [ad4_state_ipcs][AD_INIT] = ad4_no_op_setup,
- [ad4_state_ipcs][AD_CFG] = ad4_no_op_setup,
- [ad4_state_ipcs][AD_INPUT] = ad4_no_op_setup,
- [ad4_state_ipcs][AD_SUSPEND] = ad4_no_op_setup,
- [ad4_state_ipcs][AD_ASSERTIVE] = ad4_no_op_setup,
- [ad4_state_ipcs][AD_BACKLIGHT] = ad4_no_op_setup,
- [ad4_state_ipcs][AD_IPC_SUSPEND] = ad4_no_op_setup,
- [ad4_state_ipcs][AD_IPC_RESUME] = ad4_ipc_resume_setup_ipcs,
- [ad4_state_ipcs][AD_IPC_RESET] = ad4_no_op_setup,
-
- [ad4_state_ipcr][AD_MODE] = ad4_mode_setup_common,
- [ad4_state_ipcr][AD_INIT] = ad4_init_setup_ipcr,
- [ad4_state_ipcr][AD_CFG] = ad4_cfg_setup_ipcr,
- [ad4_state_ipcr][AD_INPUT] = ad4_input_setup_ipcr,
- [ad4_state_ipcr][AD_SUSPEND] = ad4_suspend_setup,
- [ad4_state_ipcr][AD_ASSERTIVE] = ad4_assertive_setup_ipcr,
- [ad4_state_ipcr][AD_BACKLIGHT] = ad4_backlight_setup_ipcr,
- [ad4_state_ipcr][AD_IPC_SUSPEND] = ad4_ipc_suspend_setup_ipcr,
- [ad4_state_ipcr][AD_IPC_RESUME] = ad4_no_op_setup,
- [ad4_state_ipcr][AD_IPC_RESET] = ad4_ipc_reset_setup_ipcr,
-};
-
-struct ad4_info {
- enum ad4_state state;
- u32 completed_ops_mask;
- bool ad4_support;
- enum ad4_modes mode;
- bool is_master;
- u32 last_assertive;
- u32 cached_assertive;
- u64 last_als;
- u64 cached_als;
- u64 last_bl;
- u64 cached_bl;
- u32 last_str;
- u32 frame_count;
- u32 frmt_mode;
- u32 irdx_control_0;
- u32 tf_ctrl;
- u32 vc_control_0;
-};
-
-static struct ad4_info info[DSPP_MAX] = {
- [DSPP_0] = {ad4_state_idle, 0, true, AD4_OFF, false, 0x80, 0x80},
- [DSPP_1] = {ad4_state_idle, 0, true, AD4_OFF, false, 0x80, 0x80},
- [DSPP_2] = {ad4_state_max, 0, false, AD4_OFF, false, 0x80, 0x80},
- [DSPP_3] = {ad4_state_max, 0, false, AD4_OFF, false, 0x80, 0x80},
-};
-
-void dpu_setup_dspp_ad4(struct dpu_hw_dspp *dspp, void *ad_cfg)
-{
- int ret = 0;
- struct dpu_ad_hw_cfg *cfg = ad_cfg;
-
- ret = ad4_params_check(dspp, ad_cfg);
- if (ret)
- return;
-
- ret = prop_set_func[info[dspp->idx].state][cfg->prop](dspp, ad_cfg);
- if (ret)
- DRM_ERROR("op failed %d ret %d\n", cfg->prop, ret);
-}
-
-int dpu_validate_dspp_ad4(struct dpu_hw_dspp *dspp, u32 *prop)
-{
-
- if (!dspp || !prop) {
- DRM_ERROR("invalid params dspp %pK prop %pK\n", dspp, prop);
- return -EINVAL;
- }
-
- if (*prop >= AD_PROPMAX) {
- DRM_ERROR("invalid prop set %d\n", *prop);
- return -EINVAL;
- }
-
- if (dspp->idx >= DSPP_MAX || !info[dspp->idx].ad4_support) {
- DRM_ERROR("ad4 not supported for dspp idx %d\n", dspp->idx);
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int ad4_params_check(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- struct dpu_hw_mixer *hw_lm;
-
- if (!dspp || !cfg || !cfg->hw_cfg) {
- DRM_ERROR("invalid dspp %pK cfg %pK hw_cfg %pK\n",
- dspp, cfg, ((cfg) ? (cfg->hw_cfg) : NULL));
- return -EINVAL;
- }
-
- if (!cfg->hw_cfg->mixer_info) {
- DRM_ERROR("invalid mixed info\n");
- return -EINVAL;
- }
-
- if (dspp->idx >= DSPP_MAX || !info[dspp->idx].ad4_support) {
- DRM_ERROR("ad4 not supported for dspp idx %d\n", dspp->idx);
- return -EINVAL;
- }
-
- if (cfg->prop >= AD_PROPMAX) {
- DRM_ERROR("invalid prop set %d\n", cfg->prop);
- return -EINVAL;
- }
-
- if (info[dspp->idx].state >= ad4_state_max) {
- DRM_ERROR("in max state for dspp idx %d\n", dspp->idx);
- return -EINVAL;
- }
-
- if (!prop_set_func[info[dspp->idx].state][cfg->prop]) {
- DRM_ERROR("prop set not implemented for state %d prop %d\n",
- info[dspp->idx].state, cfg->prop);
- return -EINVAL;
- }
-
- if (!cfg->hw_cfg->num_of_mixers ||
- cfg->hw_cfg->num_of_mixers > CRTC_DUAL_MIXERS) {
- DRM_ERROR("invalid mixer cnt %d\n",
- cfg->hw_cfg->num_of_mixers);
- return -EINVAL;
- }
- hw_lm = cfg->hw_cfg->mixer_info;
- if (!hw_lm) {
- DRM_ERROR("invalid mixer info\n");
- return -EINVAL;
- }
-
- if (cfg->hw_cfg->num_of_mixers == 1 &&
- hw_lm->cfg.out_height != cfg->hw_cfg->displayv &&
- hw_lm->cfg.out_width != cfg->hw_cfg->displayh) {
- DRM_ERROR("single_lm lmh %d lmw %d displayh %d displayw %d\n",
- hw_lm->cfg.out_height, hw_lm->cfg.out_width,
- cfg->hw_cfg->displayh, cfg->hw_cfg->displayv);
- return -EINVAL;
- } else if (hw_lm->cfg.out_height != cfg->hw_cfg->displayv &&
- hw_lm->cfg.out_width != (cfg->hw_cfg->displayh >> 1)) {
- DRM_ERROR("dual_lm lmh %d lmw %d displayh %d displayw %d\n",
- hw_lm->cfg.out_height, hw_lm->cfg.out_width,
- cfg->hw_cfg->displayh, cfg->hw_cfg->displayv);
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int ad4_no_op_setup(struct dpu_hw_dspp *dspp, struct dpu_ad_hw_cfg *cfg)
-{
- return 0;
-}
-
-static int ad4_setup_debug(struct dpu_hw_dspp *dspp, struct dpu_ad_hw_cfg *cfg)
-{
- u32 strength = 0, i = 0;
- struct dpu_hw_mixer *hw_lm;
-
- hw_lm = cfg->hw_cfg->mixer_info;
- if ((cfg->hw_cfg->num_of_mixers == 2) && hw_lm->cfg.right_mixer) {
- /* this AD core is the salve core */
- for (i = DSPP_0; i < DSPP_MAX; i++) {
- if (info[i].is_master) {
- strength = info[i].last_str;
- break;
- }
- }
- } else {
- strength = DPU_REG_READ(&dspp->hw,
- dspp->cap->sblk->ad.base + 0x4c);
- pr_debug("%s(): AD strength = %d\n", __func__, strength);
- }
-
- return 0;
-}
-
-static int ad4_mode_setup(struct dpu_hw_dspp *dspp, enum ad4_modes mode)
-{
- u32 blk_offset;
-
- blk_offset = 0x04;
- if (mode == AD4_OFF) {
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- 0x101);
- info[dspp->idx].state = ad4_state_idle;
- pr_debug("%s(): AD state move to idle\n", __func__);
- info[dspp->idx].completed_ops_mask = 0;
- /* reset last values to register default */
- info[dspp->idx].last_assertive = 0x80;
- info[dspp->idx].cached_assertive = U8_MAX;
- info[dspp->idx].last_bl = 0xFFFF;
- info[dspp->idx].cached_bl = U64_MAX;
- info[dspp->idx].last_als = 0x0;
- info[dspp->idx].cached_als = U64_MAX;
- } else {
- if (info[dspp->idx].state == ad4_state_idle) {
- info[dspp->idx].frame_count = 0;
- info[dspp->idx].state = ad4_state_startup;
- pr_debug("%s(): AD state move to startup\n", __func__);
- }
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- 0x100);
- }
-
- return 0;
-}
-
-static int ad4_init_setup(struct dpu_hw_dspp *dspp, struct dpu_ad_hw_cfg *cfg)
-{
- u32 frame_start, frame_end, proc_start, proc_end;
- struct dpu_hw_mixer *hw_lm;
- u32 blk_offset, tile_ctl, val, i;
- u32 off1, off2, off3, off4, off5, off6;
- struct drm_msm_ad4_init *init;
-
- if (!cfg->hw_cfg->payload) {
- info[dspp->idx].completed_ops_mask &= ~ad4_init;
- return 0;
- }
-
- if (cfg->hw_cfg->len != sizeof(struct drm_msm_ad4_init)) {
- DRM_ERROR("invalid sz param exp %zd given %d cfg %pK\n",
- sizeof(struct drm_msm_ad4_init), cfg->hw_cfg->len,
- cfg->hw_cfg->payload);
- return -EINVAL;
- }
-
- hw_lm = cfg->hw_cfg->mixer_info;
- if (cfg->hw_cfg->num_of_mixers == 1) {
- frame_start = 0;
- frame_end = 0xffff;
- proc_start = 0;
- proc_end = 0xffff;
- tile_ctl = 0;
- info[dspp->idx].is_master = true;
- } else {
- tile_ctl = 0x5;
- if (hw_lm->cfg.right_mixer) {
- frame_start = (cfg->hw_cfg->displayh >> 1) -
- MERGE_WIDTH_RIGHT;
- frame_end = cfg->hw_cfg->displayh - 1;
- proc_start = (cfg->hw_cfg->displayh >> 1);
- proc_end = frame_end;
- tile_ctl |= 0x10;
- info[dspp->idx].is_master = false;
- } else {
- frame_start = 0;
- frame_end = (cfg->hw_cfg->displayh >> 1) +
- MERGE_WIDTH_LEFT;
- proc_start = 0;
- proc_end = (cfg->hw_cfg->displayh >> 1) - 1;
- tile_ctl |= 0x10;
- info[dspp->idx].is_master = true;
- }
- }
-
- init = cfg->hw_cfg->payload;
-
- info[dspp->idx].frmt_mode = (init->init_param_009 & (BIT(14) - 1));
-
- blk_offset = 0xc;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- init->init_param_010);
-
- init->init_param_012 = cfg->hw_cfg->displayv & (BIT(17) - 1);
- init->init_param_011 = cfg->hw_cfg->displayh & (BIT(17) - 1);
- blk_offset = 0x10;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- ((init->init_param_011 << 16) | init->init_param_012));
-
- blk_offset = 0x14;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- tile_ctl);
-
- blk_offset = 0x44;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- ((((init->init_param_013) & (BIT(17) - 1)) << 16) |
- (init->init_param_014 & (BIT(17) - 1))));
-
- blk_offset = 0x5c;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_015 & (BIT(16) - 1)));
- blk_offset = 0x60;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_016 & (BIT(8) - 1)));
- blk_offset = 0x64;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_017 & (BIT(12) - 1)));
- blk_offset = 0x68;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_018 & (BIT(12) - 1)));
- blk_offset = 0x6c;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_019 & (BIT(12) - 1)));
- blk_offset = 0x70;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_020 & (BIT(16) - 1)));
- blk_offset = 0x74;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_021 & (BIT(8) - 1)));
- blk_offset = 0x78;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_022 & (BIT(8) - 1)));
- blk_offset = 0x7c;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_023 & (BIT(16) - 1)));
- blk_offset = 0x80;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (((init->init_param_024 & (BIT(16) - 1)) << 16) |
- ((init->init_param_025 & (BIT(16) - 1)))));
- blk_offset = 0x84;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (((init->init_param_026 & (BIT(16) - 1)) << 16) |
- ((init->init_param_027 & (BIT(16) - 1)))));
-
- blk_offset = 0x90;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_028 & (BIT(16) - 1)));
- blk_offset = 0x94;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_029 & (BIT(16) - 1)));
-
- blk_offset = 0x98;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (((init->init_param_035 & (BIT(16) - 1)) << 16) |
- ((init->init_param_030 & (BIT(16) - 1)))));
-
- blk_offset = 0x9c;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (((init->init_param_032 & (BIT(16) - 1)) << 16) |
- ((init->init_param_031 & (BIT(16) - 1)))));
- blk_offset = 0xa0;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (((init->init_param_034 & (BIT(16) - 1)) << 16) |
- ((init->init_param_033 & (BIT(16) - 1)))));
-
- blk_offset = 0xb4;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_036 & (BIT(8) - 1)));
- blk_offset = 0xcc;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_037 & (BIT(8) - 1)));
- blk_offset = 0xc0;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_038 & (BIT(8) - 1)));
- blk_offset = 0xd8;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_039 & (BIT(8) - 1)));
-
- blk_offset = 0xe8;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_040 & (BIT(16) - 1)));
-
- blk_offset = 0xf4;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_041 & (BIT(8) - 1)));
-
- blk_offset = 0x100;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_042 & (BIT(16) - 1)));
-
- blk_offset = 0x10c;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_043 & (BIT(8) - 1)));
-
- blk_offset = 0x120;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_044 & (BIT(16) - 1)));
- blk_offset = 0x124;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_045 & (BIT(16) - 1)));
-
- blk_offset = 0x128;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_046 & (BIT(1) - 1)));
- blk_offset = 0x12c;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_047 & (BIT(8) - 1)));
-
- info[dspp->idx].irdx_control_0 = (init->init_param_048 & (BIT(5) - 1));
-
- blk_offset = 0x140;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_049 & (BIT(8) - 1)));
-
- blk_offset = 0x144;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_050 & (BIT(8) - 1)));
- blk_offset = 0x148;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (((init->init_param_051 & (BIT(8) - 1)) << 8) |
- ((init->init_param_052 & (BIT(8) - 1)))));
-
- blk_offset = 0x14c;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_053 & (BIT(10) - 1)));
- blk_offset = 0x150;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_054 & (BIT(10) - 1)));
- blk_offset = 0x154;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_055 & (BIT(8) - 1)));
-
- blk_offset = 0x158;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_056 & (BIT(8) - 1)));
- blk_offset = 0x164;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_057 & (BIT(8) - 1)));
- blk_offset = 0x168;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_058 & (BIT(4) - 1)));
-
- blk_offset = 0x17c;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (frame_start & (BIT(16) - 1)));
- blk_offset = 0x180;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (frame_end & (BIT(16) - 1)));
- blk_offset = 0x184;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (proc_start & (BIT(16) - 1)));
- blk_offset = 0x188;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (proc_end & (BIT(16) - 1)));
-
- blk_offset = 0x18c;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_059 & (BIT(4) - 1)));
-
- blk_offset = 0x190;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (((init->init_param_061 & (BIT(8) - 1)) << 8) |
- ((init->init_param_060 & (BIT(8) - 1)))));
-
- blk_offset = 0x194;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_062 & (BIT(10) - 1)));
-
- blk_offset = 0x1a0;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_063 & (BIT(10) - 1)));
- blk_offset = 0x1a4;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_064 & (BIT(10) - 1)));
- blk_offset = 0x1a8;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_065 & (BIT(10) - 1)));
- blk_offset = 0x1ac;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_066 & (BIT(8) - 1)));
- blk_offset = 0x1b0;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_067 & (BIT(8) - 1)));
- blk_offset = 0x1b4;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_068 & (BIT(6) - 1)));
-
- blk_offset = 0x460;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_069 & (BIT(16) - 1)));
- blk_offset = 0x464;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_070 & (BIT(10) - 1)));
- blk_offset = 0x468;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_071 & (BIT(10) - 1)));
- blk_offset = 0x46c;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_072 & (BIT(10) - 1)));
- blk_offset = 0x470;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_073 & (BIT(8) - 1)));
- blk_offset = 0x474;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_074 & (BIT(10) - 1)));
- blk_offset = 0x478;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (init->init_param_075 & (BIT(10) - 1)));
-
- off1 = 0x1c0;
- off2 = 0x210;
- off3 = 0x260;
- off4 = 0x2b0;
- off5 = 0x380;
- off6 = 0x3d0;
- for (i = 0; i < AD4_LUT_GRP0_SIZE - 1; i = i + 2) {
- val = (init->init_param_001[i] & (BIT(16) - 1));
- val |= ((init->init_param_001[i + 1] & (BIT(16) - 1))
- << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + off1, val);
- off1 += 4;
-
- val = (init->init_param_002[i] & (BIT(16) - 1));
- val |= ((init->init_param_002[i + 1] & (BIT(16) - 1))
- << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + off2, val);
- off2 += 4;
-
- val = (init->init_param_003[i] & (BIT(16) - 1));
- val |= ((init->init_param_003[i + 1] & (BIT(16) - 1))
- << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + off3, val);
- off3 += 4;
-
- val = (init->init_param_004[i] & (BIT(16) - 1));
- val |= ((init->init_param_004[i + 1] & (BIT(16) - 1))
- << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + off4, val);
- off4 += 4;
-
- val = (init->init_param_007[i] & (BIT(16) - 1));
- val |= ((init->init_param_007[i + 1] &
- (BIT(16) - 1)) << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + off5, val);
- off5 += 4;
-
- val = (init->init_param_008[i] & (BIT(12) - 1));
- val |= ((init->init_param_008[i + 1] &
- (BIT(12) - 1)) << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + off6, val);
- off6 += 4;
- }
- /* write last index data */
- i = AD4_LUT_GRP0_SIZE - 1;
- val = ((init->init_param_001[i] & (BIT(16) - 1)) << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + off1, val);
- val = ((init->init_param_002[i] & (BIT(16) - 1)) << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + off2, val);
- val = ((init->init_param_003[i] & (BIT(16) - 1)) << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + off3, val);
- val = ((init->init_param_004[i] & (BIT(16) - 1)) << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + off4, val);
- val = ((init->init_param_007[i] & (BIT(16) - 1)) << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + off5, val);
- val = ((init->init_param_008[i] & (BIT(12) - 1)) << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + off6, val);
-
- off1 = 0x300;
- off2 = 0x340;
- for (i = 0; i < AD4_LUT_GRP1_SIZE; i = i + 2) {
- val = (init->init_param_005[i] & (BIT(16) - 1));
- val |= ((init->init_param_005[i + 1] &
- (BIT(16) - 1)) << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + off1, val);
- off1 += 4;
-
- val = (init->init_param_006[i] & (BIT(16) - 1));
- val |= ((init->init_param_006[i + 1] & (BIT(16) - 1))
- << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + off2, val);
- off2 += 4;
- }
-
- return 0;
-}
-
-static int ad4_cfg_setup(struct dpu_hw_dspp *dspp, struct dpu_ad_hw_cfg *cfg)
-{
- u32 blk_offset, val;
- struct drm_msm_ad4_cfg *ad_cfg;
-
- if (!cfg->hw_cfg->payload) {
- info[dspp->idx].completed_ops_mask &= ~ad4_cfg;
- return 0;
- }
-
- if (cfg->hw_cfg->len != sizeof(struct drm_msm_ad4_cfg)) {
- DRM_ERROR("invalid sz param exp %zd given %d cfg %pK\n",
- sizeof(struct drm_msm_ad4_cfg), cfg->hw_cfg->len,
- cfg->hw_cfg->payload);
- return -EINVAL;
- }
- ad_cfg = cfg->hw_cfg->payload;
-
- blk_offset = 0x18;
- val = (ad_cfg->cfg_param_002 & (BIT(16) - 1));
- val |= ((ad_cfg->cfg_param_001 & (BIT(16) - 1)) << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_004 & (BIT(16) - 1));
- val |= ((ad_cfg->cfg_param_003 & (BIT(16) - 1)) << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- blk_offset = 0x20;
- val = (ad_cfg->cfg_param_005 & (BIT(8) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset = 0x24;
- val = (ad_cfg->cfg_param_006 & (BIT(7) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- info[dspp->idx].tf_ctrl = (ad_cfg->cfg_param_008 & (BIT(8) - 1));
-
- blk_offset = 0x38;
- val = (ad_cfg->cfg_param_009 & (BIT(10) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- blk_offset = 0x3c;
- val = (ad_cfg->cfg_param_010 & (BIT(12) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = ((ad_cfg->cfg_param_011 & (BIT(16) - 1)) << 16);
- val |= (ad_cfg->cfg_param_012 & (BIT(16) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- blk_offset = 0x88;
- val = (ad_cfg->cfg_param_013 & (BIT(8) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_014 & (BIT(16) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- blk_offset = 0xa4;
- val = (ad_cfg->cfg_param_015 & (BIT(16) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_016 & (BIT(10) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_017 & (BIT(16) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_018 & (BIT(16) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- blk_offset = 0xc4;
- val = (ad_cfg->cfg_param_019 & (BIT(16) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_020 & (BIT(16) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- blk_offset = 0xb8;
- val = (ad_cfg->cfg_param_021 & (BIT(16) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_022 & (BIT(16) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- blk_offset = 0xd0;
- val = (ad_cfg->cfg_param_023 & (BIT(16) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_024 & (BIT(16) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- blk_offset = 0xdc;
- val = (ad_cfg->cfg_param_025 & (BIT(16) - 1));
- val |= ((ad_cfg->cfg_param_026 & (BIT(16) - 1)) << 16);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_027 & (BIT(16) - 1));
- val |= ((ad_cfg->cfg_param_028 & (BIT(16) - 1)) << 16);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_029 & (BIT(16) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- blk_offset = 0xec;
- val = (ad_cfg->cfg_param_030 & (BIT(16) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_031 & (BIT(12) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- blk_offset = 0xf8;
- val = (ad_cfg->cfg_param_032 & (BIT(10) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_033 & (BIT(8) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- blk_offset = 0x104;
- val = (ad_cfg->cfg_param_034 & (BIT(16) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_035 & (BIT(12) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- blk_offset = 0x110;
- val = (ad_cfg->cfg_param_036 & (BIT(12) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_037 & (BIT(12) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_038 & (BIT(8) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_039 & (BIT(8) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- blk_offset = 0x134;
- val = (ad_cfg->cfg_param_040 & (BIT(12) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- info[dspp->idx].vc_control_0 = (ad_cfg->cfg_param_041 & (BIT(7) - 1));
-
- blk_offset += 160;
- val = (ad_cfg->cfg_param_043 & (BIT(10) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- blk_offset = 0x16c;
- val = (ad_cfg->cfg_param_044 & (BIT(8) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_045 & (BIT(8) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- blk_offset += 4;
- val = (ad_cfg->cfg_param_046 & (BIT(16) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
-
- return 0;
-}
-
-static int ad4_input_setup(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- u64 *val, als;
- u32 blk_offset;
-
- if (cfg->hw_cfg->len != sizeof(u64) && cfg->hw_cfg->payload) {
- DRM_ERROR("invalid sz param exp %zd given %d cfg %pK\n",
- sizeof(u64), cfg->hw_cfg->len, cfg->hw_cfg->payload);
- return -EINVAL;
- }
-
- blk_offset = 0x28;
- if (cfg->hw_cfg->payload) {
- val = cfg->hw_cfg->payload;
- } else {
- als = 0;
- val = &als;
- }
- info[dspp->idx].last_als = (*val & (BIT(16) - 1));
- info[dspp->idx].completed_ops_mask |= ad4_input;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].last_als);
- return 0;
-}
-
-static int ad4_suspend_setup(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- info[dspp->idx].state = ad4_state_idle;
- pr_debug("%s(): AD state move to idle\n", __func__);
- info[dspp->idx].completed_ops_mask = 0;
- return 0;
-}
-
-static int ad4_mode_setup_common(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
-
- if (cfg->hw_cfg->len != sizeof(u64) || !cfg->hw_cfg->payload) {
- DRM_ERROR("invalid sz param exp %zd given %d cfg %pK\n",
- sizeof(u64), cfg->hw_cfg->len, cfg->hw_cfg->payload);
- return -EINVAL;
- }
-
- info[dspp->idx].mode = *((enum ad4_modes *)
- (cfg->hw_cfg->payload));
- info[dspp->idx].completed_ops_mask |= ad4_mode;
-
- if (AD_STATE_READY(info[dspp->idx].completed_ops_mask) ||
- info[dspp->idx].mode == AD4_OFF)
- ad4_mode_setup(dspp, info[dspp->idx].mode);
-
- return 0;
-}
-
-static int ad4_init_setup_idle(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- int ret;
- u32 blk_offset;
-
- if (!cfg->hw_cfg->payload) {
- info[dspp->idx].completed_ops_mask &= ~ad4_init;
- return 0;
- }
-
- ret = ad4_init_setup(dspp, cfg);
- if (ret)
- return ret;
-
- /* enable memory initialization*/
- /* frmt mode */
- blk_offset = 0x8;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (info[dspp->idx].frmt_mode & 0x1fff));
- /* memory init */
- blk_offset = 0x450;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, 0x1);
-
- /* enforce 0 initial strength when powering up AD config */
- /* irdx_control_0 */
- blk_offset = 0x13c;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, 0x6);
-
- info[dspp->idx].completed_ops_mask |= ad4_init;
-
- if (AD_STATE_READY(info[dspp->idx].completed_ops_mask))
- ad4_mode_setup(dspp, info[dspp->idx].mode);
-
- return 0;
-}
-
-static int ad4_init_setup_run(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- int ret;
- u32 blk_offset;
-
- if (!cfg->hw_cfg->payload) {
- info[dspp->idx].completed_ops_mask &= ~ad4_init;
- return 0;
- }
-
- ret = ad4_init_setup(dspp, cfg);
- if (ret)
- return ret;
-
- /* disable memory initialization*/
- /* frmt mode */
- blk_offset = 0x8;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (info[dspp->idx].frmt_mode | 0x2000));
- /* no need to explicitly set memory initialization sequence,
- * since AD hw were not powered off.
- */
-
- /* irdx_control_0 */
- blk_offset = 0x13c;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].irdx_control_0);
-
- return 0;
-}
-
-static int ad4_init_setup_ipcr(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- int ret;
- u32 blk_offset;
-
- if (!cfg->hw_cfg->payload) {
- info[dspp->idx].completed_ops_mask &= ~ad4_init;
- return 0;
- }
-
- ret = ad4_init_setup(dspp, cfg);
- if (ret)
- return ret;
- /* no need to explicitly set memory initialization sequence,
- * since register reset values are the correct configuration
- */
- /* frmt mode */
- blk_offset = 0x8;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (info[dspp->idx].frmt_mode | 0x2000));
- /* irdx_control_0 */
- blk_offset = 0x13c;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].irdx_control_0);
-
- info[dspp->idx].completed_ops_mask |= ad4_init;
- if (AD_STATE_READY(info[dspp->idx].completed_ops_mask))
- ad4_mode_setup(dspp, info[dspp->idx].mode);
-
- return 0;
-}
-
-static int ad4_cfg_setup_idle(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- int ret;
- u32 blk_offset;
-
- if (!cfg->hw_cfg->payload) {
- info[dspp->idx].completed_ops_mask &= ~ad4_cfg;
- return 0;
- }
-
- ret = ad4_cfg_setup(dspp, cfg);
- if (ret)
- return ret;
-
- /* enforce 0 initial strength when powering up AD config */
- /* assertiveness */
- blk_offset = 0x30;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, 0x0);
- /* tf control */
- blk_offset = 0x34;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, 0x55);
-
- /* vc_control_0 */
- blk_offset = 0x138;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].vc_control_0);
-
- info[dspp->idx].completed_ops_mask |= ad4_cfg;
- if (AD_STATE_READY(info[dspp->idx].completed_ops_mask))
- ad4_mode_setup(dspp, info[dspp->idx].mode);
- return 0;
-}
-
-static int ad4_cfg_setup_run(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- int ret;
- u32 blk_offset;
-
- if (!cfg->hw_cfg->payload) {
- info[dspp->idx].completed_ops_mask &= ~ad4_cfg;
- return 0;
- }
-
- ret = ad4_cfg_setup(dspp, cfg);
- if (ret)
- return ret;
-
- /* assertiveness */
- blk_offset = 0x30;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].last_assertive);
- /* tf control */
- blk_offset = 0x34;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].tf_ctrl);
- /* vc_control_0 */
- blk_offset = 0x138;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].vc_control_0);
-
- return 0;
-}
-
-static int ad4_cfg_setup_ipcr(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- int ret;
- u32 blk_offset;
-
- if (!cfg->hw_cfg->payload) {
- info[dspp->idx].completed_ops_mask &= ~ad4_cfg;
- return 0;
- }
-
- ret = ad4_cfg_setup(dspp, cfg);
- if (ret)
- return ret;
-
- /* assertiveness */
- blk_offset = 0x30;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].last_assertive);
-
- info[dspp->idx].completed_ops_mask |= ad4_cfg;
- if (AD_STATE_READY(info[dspp->idx].completed_ops_mask))
- ad4_mode_setup(dspp, info[dspp->idx].mode);
- return 0;
-}
-
-static int ad4_input_setup_idle(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- int ret;
-
- ret = ad4_input_setup(dspp, cfg);
- if (ret)
- return ret;
-
- info[dspp->idx].completed_ops_mask |= ad4_input;
- if (AD_STATE_READY(info[dspp->idx].completed_ops_mask))
- ad4_mode_setup(dspp, info[dspp->idx].mode);
-
- return 0;
-}
-
-static int ad4_input_setup_ipcr(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- u64 *val, als;
- u32 blk_offset;
-
- if (cfg->hw_cfg->len != sizeof(u64) && cfg->hw_cfg->payload) {
- DRM_ERROR("invalid sz param exp %zd given %d cfg %pK\n",
- sizeof(u64), cfg->hw_cfg->len, cfg->hw_cfg->payload);
- return -EINVAL;
- }
-
- blk_offset = 0x28;
- if (cfg->hw_cfg->payload) {
- val = cfg->hw_cfg->payload;
- } else {
- als = 0;
- val = &als;
- }
- info[dspp->idx].cached_als = *val & (BIT(16) - 1);
- info[dspp->idx].completed_ops_mask |= ad4_input;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].last_als);
-
- if (AD_STATE_READY(info[dspp->idx].completed_ops_mask))
- ad4_mode_setup(dspp, info[dspp->idx].mode);
-
- return 0;
-}
-
-static int ad4_assertive_setup(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- u64 *val, assertive;
- u32 blk_offset;
-
- if (cfg->hw_cfg->len != sizeof(u64) && cfg->hw_cfg->payload) {
- DRM_ERROR("invalid sz param exp %zd given %d cfg %pK\n",
- sizeof(u64), cfg->hw_cfg->len, cfg->hw_cfg->payload);
- return -EINVAL;
- }
-
- blk_offset = 0x30;
- if (cfg->hw_cfg->payload) {
- val = cfg->hw_cfg->payload;
- } else {
- assertive = 0;
- val = &assertive;
- }
-
- info[dspp->idx].last_assertive = *val & (BIT(8) - 1);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- (info[dspp->idx].last_assertive));
- return 0;
-}
-
-static int ad4_assertive_setup_ipcr(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- u64 *val, assertive;
- u32 blk_offset;
-
- if (cfg->hw_cfg->len != sizeof(u64) && cfg->hw_cfg->payload) {
- DRM_ERROR("invalid sz param exp %zd given %d cfg %pK\n",
- sizeof(u64), cfg->hw_cfg->len, cfg->hw_cfg->payload);
- return -EINVAL;
- }
-
- blk_offset = 0x30;
- if (cfg->hw_cfg->payload) {
- val = cfg->hw_cfg->payload;
- } else {
- assertive = 0;
- val = &assertive;
- }
-
- info[dspp->idx].cached_assertive = *val & (BIT(8) - 1);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].last_assertive);
-
- return 0;
-}
-
-static int ad4_backlight_setup(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- u64 *val, bl;
- u32 blk_offset;
-
- if (cfg->hw_cfg->len != sizeof(u64) && cfg->hw_cfg->payload) {
- DRM_ERROR("invalid sz param exp %zd given %d cfg %pK\n",
- sizeof(u64), cfg->hw_cfg->len, cfg->hw_cfg->payload);
- return -EINVAL;
- }
-
- blk_offset = 0x2c;
- if (cfg->hw_cfg->payload) {
- val = cfg->hw_cfg->payload;
- } else {
- bl = 0;
- val = &bl;
- }
-
- info[dspp->idx].last_bl = *val & (BIT(16) - 1);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].last_bl);
- return 0;
-}
-
-static int ad4_backlight_setup_ipcr(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- u64 *val, bl;
- u32 blk_offset;
-
- if (cfg->hw_cfg->len != sizeof(u64) && cfg->hw_cfg->payload) {
- DRM_ERROR("invalid sz param exp %zd given %d cfg %pK\n",
- sizeof(u64), cfg->hw_cfg->len, cfg->hw_cfg->payload);
- return -EINVAL;
- }
-
- blk_offset = 0x2c;
- if (cfg->hw_cfg->payload) {
- val = cfg->hw_cfg->payload;
- } else {
- bl = 0;
- val = &bl;
- }
-
- info[dspp->idx].cached_bl = *val & (BIT(16) - 1);
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].last_bl);
-
- return 0;
-}
-
-void dpu_read_intr_resp_ad4(struct dpu_hw_dspp *dspp, u32 event, u32 *resp)
-{
- if (!dspp || !resp) {
- DRM_ERROR("invalid params dspp %pK resp %pK\n", dspp, resp);
- return;
- }
-
- switch (event) {
- case AD4_BACKLIGHT:
- *resp = DPU_REG_READ(&dspp->hw,
- dspp->cap->sblk->ad.base + 0x48);
- break;
- default:
- break;
- }
-}
-
-static int ad4_ipc_suspend_setup_run(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- u32 strength = 0, i = 0;
- struct dpu_hw_mixer *hw_lm;
-
- hw_lm = cfg->hw_cfg->mixer_info;
- if ((cfg->hw_cfg->num_of_mixers == 2) && hw_lm->cfg.right_mixer) {
- /* this AD core is the salve core */
- for (i = DSPP_0; i < DSPP_MAX; i++) {
- if (info[i].is_master) {
- strength = info[i].last_str;
- break;
- }
- }
- } else {
- strength = DPU_REG_READ(&dspp->hw,
- dspp->cap->sblk->ad.base + 0x4c);
- pr_debug("%s(): AD strength = %d\n", __func__, strength);
- }
- info[dspp->idx].last_str = strength;
- info[dspp->idx].state = ad4_state_ipcs;
- pr_debug("%s(): AD state move to ipcs\n", __func__);
-
- return 0;
-}
-
-static int ad4_ipc_resume_setup_ipcs(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- u32 blk_offset, val;
-
- info[dspp->idx].frame_count = 0;
- info[dspp->idx].state = ad4_state_ipcr;
- pr_debug("%s(): AD state move to ipcr\n", __func__);
-
- /* no need to rewrite frmt_mode bit 13 and mem_init,
- * since the default register values are exactly what
- * we wanted.
- */
-
- /* ipc resume with manual strength */
- /* tf control */
- blk_offset = 0x34;
- val = (0x55 & (BIT(8) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- /* set manual strength */
- blk_offset = 0x15c;
- val = (info[dspp->idx].last_str & (BIT(10) - 1));
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val);
- /* enable manual mode */
- blk_offset = 0x138;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, 0);
-
- return 0;
-}
-
-static int ad4_ipc_suspend_setup_ipcr(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- info[dspp->idx].state = ad4_state_ipcs;
- pr_debug("%s(): AD state move to ipcs\n", __func__);
- return 0;
-}
-
-static int ad4_ipc_reset_setup_ipcr(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- int ret;
- u32 strength = 0, i = 0;
- struct dpu_hw_mixer *hw_lm;
-
- /* Read AD calculator strength output during the 2 frames of manual
- * strength mode, and assign the strength output to last_str
- * when frame count reaches AD_IPC_FRAME_COUNT to avoid flickers
- * caused by strength was not converged before entering IPC mode
- */
- hw_lm = cfg->hw_cfg->mixer_info;
- if ((cfg->hw_cfg->num_of_mixers == 2) && hw_lm->cfg.right_mixer) {
- /* this AD core is the salve core */
- for (i = DSPP_0; i < DSPP_MAX; i++) {
- if (info[i].is_master) {
- strength = info[i].last_str;
- break;
- }
- }
- } else {
- strength = DPU_REG_READ(&dspp->hw,
- dspp->cap->sblk->ad.base + 0x4c);
- pr_debug("%s(): AD strength = %d\n", __func__, strength);
- }
-
- if (info[dspp->idx].frame_count == AD_IPC_FRAME_COUNT) {
- info[dspp->idx].state = ad4_state_run;
- pr_debug("%s(): AD state move to run\n", __func__);
- info[dspp->idx].last_str = strength;
- ret = ad4_cfg_ipc_reset(dspp, cfg);
- if (ret)
- return ret;
- } else {
- info[dspp->idx].frame_count++;
- }
-
- return 0;
-}
-
-static int ad4_cfg_ipc_reset(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- u32 blk_offset;
-
- /* revert manual strength */
- /* tf control */
- blk_offset = 0x34;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].tf_ctrl);
- /* vc_control_0 */
- blk_offset = 0x138;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].vc_control_0);
-
- /* reset cached ALS, backlight and assertiveness */
- if (info[dspp->idx].cached_als != U64_MAX) {
- DPU_REG_WRITE(&dspp->hw,
- dspp->cap->sblk->ad.base + 0x28,
- info[dspp->idx].cached_als);
- info[dspp->idx].last_als = info[dspp->idx].cached_als;
- info[dspp->idx].cached_als = U64_MAX;
- }
- if (info[dspp->idx].cached_bl != U64_MAX) {
- DPU_REG_WRITE(&dspp->hw,
- dspp->cap->sblk->ad.base + 0x2c,
- info[dspp->idx].cached_bl);
- info[dspp->idx].last_bl = info[dspp->idx].cached_bl;
- info[dspp->idx].cached_bl = U64_MAX;
- }
- if (info[dspp->idx].cached_assertive != U8_MAX) {
- DPU_REG_WRITE(&dspp->hw,
- dspp->cap->sblk->ad.base + 0x30,
- info[dspp->idx].cached_assertive);
- info[dspp->idx].last_assertive =
- info[dspp->idx].cached_assertive;
- info[dspp->idx].cached_assertive = U8_MAX;
- }
-
- return 0;
-}
-
-static int ad4_ipc_reset_setup_startup(struct dpu_hw_dspp *dspp,
- struct dpu_ad_hw_cfg *cfg)
-{
- u32 blk_offset;
-
- if (info[dspp->idx].frame_count == AD_IPC_FRAME_COUNT) {
- info[dspp->idx].state = ad4_state_run;
- pr_debug("%s(): AD state move to run\n", __func__);
-
- /* revert enforce 0 initial strength */
- /* irdx_control_0 */
- blk_offset = 0x13c;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].irdx_control_0);
- /* assertiveness */
- blk_offset = 0x30;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].last_assertive);
- /* tf control */
- blk_offset = 0x34;
- DPU_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
- info[dspp->idx].tf_ctrl);
- } else {
- info[dspp->idx].frame_count++;
- }
-
- return 0;
-}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 1c0959f..0fb0b27 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -32,14 +32,6 @@
#define MIXER_SDM845_MASK \
(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))

-#define DSPP_SDM845_MASK \
- (BIT(DPU_DSPP_IGC) | BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC) |\
- BIT(DPU_DSPP_HSIC) | BIT(DPU_DSPP_GAMUT) | BIT(DPU_DSPP_HIST) |\
- BIT(DPU_DSPP_MEMCOLOR) | BIT(DPU_DSPP_SIXZONE) | BIT(DPU_DSPP_VLUT))
-
-#define DSPP_AD_SDM845_MASK \
- (DSPP_SDM845_MASK | BIT(DPU_DSPP_AD))
-
#define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)

#define PINGPONG_SDM845_SPLIT_MASK \
@@ -235,76 +227,33 @@
},
};

-#define LM_BLK(_name, _id, _base, _dspp, _ds, _pp, _lmpair) \
+#define LM_BLK(_name, _id, _base, _ds, _pp, _lmpair) \
{ \
.name = _name, .id = _id, \
.base = _base, .len = 0x320, \
.features = MIXER_SDM845_MASK, \
.sblk = &sdm845_lm_sblk, \
- .dspp = _dspp, .ds = _ds, \
+ .ds = _ds, \
.pingpong = _pp, \
.lm_pair_mask = (1 << _lmpair) \
}
+
static struct dpu_lm_cfg sdm845_lm[] = {
- LM_BLK("lm_0", LM_0, 0x45000, DSPP_0,
+ LM_BLK("lm_0", LM_0, 0x45000,
DS_0, PINGPONG_0, LM_1),
- LM_BLK("lm_1", LM_1, 0x46000, DSPP_1,
+ LM_BLK("lm_1", LM_1, 0x46000,
DS_1, PINGPONG_1, LM_0),
- LM_BLK("lm_2", LM_2, 0x47000, DSPP_2,
+ LM_BLK("lm_2", LM_2, 0x47000,
DS_MAX, PINGPONG_2, LM_5),
- LM_BLK("lm_3", LM_3, 0x0, DSPP_MAX,
+ LM_BLK("lm_3", LM_3, 0x0,
DS_MAX, PINGPONG_MAX, 0),
- LM_BLK("lm_4", LM_4, 0x0, DSPP_MAX,
+ LM_BLK("lm_4", LM_4, 0x0,
DS_MAX, PINGPONG_MAX, 0),
- LM_BLK("lm_5", LM_5, 0x4a000, DSPP_3,
+ LM_BLK("lm_5", LM_5, 0x4a000,
DS_MAX, PINGPONG_3, LM_2),
};

/*************************************************************
- * DSPP sub blocks config
- *************************************************************/
-static struct dpu_dspp_top_cfg sdm845_dspp_top = {
- .name = "dspp_top", .base = 0x1300, .len = 0xc
-};
-
-static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {
- .igc = {.id = DPU_DSPP_IGC, .base = 0x0,
- .len = 0x0, .version = 0x30001},
- .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
- .len = 0x0, .version = 0x40000},
- .gc = {.id = DPU_DSPP_GC, .base = 0x17c0,
- .len = 0x0, .version = 0x10008},
- .hsic = {.id = DPU_DSPP_HSIC, .base = 0x800,
- .len = 0x0, .version = 0x10007},
- .memcolor = {.id = DPU_DSPP_MEMCOLOR, .base = 0x880,
- .len = 0x0, .version = 0x10007},
- .sixzone = {.id = DPU_DSPP_SIXZONE, .base = 0x900,
- .len = 0x0, .version = 0x10007},
- .gamut = {.id = DPU_DSPP_GAMUT, .base = 0x1000,
- .len = 0x0, .version = 0x40000},
- .hist = {.id = DPU_DSPP_HIST, .base = 0x800,
- .len = 0x0, .version = 0x10007},
- /* TODO : Move AD out of DSPP config */
- .vlut = {.id = DPU_DSPP_VLUT, .base = 0xa00,
- .len = 0x0, .version = 0x10008},
-};
-
-#define DSPP_BLK(_name, _id, _base) \
- {\
- .name = _name, .id = _id, \
- .base = _base, .len = 0x17e0, \
- .features = DSPP_SDM845_MASK, \
- .sblk = &sdm845_dspp_sblk, \
- }
-
-static struct dpu_dspp_cfg sdm845_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x55000),
- DSPP_BLK("dspp_1", DSPP_1, 0x57000),
- DSPP_BLK("dspp_2", DSPP_2, 0x59000),
- DSPP_BLK("dspp_3", DSPP_3, 0x5b000),
-};
-
-/*************************************************************
* DS sub blocks config
*************************************************************/
static const struct dpu_ds_top_cfg sdm845_ds_top = {
@@ -518,9 +467,6 @@ void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
.sspp = sdm845_sspp,
.mixer_count = ARRAY_SIZE(sdm845_lm),
.mixer = sdm845_lm,
- .dspp_top = sdm845_dspp_top,
- .dspp_count = ARRAY_SIZE(sdm845_dspp),
- .dspp = sdm845_dspp,
.ds_count = ARRAY_SIZE(sdm845_ds),
.ds = sdm845_ds,
.pingpong_count = ARRAY_SIZE(sdm845_pp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 248bdab..f0cb0d4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -63,11 +63,6 @@

#define CRTC_DUAL_MIXERS 2

-#define DPU_COLOR_PROCESS_VER(MAJOR, MINOR) \
- ((((MAJOR) & 0xFFFF) << 16) | (((MINOR) & 0xFFFF)))
-#define DPU_COLOR_PROCESS_MAJOR(version) (((version) & 0xFFFF0000) >> 16)
-#define DPU_COLOR_PROCESS_MINOR(version) ((version) & 0xFFFF)
-
#define MAX_XIN_COUNT 16

/**
@@ -109,10 +104,6 @@ enum {
* @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes
* @DPU_SSPP_CSC, Support of Color space converion
* @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
- * @DPU_SSPP_HSIC, Global HSIC control
- * @DPU_SSPP_MEMCOLOR Memory Color Support
- * @DPU_SSPP_IGC, Inverse gamma correction
- * @DPU_SSPP_PCC, Color correction support
* @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer
* @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq
* @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control
@@ -131,10 +122,6 @@ enum {
DPU_SSPP_SCALER_RGB,
DPU_SSPP_CSC,
DPU_SSPP_CSC_10BIT,
- DPU_SSPP_HSIC,
- DPU_SSPP_MEMCOLOR,
- DPU_SSPP_IGC,
- DPU_SSPP_PCC,
DPU_SSPP_CURSOR,
DPU_SSPP_QOS,
DPU_SSPP_QOS_8LVL,
@@ -164,36 +151,6 @@ enum {
};

/**
- * DSPP sub-blocks
- * @DPU_DSPP_IGC DSPP Inverse gamma correction block
- * @DPU_DSPP_PCC Panel color correction block
- * @DPU_DSPP_GC Gamma correction block
- * @DPU_DSPP_HSIC Global HSIC block
- * @DPU_DSPP_MEMCOLOR Memory Color block
- * @DPU_DSPP_SIXZONE Six zone block
- * @DPU_DSPP_GAMUT Gamut bloc
- * @DPU_DSPP_DITHER Dither block
- * @DPU_DSPP_HIST Histogram block
- * @DPU_DSPP_VLUT PA VLUT block
- * @DPU_DSPP_AD AD block
- * @DPU_DSPP_MAX maximum value
- */
-enum {
- DPU_DSPP_IGC = 0x1,
- DPU_DSPP_PCC,
- DPU_DSPP_GC,
- DPU_DSPP_HSIC,
- DPU_DSPP_MEMCOLOR,
- DPU_DSPP_SIXZONE,
- DPU_DSPP_GAMUT,
- DPU_DSPP_DITHER,
- DPU_DSPP_HIST,
- DPU_DSPP_VLUT,
- DPU_DSPP_AD,
- DPU_DSPP_MAX
-};
-
-/**
* PINGPONG sub-blocks
* @DPU_PINGPONG_TE Tear check block
* @DPU_PINGPONG_TE2 Additional tear check block for split pipes
@@ -427,20 +384,6 @@ struct dpu_lm_sub_blks {
struct dpu_pp_blk gc;
};

-struct dpu_dspp_sub_blks {
- struct dpu_pp_blk igc;
- struct dpu_pp_blk pcc;
- struct dpu_pp_blk gc;
- struct dpu_pp_blk hsic;
- struct dpu_pp_blk memcolor;
- struct dpu_pp_blk sixzone;
- struct dpu_pp_blk gamut;
- struct dpu_pp_blk dither;
- struct dpu_pp_blk hist;
- struct dpu_pp_blk ad;
- struct dpu_pp_blk vlut;
-};
-
struct dpu_pingpong_sub_blks {
struct dpu_pp_blk te;
struct dpu_pp_blk te2;
@@ -530,7 +473,6 @@ struct dpu_sspp_cfg {
* @base register offset of this block
* @features bit mask identifying sub-blocks/features
* @sblk: LM Sub-blocks information
- * @dspp: ID of connected DSPP, DSPP_MAX if unsupported
* @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported
* @ds: ID of connected DS, DS_MAX if unsupported
* @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL
@@ -538,37 +480,12 @@ struct dpu_sspp_cfg {
struct dpu_lm_cfg {
DPU_HW_BLK_INFO;
const struct dpu_lm_sub_blks *sblk;
- u32 dspp;
u32 pingpong;
u32 ds;
unsigned long lm_pair_mask;
};

/**
- * struct dpu_dspp_cfg - information of DSPP top block
- * @id enum identifying this block
- * @base register offset of this block
- * @features bit mask identifying sub-blocks/features
- * supported by this block
- */
-struct dpu_dspp_top_cfg {
- DPU_HW_BLK_INFO;
-};
-
-/**
- * struct dpu_dspp_cfg - information of DSPP blocks
- * @id enum identifying this block
- * @base register offset of this block
- * @features bit mask identifying sub-blocks/features
- * supported by this block
- * @sblk sub-blocks information
- */
-struct dpu_dspp_cfg {
- DPU_HW_BLK_INFO;
- const struct dpu_dspp_sub_blks *sblk;
-};
-
-/**
* struct dpu_ds_top_cfg - information of dest scaler top
* @id enum identifying this block
* @base register offset of this block
@@ -811,11 +728,6 @@ struct dpu_mdss_cfg {
u32 mixer_count;
struct dpu_lm_cfg *mixer;

- struct dpu_dspp_top_cfg dspp_top;
-
- u32 dspp_count;
- struct dpu_dspp_cfg *dspp;
-
u32 ds_count;
struct dpu_ds_cfg *ds;

@@ -859,7 +771,6 @@ struct dpu_mdss_hw_cfg_handler {
#define BLK_DMA(s) ((s)->dma)
#define BLK_CURSOR(s) ((s)->cursor)
#define BLK_MIXER(s) ((s)->mixer)
-#define BLK_DSPP(s) ((s)->dspp)
#define BLK_DS(s) ((s)->ds)
#define BLK_PINGPONG(s) ((s)->pingpong)
#define BLK_CDM(s) ((s)->cdm)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_common_v4.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_common_v4.h
deleted file mode 100644
index 495e675..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_common_v4.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef _DPU_HW_COLOR_PROC_COMMON_V4_H_
-#define _DPU_HW_COLOR_PROC_COMMON_V4_H_
-
-#define GAMUT_TABLE_SEL_OFF 0x4
-#define GAMUT_UPPER_COLOR_OFF 0x8
-#define GAMUT_LOWER_COLOR_OFF 0xc
-#define GAMUT_SCALEA_OFFSET_OFF 0x10
-#define GAMUT_SCALEB_OFFSET_OFF 0xe0
-#define GAMUT_TABLE0_SEL BIT(12)
-#define GAMUT_MAP_EN BIT(1)
-#define GAMUT_EN BIT(0)
-#define GAMUT_MODE_13B_OFF 640
-#define GAMUT_MODE_5_OFF 1248
-
-enum {
- gamut_mode_17 = 0,
- gamut_mode_5,
- gamut_mode_13a,
- gamut_mode_13b,
-};
-
-#define GC_C0_OFF 0x4
-#define GC_C0_INDEX_OFF 0x8
-#define GC_8B_ROUND_EN BIT(1)
-#define GC_EN BIT(0)
-#define GC_TBL_NUM 3
-#define GC_LUT_SWAP_OFF 0x1c
-
-#define IGC_TBL_NUM 3
-#define IGC_DITHER_OFF 0x7e0
-#define IGC_OPMODE_OFF 0x0
-#define IGC_C0_OFF 0x0
-#define IGC_DATA_MASK (BIT(12) - 1)
-#define IGC_DSPP_SEL_MASK_MAX (BIT(4) - 1)
-#define IGC_DSPP_SEL_MASK(n) \
- ((IGC_DSPP_SEL_MASK_MAX & ~(1 << (n))) << 28)
-#define IGC_INDEX_UPDATE BIT(25)
-#define IGC_EN BIT(0)
-#define IGC_DIS 0
-#define IGC_DITHER_DATA_MASK (BIT(4) - 1)
-
-#define PCC_NUM_PLANES 3
-#define PCC_NUM_COEFF 11
-#define PCC_EN BIT(0)
-#define PCC_DIS 0
-#define PCC_C_OFF 0x4
-#define PCC_R_OFF 0x10
-#define PCC_G_OFF 0x1c
-#define PCC_B_OFF 0x28
-#define PCC_RG_OFF 0x34
-#define PCC_RB_OFF 0x40
-#define PCC_GB_OFF 0x4c
-#define PCC_RGB_OFF 0x58
-#define PCC_RR_OFF 0x64
-#define PCC_GG_OFF 0x70
-#define PCC_BB_OFF 0x7c
-
-#endif /* _DPU_HW_COLOR_PROC_COMMON_V4_H_ */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c
deleted file mode 100644
index 1c693a8..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <drm/msm_drm_pp.h>
-#include "dpu_hw_color_proc_common_v4.h"
-#include "dpu_hw_color_proc_v4.h"
-
-static int dpu_write_3d_gamut(struct dpu_hw_blk_reg_map *hw,
- struct drm_msm_3d_gamut *payload, u32 base,
- u32 *opcode)
-{
- u32 reg, tbl_len, tbl_off, scale_off, i, j;
- u32 scale_tbl_len, scale_tbl_off;
- u32 *scale_data;
-
- if (!payload || !opcode || !hw) {
- DRM_ERROR("invalid payload %pK opcode %pK hw %pK\n",
- payload, opcode, hw);
- return -EINVAL;
- }
-
- switch (payload->mode) {
- case GAMUT_3D_MODE_17:
- tbl_len = GAMUT_3D_MODE17_TBL_SZ;
- tbl_off = 0;
- scale_off = GAMUT_SCALEA_OFFSET_OFF;
- *opcode = gamut_mode_17 << 2;
- break;
- case GAMUT_3D_MODE_13:
- *opcode = (*opcode & (BIT(4) - 1)) >> 2;
- if (*opcode == gamut_mode_13a)
- *opcode = gamut_mode_13b;
- else
- *opcode = gamut_mode_13a;
- tbl_len = GAMUT_3D_MODE13_TBL_SZ;
- tbl_off = (*opcode == gamut_mode_13a) ? 0 :
- GAMUT_MODE_13B_OFF;
- scale_off = (*opcode == gamut_mode_13a) ?
- GAMUT_SCALEA_OFFSET_OFF : GAMUT_SCALEB_OFFSET_OFF;
- *opcode <<= 2;
- break;
- case GAMUT_3D_MODE_5:
- *opcode = gamut_mode_5 << 2;
- tbl_len = GAMUT_3D_MODE5_TBL_SZ;
- tbl_off = GAMUT_MODE_5_OFF;
- scale_off = GAMUT_SCALEB_OFFSET_OFF;
- break;
- default:
- DRM_ERROR("invalid mode %d\n", payload->mode);
- return -EINVAL;
- }
-
- if (payload->flags & GAMUT_3D_MAP_EN)
- *opcode |= GAMUT_MAP_EN;
- *opcode |= GAMUT_EN;
-
- for (i = 0; i < GAMUT_3D_TBL_NUM; i++) {
- reg = GAMUT_TABLE0_SEL << i;
- reg |= ((tbl_off) & (BIT(11) - 1));
- DPU_REG_WRITE(hw, base + GAMUT_TABLE_SEL_OFF, reg);
- for (j = 0; j < tbl_len; j++) {
- DPU_REG_WRITE(hw, base + GAMUT_LOWER_COLOR_OFF,
- payload->col[i][j].c2_c1);
- DPU_REG_WRITE(hw, base + GAMUT_UPPER_COLOR_OFF,
- payload->col[i][j].c0);
- }
- }
-
- if ((*opcode & GAMUT_MAP_EN)) {
- if (scale_off == GAMUT_SCALEA_OFFSET_OFF)
- scale_tbl_len = GAMUT_3D_SCALE_OFF_SZ;
- else
- scale_tbl_len = GAMUT_3D_SCALEB_OFF_SZ;
- for (i = 0; i < GAMUT_3D_SCALE_OFF_TBL_NUM; i++) {
- scale_tbl_off = base + scale_off +
- i * scale_tbl_len * sizeof(u32);
- scale_data = &payload->scale_off[i][0];
- for (j = 0; j < scale_tbl_len; j++)
- DPU_REG_WRITE(hw,
- scale_tbl_off + (j * sizeof(u32)),
- scale_data[j]);
- }
- }
- DPU_REG_WRITE(hw, base, *opcode);
- return 0;
-}
-
-void dpu_setup_dspp_3d_gamutv4(struct dpu_hw_dspp *ctx, void *cfg)
-{
- struct drm_msm_3d_gamut *payload;
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
- u32 op_mode;
-
- if (!ctx || !cfg) {
- DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
- return;
- }
-
- op_mode = DPU_REG_READ(&ctx->hw, ctx->cap->sblk->gamut.base);
- if (!hw_cfg->payload) {
- DRM_DEBUG_DRIVER("disable gamut feature\n");
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->gamut.base, 0);
- return;
- }
-
- payload = hw_cfg->payload;
- dpu_write_3d_gamut(&ctx->hw, payload, ctx->cap->sblk->gamut.base,
- &op_mode);
-
-}
-
-void dpu_setup_dspp_igcv3(struct dpu_hw_dspp *ctx, void *cfg)
-{
- struct drm_msm_igc_lut *lut_cfg;
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
- int i = 0, j = 0;
- u32 *addr = NULL;
- u32 offset = 0;
-
- if (!ctx || !cfg) {
- DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
- return;
- }
-
- if (!hw_cfg->payload) {
- DRM_DEBUG_DRIVER("disable igc feature\n");
- DPU_REG_WRITE(&ctx->hw, IGC_OPMODE_OFF, 0);
- return;
- }
-
- if (hw_cfg->len != sizeof(struct drm_msm_igc_lut)) {
- DRM_ERROR("invalid size of payload len %d exp %zd\n",
- hw_cfg->len, sizeof(struct drm_msm_igc_lut));
- return;
- }
-
- lut_cfg = hw_cfg->payload;
-
- for (i = 0; i < IGC_TBL_NUM; i++) {
- addr = lut_cfg->c0 + (i * ARRAY_SIZE(lut_cfg->c0));
- offset = IGC_C0_OFF + (i * sizeof(u32));
-
- for (j = 0; j < IGC_TBL_LEN; j++) {
- addr[j] &= IGC_DATA_MASK;
- addr[j] |= IGC_DSPP_SEL_MASK(ctx->idx - 1);
- if (j == 0)
- addr[j] |= IGC_INDEX_UPDATE;
- /* IGC lut registers are part of DSPP Top HW block */
- DPU_REG_WRITE(&ctx->hw_top, offset, addr[j]);
- }
- }
-
- if (lut_cfg->flags & IGC_DITHER_ENABLE) {
- DPU_REG_WRITE(&ctx->hw, IGC_DITHER_OFF,
- lut_cfg->strength & IGC_DITHER_DATA_MASK);
- }
-
- DPU_REG_WRITE(&ctx->hw, IGC_OPMODE_OFF, IGC_EN);
-}
-
-void dpu_setup_dspp_pccv4(struct dpu_hw_dspp *ctx, void *cfg)
-{
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
- struct drm_msm_pcc *pcc_cfg;
- struct drm_msm_pcc_coeff *coeffs = NULL;
- int i = 0;
- u32 base = 0;
-
- if (!ctx || !cfg) {
- DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
- return;
- }
-
- if (!hw_cfg->payload) {
- DRM_DEBUG_DRIVER("disable pcc feature\n");
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base, 0);
- return;
- }
-
- if (hw_cfg->len != sizeof(struct drm_msm_pcc)) {
- DRM_ERROR("invalid size of payload len %d exp %zd\n",
- hw_cfg->len, sizeof(struct drm_msm_pcc));
- return;
- }
-
- pcc_cfg = hw_cfg->payload;
-
- for (i = 0; i < PCC_NUM_PLANES; i++) {
- base = ctx->cap->sblk->pcc.base + (i * sizeof(u32));
- switch (i) {
- case 0:
- coeffs = &pcc_cfg->r;
- DPU_REG_WRITE(&ctx->hw,
- base + PCC_RR_OFF, pcc_cfg->r_rr);
- DPU_REG_WRITE(&ctx->hw,
- base + PCC_GG_OFF, pcc_cfg->r_gg);
- DPU_REG_WRITE(&ctx->hw,
- base + PCC_BB_OFF, pcc_cfg->r_bb);
- break;
- case 1:
- coeffs = &pcc_cfg->g;
- DPU_REG_WRITE(&ctx->hw,
- base + PCC_RR_OFF, pcc_cfg->g_rr);
- DPU_REG_WRITE(&ctx->hw,
- base + PCC_GG_OFF, pcc_cfg->g_gg);
- DPU_REG_WRITE(&ctx->hw,
- base + PCC_BB_OFF, pcc_cfg->g_bb);
- break;
- case 2:
- coeffs = &pcc_cfg->b;
- DPU_REG_WRITE(&ctx->hw,
- base + PCC_RR_OFF, pcc_cfg->b_rr);
- DPU_REG_WRITE(&ctx->hw,
- base + PCC_GG_OFF, pcc_cfg->b_gg);
- DPU_REG_WRITE(&ctx->hw,
- base + PCC_BB_OFF, pcc_cfg->b_bb);
- break;
- default:
- DRM_ERROR("invalid pcc plane: %d\n", i);
- return;
- }
-
- DPU_REG_WRITE(&ctx->hw, base + PCC_C_OFF, coeffs->c);
- DPU_REG_WRITE(&ctx->hw, base + PCC_R_OFF, coeffs->r);
- DPU_REG_WRITE(&ctx->hw, base + PCC_G_OFF, coeffs->g);
- DPU_REG_WRITE(&ctx->hw, base + PCC_B_OFF, coeffs->b);
- DPU_REG_WRITE(&ctx->hw, base + PCC_RG_OFF, coeffs->rg);
- DPU_REG_WRITE(&ctx->hw, base + PCC_RB_OFF, coeffs->rb);
- DPU_REG_WRITE(&ctx->hw, base + PCC_GB_OFF, coeffs->gb);
- DPU_REG_WRITE(&ctx->hw, base + PCC_RGB_OFF, coeffs->rgb);
- }
-
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base, PCC_EN);
-}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h
deleted file mode 100644
index c2f447fb..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef _DPU_HW_COLOR_PROC_V4_H_
-#define _DPU_HW_COLOR_PROC_V4_H_
-
-#include "dpu_hw_util.h"
-#include "dpu_hw_catalog.h"
-#include "dpu_hw_dspp.h"
-/**
- * dpu_setup_dspp_3d_gamutv4 - Function for 3d gamut v4 version feature
- * programming.
- * @ctx: dspp ctx pointer
- * @cfg: pointer to dpu_hw_cp_cfg
- */
-void dpu_setup_dspp_3d_gamutv4(struct dpu_hw_dspp *ctx, void *cfg);
-/**
- * dpu_setup_dspp_igcv3 - Function for igc v3 version feature
- * programming.
- * @ctx: dspp ctx pointer
- * @cfg: pointer to dpu_hw_cp_cfg
- */
-void dpu_setup_dspp_igcv3(struct dpu_hw_dspp *ctx, void *cfg);
-/**
- * dpu_setup_dspp_pccv4 - Function for pcc v4 version feature
- * programming.
- * @ctx: dspp ctx pointer
- * @cfg: pointer to dpu_hw_cp_cfg
- */
-void dpu_setup_dspp_pccv4(struct dpu_hw_dspp *ctx, void *cfg);
-
-#endif /* _DPU_HW_COLOR_PROC_V4_H_ */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing.h
deleted file mode 100644
index e1bdffd..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DPU_HW_COLOR_PROCESSING_H
-#define _DPU_HW_COLOR_PROCESSING_H
-
-#include "dpu_hw_color_processing_v1_7.h"
-#include "dpu_hw_reg_dma_v1_color_proc.h"
-#include "dpu_hw_color_proc_v4.h"
-
-#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.c
deleted file mode 100644
index 6c67602..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.c
+++ /dev/null
@@ -1,565 +0,0 @@
-/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <drm/msm_drm_pp.h>
-#include "dpu_hw_color_processing_v1_7.h"
-#include "dpu_hw_ctl.h"
-
-#define PA_HUE_VIG_OFF 0x110
-#define PA_SAT_VIG_OFF 0x114
-#define PA_VAL_VIG_OFF 0x118
-#define PA_CONT_VIG_OFF 0x11C
-
-#define PA_HUE_DSPP_OFF 0x238
-#define PA_SAT_DSPP_OFF 0x23C
-#define PA_VAL_DSPP_OFF 0x240
-#define PA_CONT_DSPP_OFF 0x244
-
-#define PA_LUTV_DSPP_OFF 0x1400
-#define PA_LUT_SWAP_OFF 0x234
-
-#define PA_LUTV_DSPP_CTRL_OFF 0x4c
-#define PA_LUTV_DSPP_SWAP_OFF 0x18
-
-#define PA_HUE_MASK 0xFFF
-#define PA_SAT_MASK 0xFFFF
-#define PA_VAL_MASK 0xFF
-#define PA_CONT_MASK 0xFF
-
-#define MEMCOL_PWL0_OFF 0x88
-#define MEMCOL_PWL0_MASK 0xFFFF07FF
-#define MEMCOL_PWL1_OFF 0x8C
-#define MEMCOL_PWL1_MASK 0xFFFFFFFF
-#define MEMCOL_HUE_REGION_OFF 0x90
-#define MEMCOL_HUE_REGION_MASK 0x7FF07FF
-#define MEMCOL_SAT_REGION_OFF 0x94
-#define MEMCOL_SAT_REGION_MASK 0xFFFFFF
-#define MEMCOL_VAL_REGION_OFF 0x98
-#define MEMCOL_VAL_REGION_MASK 0xFFFFFF
-#define MEMCOL_P0_LEN 0x14
-#define MEMCOL_P1_LEN 0x8
-#define MEMCOL_PWL2_OFF 0x218
-#define MEMCOL_PWL2_MASK 0xFFFFFFFF
-#define MEMCOL_BLEND_GAIN_OFF 0x21C
-#define MEMCOL_PWL_HOLD_OFF 0x214
-
-#define VIG_OP_PA_EN BIT(4)
-#define VIG_OP_PA_SKIN_EN BIT(5)
-#define VIG_OP_PA_FOL_EN BIT(6)
-#define VIG_OP_PA_SKY_EN BIT(7)
-#define VIG_OP_PA_HUE_EN BIT(25)
-#define VIG_OP_PA_SAT_EN BIT(26)
-#define VIG_OP_PA_VAL_EN BIT(27)
-#define VIG_OP_PA_CONT_EN BIT(28)
-
-#define DSPP_OP_SZ_VAL_EN BIT(31)
-#define DSPP_OP_SZ_SAT_EN BIT(30)
-#define DSPP_OP_SZ_HUE_EN BIT(29)
-#define DSPP_OP_PA_HUE_EN BIT(25)
-#define DSPP_OP_PA_SAT_EN BIT(26)
-#define DSPP_OP_PA_VAL_EN BIT(27)
-#define DSPP_OP_PA_CONT_EN BIT(28)
-#define DSPP_OP_PA_EN BIT(20)
-#define DSPP_OP_PA_LUTV_EN BIT(19)
-#define DSPP_OP_PA_SKIN_EN BIT(5)
-#define DSPP_OP_PA_FOL_EN BIT(6)
-#define DSPP_OP_PA_SKY_EN BIT(7)
-
-#define PA_VIG_DISABLE_REQUIRED(x) \
- !((x) & (VIG_OP_PA_SKIN_EN | VIG_OP_PA_SKY_EN | \
- VIG_OP_PA_FOL_EN | VIG_OP_PA_HUE_EN | \
- VIG_OP_PA_SAT_EN | VIG_OP_PA_VAL_EN | \
- VIG_OP_PA_CONT_EN))
-
-
-#define PA_DSPP_DISABLE_REQUIRED(x) \
- !((x) & (DSPP_OP_PA_SKIN_EN | DSPP_OP_PA_SKY_EN | \
- DSPP_OP_PA_FOL_EN | DSPP_OP_PA_HUE_EN | \
- DSPP_OP_PA_SAT_EN | DSPP_OP_PA_VAL_EN | \
- DSPP_OP_PA_CONT_EN | DSPP_OP_PA_LUTV_EN))
-
-#define DSPP_OP_PCC_ENABLE BIT(0)
-#define PCC_OP_MODE_OFF 0
-#define PCC_CONST_COEFF_OFF 4
-#define PCC_R_COEFF_OFF 0x10
-#define PCC_G_COEFF_OFF 0x1C
-#define PCC_B_COEFF_OFF 0x28
-#define PCC_RG_COEFF_OFF 0x34
-#define PCC_RB_COEFF_OFF 0x40
-#define PCC_GB_COEFF_OFF 0x4C
-#define PCC_RGB_COEFF_OFF 0x58
-#define PCC_CONST_COEFF_MASK 0xFFFF
-#define PCC_COEFF_MASK 0x3FFFF
-
-#define SSPP 0
-#define DSPP 1
-
-#define PGC_C0_OFF 0x4
-#define PGC_C0_INDEX_OFF 0x8
-#define PGC_8B_ROUND_EN BIT(1)
-#define PGC_EN BIT(0)
-#define PGC_TBL_NUM 3
-#define PGC_LUT_SWAP_OFF 0x1c
-
-
-static void __setup_pa_hue(struct dpu_hw_blk_reg_map *hw,
- const struct dpu_pp_blk *blk, uint32_t hue,
- int location)
-{
- u32 base = blk->base;
- u32 offset = (location == DSPP) ? PA_HUE_DSPP_OFF : PA_HUE_VIG_OFF;
- u32 op_hue_en = (location == DSPP) ? DSPP_OP_PA_HUE_EN :
- VIG_OP_PA_HUE_EN;
- u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
- u32 disable_req;
- u32 opmode;
-
- DPU_REG_WRITE(hw, base + offset, hue & PA_HUE_MASK);
-
- opmode = DPU_REG_READ(hw, base);
-
- if (!hue) {
- opmode &= ~op_hue_en;
- disable_req = (location == DSPP) ?
- PA_DSPP_DISABLE_REQUIRED(opmode) :
- PA_VIG_DISABLE_REQUIRED(opmode);
- if (disable_req)
- opmode &= ~op_pa_en;
- } else {
- opmode |= op_hue_en | op_pa_en;
- }
-
- DPU_REG_WRITE(hw, base, opmode);
-}
-
-void dpu_setup_pipe_pa_hue_v1_7(struct dpu_hw_pipe *ctx, void *cfg)
-{
- uint32_t hue = *((uint32_t *)cfg);
-
- __setup_pa_hue(&ctx->hw, &ctx->cap->sblk->hsic_blk, hue, SSPP);
-}
-
-void dpu_setup_dspp_pa_hue_v1_7(struct dpu_hw_dspp *ctx, void *cfg)
-{
- uint32_t hue = *((uint32_t *)cfg);
-
- __setup_pa_hue(&ctx->hw, &ctx->cap->sblk->hsic, hue, DSPP);
-}
-
-static void __setup_pa_sat(struct dpu_hw_blk_reg_map *hw,
- const struct dpu_pp_blk *blk, uint32_t sat,
- int location)
-{
- u32 base = blk->base;
- u32 offset = (location == DSPP) ? PA_SAT_DSPP_OFF : PA_SAT_VIG_OFF;
- u32 op_sat_en = (location == DSPP) ?
- DSPP_OP_PA_SAT_EN : VIG_OP_PA_SAT_EN;
- u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
- u32 disable_req;
- u32 opmode;
-
- DPU_REG_WRITE(hw, base + offset, sat & PA_SAT_MASK);
-
- opmode = DPU_REG_READ(hw, base);
-
- if (!sat) {
- opmode &= ~op_sat_en;
- disable_req = (location == DSPP) ?
- PA_DSPP_DISABLE_REQUIRED(opmode) :
- PA_VIG_DISABLE_REQUIRED(opmode);
- if (disable_req)
- opmode &= ~op_pa_en;
- } else {
- opmode |= op_sat_en | op_pa_en;
- }
-
- DPU_REG_WRITE(hw, base, opmode);
-}
-
-void dpu_setup_pipe_pa_sat_v1_7(struct dpu_hw_pipe *ctx, void *cfg)
-{
- uint32_t sat = *((uint32_t *)cfg);
-
- __setup_pa_sat(&ctx->hw, &ctx->cap->sblk->hsic_blk, sat, SSPP);
-}
-
-static void __setup_pa_val(struct dpu_hw_blk_reg_map *hw,
- const struct dpu_pp_blk *blk, uint32_t value,
- int location)
-{
- u32 base = blk->base;
- u32 offset = (location == DSPP) ? PA_VAL_DSPP_OFF : PA_VAL_VIG_OFF;
- u32 op_val_en = (location == DSPP) ?
- DSPP_OP_PA_VAL_EN : VIG_OP_PA_VAL_EN;
- u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
- u32 disable_req;
- u32 opmode;
-
- DPU_REG_WRITE(hw, base + offset, value & PA_VAL_MASK);
-
- opmode = DPU_REG_READ(hw, base);
-
- if (!value) {
- opmode &= ~op_val_en;
- disable_req = (location == DSPP) ?
- PA_DSPP_DISABLE_REQUIRED(opmode) :
- PA_VIG_DISABLE_REQUIRED(opmode);
- if (disable_req)
- opmode &= ~op_pa_en;
- } else {
- opmode |= op_val_en | op_pa_en;
- }
-
- DPU_REG_WRITE(hw, base, opmode);
-}
-
-void dpu_setup_pipe_pa_val_v1_7(struct dpu_hw_pipe *ctx, void *cfg)
-{
- uint32_t value = *((uint32_t *)cfg);
-
- __setup_pa_val(&ctx->hw, &ctx->cap->sblk->hsic_blk, value, SSPP);
-}
-
-static void __setup_pa_cont(struct dpu_hw_blk_reg_map *hw,
- const struct dpu_pp_blk *blk, uint32_t contrast,
- int location)
-{
- u32 base = blk->base;
- u32 offset = (location == DSPP) ? PA_CONT_DSPP_OFF : PA_CONT_VIG_OFF;
- u32 op_cont_en = (location == DSPP) ? DSPP_OP_PA_CONT_EN :
- VIG_OP_PA_CONT_EN;
- u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
- u32 disable_req;
- u32 opmode;
-
- DPU_REG_WRITE(hw, base + offset, contrast & PA_CONT_MASK);
-
- opmode = DPU_REG_READ(hw, base);
-
- if (!contrast) {
- opmode &= ~op_cont_en;
- disable_req = (location == DSPP) ?
- PA_DSPP_DISABLE_REQUIRED(opmode) :
- PA_VIG_DISABLE_REQUIRED(opmode);
- if (disable_req)
- opmode &= ~op_pa_en;
- } else {
- opmode |= op_cont_en | op_pa_en;
- }
-
- DPU_REG_WRITE(hw, base, opmode);
-}
-
-void dpu_setup_pipe_pa_cont_v1_7(struct dpu_hw_pipe *ctx, void *cfg)
-{
- uint32_t contrast = *((uint32_t *)cfg);
-
- __setup_pa_cont(&ctx->hw, &ctx->cap->sblk->hsic_blk, contrast, SSPP);
-}
-
-void dpu_setup_pipe_pa_memcol_v1_7(struct dpu_hw_pipe *ctx,
- enum dpu_memcolor_type type,
- void *cfg)
-{
- struct drm_msm_memcol *mc = cfg;
- u32 base = ctx->cap->sblk->memcolor_blk.base;
- u32 off, op, mc_en, hold = 0;
- u32 mc_i = 0;
-
- switch (type) {
- case MEMCOLOR_SKIN:
- mc_en = VIG_OP_PA_SKIN_EN;
- mc_i = 0;
- break;
- case MEMCOLOR_SKY:
- mc_en = VIG_OP_PA_SKY_EN;
- mc_i = 1;
- break;
- case MEMCOLOR_FOLIAGE:
- mc_en = VIG_OP_PA_FOL_EN;
- mc_i = 2;
- break;
- default:
- DRM_ERROR("Invalid memory color type %d\n", type);
- return;
- }
-
- op = DPU_REG_READ(&ctx->hw, base);
- if (!mc) {
- op &= ~mc_en;
- if (PA_VIG_DISABLE_REQUIRED(op))
- op &= ~VIG_OP_PA_EN;
- DPU_REG_WRITE(&ctx->hw, base, op);
- return;
- }
-
- off = base + (mc_i * MEMCOL_P0_LEN);
- DPU_REG_WRITE(&ctx->hw, (off + MEMCOL_PWL0_OFF),
- mc->color_adjust_p0 & MEMCOL_PWL0_MASK);
- DPU_REG_WRITE(&ctx->hw, (off + MEMCOL_PWL1_OFF),
- mc->color_adjust_p1 & MEMCOL_PWL1_MASK);
- DPU_REG_WRITE(&ctx->hw, (off + MEMCOL_HUE_REGION_OFF),
- mc->hue_region & MEMCOL_HUE_REGION_MASK);
- DPU_REG_WRITE(&ctx->hw, (off + MEMCOL_SAT_REGION_OFF),
- mc->sat_region & MEMCOL_SAT_REGION_MASK);
- DPU_REG_WRITE(&ctx->hw, (off + MEMCOL_VAL_REGION_OFF),
- mc->val_region & MEMCOL_VAL_REGION_MASK);
-
- off = base + (mc_i * MEMCOL_P1_LEN);
- DPU_REG_WRITE(&ctx->hw, (off + MEMCOL_PWL2_OFF),
- mc->color_adjust_p2 & MEMCOL_PWL2_MASK);
- DPU_REG_WRITE(&ctx->hw, (off + MEMCOL_BLEND_GAIN_OFF), mc->blend_gain);
-
- hold = DPU_REG_READ(&ctx->hw, off + MEMCOL_PWL_HOLD_OFF);
- hold &= ~(0xF << (mc_i * 4));
- hold |= ((mc->sat_hold & 0x3) << (mc_i * 4));
- hold |= ((mc->val_hold & 0x3) << ((mc_i * 4) + 2));
- DPU_REG_WRITE(&ctx->hw, (off + MEMCOL_PWL_HOLD_OFF), hold);
-
- op |= VIG_OP_PA_EN | mc_en;
- DPU_REG_WRITE(&ctx->hw, base, op);
-}
-
-void dpu_setup_dspp_pcc_v1_7(struct dpu_hw_dspp *ctx, void *cfg)
-{
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
- struct drm_msm_pcc *pcc;
- void __iomem *base;
-
- if (!hw_cfg || (hw_cfg->len != sizeof(*pcc) && hw_cfg->payload)) {
- DRM_ERROR("invalid params hw %p payload %p payloadsize %d \"\
- exp size %zd\n",
- hw_cfg, ((hw_cfg) ? hw_cfg->payload : NULL),
- ((hw_cfg) ? hw_cfg->len : 0), sizeof(*pcc));
- return;
- }
- base = ctx->hw.base_off + ctx->cap->base;
-
- /* Turn off feature */
- if (!hw_cfg->payload) {
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base,
- PCC_OP_MODE_OFF);
- return;
- }
- DRM_DEBUG_DRIVER("Enable PCC feature\n");
- pcc = hw_cfg->payload;
-
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_CONST_COEFF_OFF,
- pcc->r.c & PCC_CONST_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw,
- ctx->cap->sblk->pcc.base + PCC_CONST_COEFF_OFF + 4,
- pcc->g.c & PCC_CONST_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw,
- ctx->cap->sblk->pcc.base + PCC_CONST_COEFF_OFF + 8,
- pcc->b.c & PCC_CONST_COEFF_MASK);
-
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_R_COEFF_OFF,
- pcc->r.r & PCC_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_R_COEFF_OFF + 4,
- pcc->g.r & PCC_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_R_COEFF_OFF + 8,
- pcc->b.r & PCC_COEFF_MASK);
-
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_G_COEFF_OFF,
- pcc->r.g & PCC_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_G_COEFF_OFF + 4,
- pcc->g.g & PCC_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_G_COEFF_OFF + 8,
- pcc->b.g & PCC_COEFF_MASK);
-
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_B_COEFF_OFF,
- pcc->r.b & PCC_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_B_COEFF_OFF + 4,
- pcc->g.b & PCC_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_B_COEFF_OFF + 8,
- pcc->b.b & PCC_COEFF_MASK);
-
-
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RG_COEFF_OFF,
- pcc->r.rg & PCC_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RG_COEFF_OFF + 4,
- pcc->g.rg & PCC_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RG_COEFF_OFF + 8,
- pcc->b.rg & PCC_COEFF_MASK);
-
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RB_COEFF_OFF,
- pcc->r.rb & PCC_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RB_COEFF_OFF + 4,
- pcc->g.rb & PCC_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RB_COEFF_OFF + 8,
- pcc->b.rb & PCC_COEFF_MASK);
-
-
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_GB_COEFF_OFF,
- pcc->r.gb & PCC_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_GB_COEFF_OFF + 4,
- pcc->g.gb & PCC_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_GB_COEFF_OFF + 8,
- pcc->b.gb & PCC_COEFF_MASK);
-
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RGB_COEFF_OFF,
- pcc->r.rgb & PCC_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw,
- ctx->cap->sblk->pcc.base + PCC_RGB_COEFF_OFF + 4,
- pcc->g.rgb & PCC_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw,
- ctx->cap->sblk->pcc.base + PCC_RGB_COEFF_OFF + 8,
- pcc->b.rgb & PCC_COEFF_MASK);
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base, DSPP_OP_PCC_ENABLE);
-}
-
-void dpu_setup_dspp_pa_vlut_v1_7(struct dpu_hw_dspp *ctx, void *cfg)
-{
- struct drm_msm_pa_vlut *payload = NULL;
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
- u32 base = ctx->cap->sblk->vlut.base;
- u32 offset = base + PA_LUTV_DSPP_OFF;
- u32 op_mode, tmp;
- int i = 0, j = 0;
-
- if (!hw_cfg || (hw_cfg->payload && hw_cfg->len !=
- sizeof(struct drm_msm_pa_vlut))) {
- DRM_ERROR("hw %pK payload %pK payloadsize %d exp size %zd\n",
- hw_cfg, ((hw_cfg) ? hw_cfg->payload : NULL),
- ((hw_cfg) ? hw_cfg->len : 0),
- sizeof(struct drm_msm_pa_vlut));
- return;
- }
- op_mode = DPU_REG_READ(&ctx->hw, base);
- if (!hw_cfg->payload) {
- DRM_DEBUG_DRIVER("Disable vlut feature\n");
- /**
- * In the PA_VLUT disable case, remove PA_VLUT enable bit(19)
- * first, then check whether any other PA sub-features are
- * enabled or not. If none of the sub-features are enabled,
- * remove the PA global enable bit(20).
- */
- op_mode &= ~((u32)DSPP_OP_PA_LUTV_EN);
- if (PA_DSPP_DISABLE_REQUIRED(op_mode))
- op_mode &= ~((u32)DSPP_OP_PA_EN);
- DPU_REG_WRITE(&ctx->hw, base, op_mode);
- return;
- }
- payload = hw_cfg->payload;
- DRM_DEBUG_DRIVER("Enable vlut feature flags %llx\n", payload->flags);
- for (i = 0, j = 0; i < ARRAY_SIZE(payload->val); i += 2, j += 4) {
- tmp = (payload->val[i] & REG_MASK(10)) |
- ((payload->val[i + 1] & REG_MASK(10)) << 16);
- DPU_REG_WRITE(&ctx->hw, (offset + j),
- tmp);
- }
- DPU_REG_WRITE(&ctx->hw, (base + PA_LUT_SWAP_OFF), 1);
- op_mode |= DSPP_OP_PA_EN | DSPP_OP_PA_LUTV_EN;
- DPU_REG_WRITE(&ctx->hw, base, op_mode);
-}
-
-void dpu_setup_dspp_pa_vlut_v1_8(struct dpu_hw_dspp *ctx, void *cfg)
-{
- struct drm_msm_pa_vlut *payload = NULL;
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
- struct dpu_hw_ctl *ctl = NULL;
- u32 vlut_base, pa_hist_base;
- u32 ctrl_off, swap_off;
- u32 tmp = 0;
- int i = 0, j = 0;
- u32 flush_mask = 0;
-
- if (!ctx) {
- DRM_ERROR("invalid input parameter NULL ctx\n");
- return;
- }
-
- if (!hw_cfg || (hw_cfg->payload && hw_cfg->len !=
- sizeof(struct drm_msm_pa_vlut))) {
- DRM_ERROR("hw %pK payload %pK payloadsize %d exp size %zd\n",
- hw_cfg, ((hw_cfg) ? hw_cfg->payload : NULL),
- ((hw_cfg) ? hw_cfg->len : 0),
- sizeof(struct drm_msm_pa_vlut));
- return;
- }
-
- ctl = hw_cfg->ctl;
- vlut_base = ctx->cap->sblk->vlut.base;
- pa_hist_base = ctx->cap->sblk->hist.base;
- ctrl_off = pa_hist_base + PA_LUTV_DSPP_CTRL_OFF;
- swap_off = pa_hist_base + PA_LUTV_DSPP_SWAP_OFF;
-
- if (!hw_cfg->payload) {
- DRM_DEBUG_DRIVER("Disable vlut feature\n");
- DPU_REG_WRITE(&ctx->hw, ctrl_off, 0);
- goto exit;
- }
-
- payload = hw_cfg->payload;
- DRM_DEBUG_DRIVER("Enable vlut feature flags %llx\n", payload->flags);
- for (i = 0, j = 0; i < ARRAY_SIZE(payload->val); i += 2, j += 4) {
- tmp = (payload->val[i] & REG_MASK(10)) |
- ((payload->val[i + 1] & REG_MASK(10)) << 16);
- DPU_REG_WRITE(&ctx->hw, (vlut_base + j), tmp);
- }
- DPU_REG_WRITE(&ctx->hw, ctrl_off, 1);
- DPU_REG_WRITE(&ctx->hw, swap_off, 1);
-
-exit:
- /* update flush bit */
- if (ctl && ctl->ops.get_bitmask_dspp_pavlut) {
- ctl->ops.get_bitmask_dspp_pavlut(ctl, &flush_mask, ctx->idx);
- if (ctl->ops.update_pending_flush)
- ctl->ops.update_pending_flush(ctl, flush_mask);
- }
-}
-
-void dpu_setup_dspp_gc_v1_7(struct dpu_hw_dspp *ctx, void *cfg)
-{
- struct drm_msm_pgc_lut *payload = NULL;
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
- u32 c0_off, c1_off, c2_off, i;
-
- if (!hw_cfg || (hw_cfg->payload && hw_cfg->len !=
- sizeof(struct drm_msm_pgc_lut))) {
- DRM_ERROR("hw %pK payload %pK payloadsize %d exp size %zd\n",
- hw_cfg, ((hw_cfg) ? hw_cfg->payload : NULL),
- ((hw_cfg) ? hw_cfg->len : 0),
- sizeof(struct drm_msm_pgc_lut));
- return;
- }
-
- if (!hw_cfg->payload) {
- DRM_DEBUG_DRIVER("Disable pgc feature\n");
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->gc.base, 0);
- return;
- }
- payload = hw_cfg->payload;
-
- /* Initialize index offsets */
- c0_off = ctx->cap->sblk->gc.base + PGC_C0_INDEX_OFF;
- c1_off = c0_off + (sizeof(u32) * 2);
- c2_off = c1_off + (sizeof(u32) * 2);
- DPU_REG_WRITE(&ctx->hw, c0_off, 0);
- DPU_REG_WRITE(&ctx->hw, c1_off, 0);
- DPU_REG_WRITE(&ctx->hw, c2_off, 0);
-
- /* Initialize table offsets */
- c0_off = ctx->cap->sblk->gc.base + PGC_C0_OFF;
- c1_off = c0_off + (sizeof(u32) * 2);
- c2_off = c1_off + (sizeof(u32) * 2);
-
- for (i = 0; i < PGC_TBL_LEN; i++) {
- DPU_REG_WRITE(&ctx->hw, c0_off, payload->c0[i]);
- DPU_REG_WRITE(&ctx->hw, c1_off, payload->c1[i]);
- DPU_REG_WRITE(&ctx->hw, c2_off, payload->c2[i]);
- }
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->gc.base + PGC_LUT_SWAP_OFF,
- BIT(0));
- i = BIT(0) | ((payload->flags & PGC_8B_ROUND) ? BIT(1) : 0);
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->gc.base, i);
-}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.h
deleted file mode 100644
index 76807ae..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DPU_HW_COLOR_PROCESSING_V1_7_H
-#define _DPU_HW_COLOR_PROCESSING_V1_7_H
-
-#include "dpu_hw_sspp.h"
-#include "dpu_hw_dspp.h"
-
-/**
- * dpu_setup_pipe_pa_hue_v1_7 - setup SSPP hue feature in v1.7 hardware
- * @ctx: Pointer to pipe context
- * @cfg: Pointer to hue data
- */
-void dpu_setup_pipe_pa_hue_v1_7(struct dpu_hw_pipe *ctx, void *cfg);
-
-/**
- * dpu_setup_pipe_pa_sat_v1_7 - setup SSPP saturation feature in v1.7 hardware
- * @ctx: Pointer to pipe context
- * @cfg: Pointer to saturation data
- */
-void dpu_setup_pipe_pa_sat_v1_7(struct dpu_hw_pipe *ctx, void *cfg);
-
-/**
- * dpu_setup_pipe_pa_val_v1_7 - setup SSPP value feature in v1.7 hardware
- * @ctx: Pointer to pipe context
- * @cfg: Pointer to value data
- */
-void dpu_setup_pipe_pa_val_v1_7(struct dpu_hw_pipe *ctx, void *cfg);
-
-/**
- * dpu_setup_pipe_pa_cont_v1_7 - setup SSPP contrast feature in v1.7 hardware
- * @ctx: Pointer to pipe context
- * @cfg: Pointer to contrast data
- */
-void dpu_setup_pipe_pa_cont_v1_7(struct dpu_hw_pipe *ctx, void *cfg);
-
-/**
- * dpu_setup_pipe_pa_memcol_v1_7 - setup SSPP memory color in v1.7 hardware
- * @ctx: Pointer to pipe context
- * @type: Memory color type (Skin, sky, or foliage)
- * @cfg: Pointer to memory color config data
- */
-void dpu_setup_pipe_pa_memcol_v1_7(struct dpu_hw_pipe *ctx,
- enum dpu_memcolor_type type,
- void *cfg);
-
-/**
- * dpu_setup_dspp_pcc_v1_7 - setup DSPP PCC veature in v1.7 hardware
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to PCC data
- */
-void dpu_setup_dspp_pcc_v1_7(struct dpu_hw_dspp *ctx, void *cfg);
-
-/**
- * dpu_setup_dspp_pa_hue_v1_7 - setup DSPP hue feature in v1.7 hardware
- * @ctx: Pointer to DSPP context
- * @cfg: Pointer to hue data
- */
-void dpu_setup_dspp_pa_hue_v1_7(struct dpu_hw_dspp *ctx, void *cfg);
-
-/**
- * dpu_setup_dspp_pa_vlut_v1_7 - setup DSPP PA vLUT feature in v1.7 hardware
- * @ctx: Pointer to DSPP context
- * @cfg: Pointer to vLUT data
- */
-void dpu_setup_dspp_pa_vlut_v1_7(struct dpu_hw_dspp *ctx, void *cfg);
-
-/**
- * dpu_setup_dspp_pa_vlut_v1_8 - setup DSPP PA vLUT feature in v1.8 hardware
- * @ctx: Pointer to DSPP context
- * @cfg: Pointer to vLUT data
- */
-void dpu_setup_dspp_pa_vlut_v1_8(struct dpu_hw_dspp *ctx, void *cfg);
-
-/**
- * dpu_setup_dspp_gc_v1_7 - setup DSPP gc feature in v1.7 hardware
- * @ctx: Pointer to DSPP context
- * @cfg: Pointer to gc data
- */
-void dpu_setup_dspp_gc_v1_7(struct dpu_hw_dspp *ctx, void *cfg);
-
-#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 6c9289c..ad02316 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -15,7 +15,6 @@
#include "dpu_hw_ctl.h"
#include "dpu_dbg.h"
#include "dpu_kms.h"
-#include "dpu_reg_dma.h"

#define CTL_LAYER(lm) \
(((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
@@ -203,38 +202,6 @@ static inline uint32_t dpu_hw_ctl_get_bitmask_mixer(struct dpu_hw_ctl *ctx,
return flushbits;
}

-static inline int dpu_hw_ctl_get_bitmask_dspp(struct dpu_hw_ctl *ctx,
- u32 *flushbits, enum dpu_dspp dspp)
-{
- switch (dspp) {
- case DSPP_0:
- *flushbits |= BIT(13);
- break;
- case DSPP_1:
- *flushbits |= BIT(14);
- break;
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-static inline int dpu_hw_ctl_get_bitmask_dspp_pavlut(struct dpu_hw_ctl *ctx,
- u32 *flushbits, enum dpu_dspp dspp)
-{
- switch (dspp) {
- case DSPP_0:
- *flushbits |= BIT(3);
- break;
- case DSPP_1:
- *flushbits |= BIT(4);
- break;
- default:
- return -EINVAL;
- }
- return 0;
-}
-
static inline int dpu_hw_ctl_get_bitmask_intf(struct dpu_hw_ctl *ctx,
u32 *flushbits, enum dpu_intf intf)
{
@@ -500,14 +467,6 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
DPU_REG_WRITE(c, CTL_TOP, intf_cfg);
}

-static void dpu_hw_reg_dma_flush(struct dpu_hw_ctl *ctx)
-{
- struct dpu_hw_reg_dma_ops *ops = dpu_reg_dma_get_ops();
-
- if (ops && ops->last_command)
- ops->last_command(ctx, DMA_CTL_QUEUE0);
-}
-
static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
unsigned long cap)
{
@@ -525,11 +484,8 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
ops->get_bitmask_sspp = dpu_hw_ctl_get_bitmask_sspp;
ops->get_bitmask_mixer = dpu_hw_ctl_get_bitmask_mixer;
- ops->get_bitmask_dspp = dpu_hw_ctl_get_bitmask_dspp;
- ops->get_bitmask_dspp_pavlut = dpu_hw_ctl_get_bitmask_dspp_pavlut;
ops->get_bitmask_intf = dpu_hw_ctl_get_bitmask_intf;
ops->get_bitmask_cdm = dpu_hw_ctl_get_bitmask_cdm;
- ops->reg_dma_flush = dpu_hw_reg_dma_flush;
};

static struct dpu_hw_blk_ops dpu_hw_ops = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index 185fd26..c66a71f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -138,14 +138,6 @@ struct dpu_hw_ctl_ops {
uint32_t (*get_bitmask_mixer)(struct dpu_hw_ctl *ctx,
enum dpu_lm blk);

- int (*get_bitmask_dspp)(struct dpu_hw_ctl *ctx,
- u32 *flushbits,
- enum dpu_dspp blk);
-
- int (*get_bitmask_dspp_pavlut)(struct dpu_hw_ctl *ctx,
- u32 *flushbits,
- enum dpu_dspp blk);
-
int (*get_bitmask_intf)(struct dpu_hw_ctl *ctx,
u32 *flushbits,
enum dpu_intf blk);
@@ -168,13 +160,6 @@ struct dpu_hw_ctl_ops {
*/
void (*setup_blendstage)(struct dpu_hw_ctl *ctx,
enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg);
-
- /**
- * Flush the reg dma by sending last command.
- * @ctx : ctl path ctx pointer
- */
- void (*reg_dma_flush)(struct dpu_hw_ctl *ctx);
-
};

/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
deleted file mode 100644
index a042cab..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <drm/msm_drm_pp.h>
-#include "dpu_hw_mdss.h"
-#include "dpu_hwio.h"
-#include "dpu_hw_catalog.h"
-#include "dpu_hw_dspp.h"
-#include "dpu_hw_color_processing.h"
-#include "dpu_dbg.h"
-#include "dpu_ad4.h"
-#include "dpu_kms.h"
-
-static struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp,
- struct dpu_mdss_cfg *m,
- void __iomem *addr,
- struct dpu_hw_blk_reg_map *b)
-{
- int i;
-
- if (!m || !addr || !b)
- return ERR_PTR(-EINVAL);
-
- for (i = 0; i < m->dspp_count; i++) {
- if (dspp == m->dspp[i].id) {
- b->base_off = addr;
- b->blk_off = m->dspp[i].base;
- b->length = m->dspp[i].len;
- b->hwversion = m->hwversion;
- b->log_mask = DPU_DBG_MASK_DSPP;
- return &m->dspp[i];
- }
- }
-
- return ERR_PTR(-EINVAL);
-}
-
-static void _setup_dspp_ops(struct dpu_hw_dspp *c, unsigned long features)
-{
- int i = 0, ret;
-
- if (!c || !c->cap || !c->cap->sblk)
- return;
-
- for (i = 0; i < DPU_DSPP_MAX; i++) {
- if (!test_bit(i, &features))
- continue;
- switch (i) {
- case DPU_DSPP_PCC:
- if (c->cap->sblk->pcc.version ==
- (DPU_COLOR_PROCESS_VER(0x1, 0x7)))
- c->ops.setup_pcc = dpu_setup_dspp_pcc_v1_7;
- else if (c->cap->sblk->pcc.version ==
- (DPU_COLOR_PROCESS_VER(0x4, 0x0))) {
- ret = reg_dmav1_init_dspp_op_v4(i, c->idx);
- if (!ret)
- c->ops.setup_pcc =
- reg_dmav1_setup_dspp_pccv4;
- else
- c->ops.setup_pcc =
- dpu_setup_dspp_pccv4;
- }
- break;
- case DPU_DSPP_HSIC:
- if (c->cap->sblk->hsic.version ==
- (DPU_COLOR_PROCESS_VER(0x1, 0x7)))
- c->ops.setup_hue = dpu_setup_dspp_pa_hue_v1_7;
- break;
- case DPU_DSPP_VLUT:
- if (c->cap->sblk->vlut.version ==
- (DPU_COLOR_PROCESS_VER(0x1, 0x7))) {
- c->ops.setup_vlut =
- dpu_setup_dspp_pa_vlut_v1_7;
- } else if (c->cap->sblk->vlut.version ==
- (DPU_COLOR_PROCESS_VER(0x1, 0x8))) {
- ret = reg_dmav1_init_dspp_op_v4(i, c->idx);
- if (!ret)
- c->ops.setup_vlut =
- reg_dmav1_setup_dspp_vlutv18;
- else
- c->ops.setup_vlut =
- dpu_setup_dspp_pa_vlut_v1_8;
- }
- break;
- case DPU_DSPP_GAMUT:
- if (c->cap->sblk->gamut.version ==
- DPU_COLOR_PROCESS_VER(0x4, 0)) {
- ret = reg_dmav1_init_dspp_op_v4(i, c->idx);
- if (!ret)
- c->ops.setup_gamut =
- reg_dmav1_setup_dspp_3d_gamutv4;
- else
- c->ops.setup_gamut =
- dpu_setup_dspp_3d_gamutv4;
- }
- break;
- case DPU_DSPP_GC:
- if (c->cap->sblk->gc.version ==
- DPU_COLOR_PROCESS_VER(0x1, 8)) {
- ret = reg_dmav1_init_dspp_op_v4(i, c->idx);
- if (!ret)
- c->ops.setup_gc =
- reg_dmav1_setup_dspp_gcv18;
- /** programming for v18 through ahb is same
- * as v17 hence assign v17 function
- */
- else
- c->ops.setup_gc =
- dpu_setup_dspp_gc_v1_7;
- }
- break;
- case DPU_DSPP_IGC:
- if (c->cap->sblk->igc.version ==
- DPU_COLOR_PROCESS_VER(0x3, 0x1)) {
- ret = reg_dmav1_init_dspp_op_v4(i, c->idx);
- if (!ret)
- c->ops.setup_igc =
- reg_dmav1_setup_dspp_igcv31;
- else
- c->ops.setup_igc =
- dpu_setup_dspp_igcv3;
- }
- break;
- case DPU_DSPP_AD:
- if (c->cap->sblk->ad.version ==
- DPU_COLOR_PROCESS_VER(4, 0)) {
- c->ops.setup_ad = dpu_setup_dspp_ad4;
- c->ops.ad_read_intr_resp =
- dpu_read_intr_resp_ad4;
- c->ops.validate_ad = dpu_validate_dspp_ad4;
- }
- break;
- default:
- break;
- }
- }
-}
-
-static struct dpu_hw_blk_ops dpu_hw_ops = {
- .start = NULL,
- .stop = NULL,
-};
-
-struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx,
- void __iomem *addr,
- struct dpu_mdss_cfg *m)
-{
- struct dpu_hw_dspp *c;
- struct dpu_dspp_cfg *cfg;
- int rc;
-
- if (!addr || !m)
- return ERR_PTR(-EINVAL);
-
- c = kzalloc(sizeof(*c), GFP_KERNEL);
- if (!c)
- return ERR_PTR(-ENOMEM);
-
- cfg = _dspp_offset(idx, m, addr, &c->hw);
- if (IS_ERR_OR_NULL(cfg)) {
- kfree(c);
- return ERR_PTR(-EINVAL);
- }
-
- /* Populate DSPP Top HW block */
- c->hw_top.base_off = addr;
- c->hw_top.blk_off = m->dspp_top.base;
- c->hw_top.length = m->dspp_top.len;
- c->hw_top.hwversion = m->hwversion;
- c->hw_top.log_mask = DPU_DBG_MASK_DSPP;
-
- /* Assign ops */
- c->idx = idx;
- c->cap = cfg;
- _setup_dspp_ops(c, c->cap->features);
-
- rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSPP, idx, &dpu_hw_ops);
- if (rc) {
- DPU_ERROR("failed to init hw blk %d\n", rc);
- goto blk_init_error;
- }
-
- dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off,
- c->hw.blk_off + c->hw.length, c->hw.xin_id);
-
- return c;
-
-blk_init_error:
- kzfree(c);
-
- return ERR_PTR(rc);
-}
-
-void dpu_hw_dspp_destroy(struct dpu_hw_dspp *dspp)
-{
- if (dspp) {
- reg_dmav1_deinit_dspp_ops(dspp->idx);
- dpu_hw_blk_destroy(&dspp->base);
- }
- kfree(dspp);
-}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
deleted file mode 100644
index cc72490..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DPU_HW_DSPP_H
-#define _DPU_HW_DSPP_H
-
-#include "dpu_hw_blk.h"
-
-struct dpu_hw_dspp;
-
-/**
- * struct dpu_hw_dspp_ops - interface to the dspp hardware driver functions
- * Caller must call the init function to get the dspp context for each dspp
- * Assumption is these functions will be called after clocks are enabled
- */
-struct dpu_hw_dspp_ops {
- /**
- * setup_histogram - setup dspp histogram
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_histogram)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * read_histogram - read dspp histogram
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*read_histogram)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_igc - update dspp igc
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_igc)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_pa - setup dspp pa
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_pa)(struct dpu_hw_dspp *dspp, void *cfg);
-
- /**
- * setup_pcc - setup dspp pcc
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_pcc)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_sharpening - setup dspp sharpening
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_sharpening)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_pa_memcolor - setup dspp memcolor
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_pa_memcolor)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_sixzone - setup dspp six zone
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_sixzone)(struct dpu_hw_dspp *dspp, void *cfg);
-
- /**
- * setup_danger_safe - setup danger safe LUTS
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_danger_safe)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_dither - setup dspp dither
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_dither)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_hue - setup dspp PA hue
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_hue)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_sat - setup dspp PA saturation
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_sat)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_val - setup dspp PA value
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_val)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_cont - setup dspp PA contrast
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_cont)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_vlut - setup dspp PA VLUT
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_vlut)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_gc - update dspp gc
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_gc)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_gamut - update dspp gamut
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_gamut)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * validate_ad - check if ad property can be set
- * @ctx: Pointer to dspp context
- * @prop: Pointer to ad property being validated
- */
- int (*validate_ad)(struct dpu_hw_dspp *ctx, u32 *prop);
-
- /**
- * setup_ad - update the ad property
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to ad configuration
- */
- void (*setup_ad)(struct dpu_hw_dspp *ctx, void *cfg);
-
- /**
- * ad_read_intr_resp - function to get interrupt response for ad
- * @event: Event for which response needs to be read
- * @resp: Pointer to u32 where response value is dumped.
- */
- void (*ad_read_intr_resp)(struct dpu_hw_dspp *ctx, u32 event,
- u32 *resp);
-
-};
-
-/**
- * struct dpu_hw_dspp - dspp description
- * @base: Hardware block base structure
- * @hw: Block hardware details
- * @hw_top: Block hardware top details
- * @idx: DSPP index
- * @cap: Pointer to layer_cfg
- * @ops: Pointer to operations possible for this DSPP
- */
-struct dpu_hw_dspp {
- struct dpu_hw_blk base;
- struct dpu_hw_blk_reg_map hw;
-
- /* dspp top */
- struct dpu_hw_blk_reg_map hw_top;
-
- /* dspp */
- enum dpu_dspp idx;
- const struct dpu_dspp_cfg *cap;
-
- /* Ops */
- struct dpu_hw_dspp_ops ops;
-};
-
-/**
- * dpu_hw_dspp - convert base object dpu_hw_base to container
- * @hw: Pointer to base hardware block
- * return: Pointer to hardware block container
- */
-static inline struct dpu_hw_dspp *to_dpu_hw_dspp(struct dpu_hw_blk *hw)
-{
- return container_of(hw, struct dpu_hw_dspp, base);
-}
-
-/**
- * dpu_hw_dspp_init - initializes the dspp hw driver object.
- * should be called once before accessing every dspp.
- * @idx: DSPP index for which driver object is required
- * @addr: Mapped register io address of MDP
- * @Return: pointer to structure or ERR_PTR
- */
-struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx,
- void __iomem *addr,
- struct dpu_mdss_cfg *m);
-
-/**
- * dpu_hw_dspp_destroy(): Destroys DSPP driver context
- * @dspp: Pointer to DSPP driver context
- */
-void dpu_hw_dspp_destroy(struct dpu_hw_dspp *dspp);
-
-#endif /*_DPU_HW_DSPP_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index ad21867..75a30db 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -10,6 +10,7 @@
* GNU General Public License for more details.
*/

+#include <uapi/drm/dpu_drm.h>
#include "dpu_kms.h"
#include "dpu_hw_catalog.h"
#include "dpu_hwio.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 70d57c9..fcd164f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -99,7 +99,6 @@ enum dpu_hw_blk_type {
DPU_HW_BLK_TOP = 0,
DPU_HW_BLK_SSPP,
DPU_HW_BLK_LM,
- DPU_HW_BLK_DSPP,
DPU_HW_BLK_DS,
DPU_HW_BLK_CTL,
DPU_HW_BLK_CDM,
@@ -461,39 +460,16 @@ struct dpu_mdss_color {
*/
#define DPU_DBG_MASK_NONE (1 << 0)
#define DPU_DBG_MASK_CDM (1 << 1)
-#define DPU_DBG_MASK_DSPP (1 << 2)
-#define DPU_DBG_MASK_INTF (1 << 3)
-#define DPU_DBG_MASK_LM (1 << 4)
-#define DPU_DBG_MASK_CTL (1 << 5)
-#define DPU_DBG_MASK_PINGPONG (1 << 6)
-#define DPU_DBG_MASK_SSPP (1 << 7)
-#define DPU_DBG_MASK_WB (1 << 8)
-#define DPU_DBG_MASK_TOP (1 << 9)
-#define DPU_DBG_MASK_VBIF (1 << 10)
-#define DPU_DBG_MASK_ROT (1 << 11)
-#define DPU_DBG_MASK_DS (1 << 12)
-
-/**
- * struct dpu_hw_cp_cfg: hardware dspp/lm feature payload.
- * @payload: Feature specific payload.
- * @len: Length of the payload.
- * @ctl: control pointer associated with dspp/lm.
- * @last_feature: last feature that will be set.
- * @num_of_mixers: number of layer mixers for the display.
- * @mixer_info: mixer info pointer associated with lm.
- * @displayv: height of the display.
- * @displayh: width of the display.
- */
-struct dpu_hw_cp_cfg {
- void *payload;
- u32 len;
- void *ctl;
- u32 last_feature;
- u32 num_of_mixers;
- void *mixer_info;
- u32 displayv;
- u32 displayh;
-};
+#define DPU_DBG_MASK_INTF (1 << 2)
+#define DPU_DBG_MASK_LM (1 << 3)
+#define DPU_DBG_MASK_CTL (1 << 4)
+#define DPU_DBG_MASK_PINGPONG (1 << 5)
+#define DPU_DBG_MASK_SSPP (1 << 6)
+#define DPU_DBG_MASK_WB (1 << 7)
+#define DPU_DBG_MASK_TOP (1 << 8)
+#define DPU_DBG_MASK_VBIF (1 << 9)
+#define DPU_DBG_MASK_ROT (1 << 10)
+#define DPU_DBG_MASK_DS (1 << 11)

/**
* struct dpu_hw_dim_layer: dim layer configs
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 0bfb511..84d2176 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -36,11 +36,6 @@
#define PP_FBC_BUDGET_CTL 0x038
#define PP_FBC_LOSSY_MODE 0x03C

-#define DITHER_DEPTH_MAP_INDEX 9
-static u32 dither_depth_map[DITHER_DEPTH_MAP_INDEX] = {
- 0, 0, 0, 0, 0, 1, 2, 3, 3
-};
-
static struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp,
struct dpu_mdss_cfg *m,
void __iomem *addr,
@@ -109,57 +104,6 @@ static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp,
return rc;
}

-static int dpu_hw_pp_setup_dither_v1(struct dpu_hw_pingpong *pp,
- void *cfg, size_t len)
-{
- struct dpu_hw_blk_reg_map *c;
- struct drm_msm_dither *dither = (struct drm_msm_dither *)cfg;
- u32 base = 0, offset = 0, data = 0, i = 0;
-
- if (!pp)
- return -EINVAL;
-
- c = &pp->hw;
- base = pp->caps->sblk->dither.base;
- if (!dither) {
- /* dither property disable case */
- DPU_REG_WRITE(c, base, 0);
- return 0;
- }
-
- if (len != sizeof(struct drm_msm_dither)) {
- DRM_ERROR("input len %zu, expected len %zu\n", len,
- sizeof(struct drm_msm_dither));
- return -EINVAL;
- }
-
- if (dither->c0_bitdepth >= DITHER_DEPTH_MAP_INDEX ||
- dither->c1_bitdepth >= DITHER_DEPTH_MAP_INDEX ||
- dither->c2_bitdepth >= DITHER_DEPTH_MAP_INDEX ||
- dither->c3_bitdepth >= DITHER_DEPTH_MAP_INDEX)
- return -EINVAL;
-
- offset += 4;
- data = dither_depth_map[dither->c0_bitdepth] & REG_MASK(2);
- data |= (dither_depth_map[dither->c1_bitdepth] & REG_MASK(2)) << 2;
- data |= (dither_depth_map[dither->c2_bitdepth] & REG_MASK(2)) << 4;
- data |= (dither_depth_map[dither->c3_bitdepth] & REG_MASK(2)) << 6;
- data |= (dither->temporal_en) ? (1 << 8) : 0;
- DPU_REG_WRITE(c, base + offset, data);
-
- for (i = 0; i < DITHER_MATRIX_SZ - 3; i += 4) {
- offset += 4;
- data = (dither->matrix[i] & REG_MASK(4)) |
- ((dither->matrix[i + 1] & REG_MASK(4)) << 4) |
- ((dither->matrix[i + 2] & REG_MASK(4)) << 8) |
- ((dither->matrix[i + 3] & REG_MASK(4)) << 12);
- DPU_REG_WRITE(c, base + offset, data);
- }
- DPU_REG_WRITE(c, base, 1);
-
- return 0;
-}
-
static int dpu_hw_pp_enable_te(struct dpu_hw_pingpong *pp, bool enable)
{
struct dpu_hw_blk_reg_map *c;
@@ -248,24 +192,12 @@ static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp)
static void _setup_pingpong_ops(struct dpu_hw_pingpong_ops *ops,
const struct dpu_pingpong_cfg *hw_cap)
{
- u32 version = 0;
-
ops->setup_tearcheck = dpu_hw_pp_setup_te_config;
ops->enable_tearcheck = dpu_hw_pp_enable_te;
ops->connect_external_te = dpu_hw_pp_connect_external_te;
ops->get_vsync_info = dpu_hw_pp_get_vsync_info;
ops->poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr;
ops->get_line_count = dpu_hw_pp_get_line_count;
-
- version = DPU_COLOR_PROCESS_MAJOR(hw_cap->sblk->dither.version);
- switch (version) {
- case 1:
- ops->setup_dither = dpu_hw_pp_setup_dither_v1;
- break;
- default:
- ops->setup_dither = NULL;
- break;
- }
};

static struct dpu_hw_blk_ops dpu_hw_ops = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
index 7dbfcae4..3caccd7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
@@ -17,7 +17,6 @@
#include "dpu_hw_mdss.h"
#include "dpu_hw_util.h"
#include "dpu_hw_blk.h"
-#include <uapi/drm/msm_drm_pp.h>

struct dpu_hw_pingpong;

@@ -88,11 +87,6 @@ struct dpu_hw_pingpong_ops {
int (*poll_timeout_wr_ptr)(struct dpu_hw_pingpong *pp, u32 timeout_us);

/**
- * Program the dither hw block
- */
- int (*setup_dither)(struct dpu_hw_pingpong *pp, void *cfg, size_t len);
-
- /**
* Obtain current vertical line counter
*/
u32 (*get_line_count)(struct dpu_hw_pingpong *pp);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
deleted file mode 100644
index 7c2772f..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
+++ /dev/null
@@ -1,757 +0,0 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include "dpu_hw_mdss.h"
-#include "dpu_hw_ctl.h"
-#include "dpu_hw_reg_dma_v1.h"
-#include "msm_drv.h"
-#include "msm_kms.h"
-#include "msm_mmu.h"
-
-#define GUARD_BYTES (BIT(8) - 1)
-#define ALIGNED_OFFSET (U32_MAX & ~(GUARD_BYTES))
-#define ADDR_ALIGN BIT(8)
-#define MAX_RELATIVE_OFF (BIT(20) - 1)
-
-#define DECODE_SEL_OP (BIT(HW_BLK_SELECT))
-#define REG_WRITE_OP ((BIT(REG_SINGLE_WRITE)) | (BIT(REG_BLK_WRITE_SINGLE)) | \
- (BIT(REG_BLK_WRITE_INC)) | (BIT(REG_BLK_WRITE_MULTIPLE)))
-
-#define REG_DMA_OPS (DECODE_SEL_OP | REG_WRITE_OP)
-#define IS_OP_ALLOWED(op, buf_op) (BIT(op) & buf_op)
-
-#define REG_DMA_OP_MODE_OFF 0x4
-
-#define REG_DMA_CTL0_QUEUE_0_CMD0_OFF 0x14
-#define REG_DMA_CTL0_RESET_OFF 0xE4
-#define REG_DMA_CTL_TRIGGER_OFF 0xD4
-
-#define SET_UP_REG_DMA_REG(hw, reg_dma) \
- do { \
- (hw).base_off = (reg_dma)->addr; \
- (hw).blk_off = (reg_dma)->caps->base; \
- (hw).hwversion = (reg_dma)->caps->version; \
-} while (0)
-
-#define SIZE_DWORD(x) ((x) / (sizeof(u32)))
-#define NOT_WORD_ALIGNED(x) ((x) & 0x3)
-
-
-#define GRP_VIG_HW_BLK_SELECT (VIG0 | VIG1 | VIG2 | VIG3)
-#define GRP_DSPP_HW_BLK_SELECT (DSPP0 | DSPP1 | DSPP2 | DSPP3)
-#define BUFFER_SPACE_LEFT(cfg) ((cfg)->dma_buf->buffer_size - \
- (cfg)->dma_buf->index)
-
-#define REG_DMA_DECODE_SEL 0x180AC060
-#define SINGLE_REG_WRITE_OPCODE (BIT(28))
-#define REL_ADDR_OPCODE (BIT(27))
-#define HW_INDEX_REG_WRITE_OPCODE (BIT(28) | BIT(29))
-#define AUTO_INC_REG_WRITE_OPCODE (BIT(30))
-#define BLK_REG_WRITE_OPCODE (BIT(30) | BIT(28))
-
-#define WRAP_MIN_SIZE 2
-#define WRAP_MAX_SIZE (BIT(4) - 1)
-#define MAX_DWORDS_SZ (BIT(14) - 1)
-#define REG_DMA_HEADERS_BUFFER_SZ (sizeof(u32) * 128)
-
-typedef int (*reg_dma_internal_ops) (struct dpu_reg_dma_setup_ops_cfg *cfg);
-
-static struct dpu_hw_reg_dma *reg_dma;
-static u32 ops_mem_size[REG_DMA_SETUP_OPS_MAX] = {
- [REG_BLK_WRITE_SINGLE] = sizeof(u32) * 2,
- [REG_BLK_WRITE_INC] = sizeof(u32) * 2,
- [REG_BLK_WRITE_MULTIPLE] = sizeof(u32) * 2,
- [HW_BLK_SELECT] = sizeof(u32) * 2,
- [REG_SINGLE_WRITE] = sizeof(u32) * 2
-};
-
-static u32 queue_sel[DMA_CTL_QUEUE_MAX] = {
- [DMA_CTL_QUEUE0] = BIT(0),
- [DMA_CTL_QUEUE1] = BIT(4),
-};
-
-static u32 reg_dma_ctl_queue_off[CTL_MAX];
-static u32 dspp_read_sel[DSPP_HIST_MAX] = {
- [DSPP0_HIST] = 0,
- [DSPP1_HIST] = 1,
- [DSPP2_HIST] = 2,
- [DSPP3_HIST] = 3,
-};
-
-static u32 v1_supported[REG_DMA_FEATURES_MAX] = {
- [GAMUT] = GRP_VIG_HW_BLK_SELECT | GRP_DSPP_HW_BLK_SELECT,
- [VLUT] = GRP_DSPP_HW_BLK_SELECT,
- [GC] = GRP_DSPP_HW_BLK_SELECT,
- [IGC] = DSPP_IGC | GRP_DSPP_HW_BLK_SELECT,
- [PCC] = GRP_DSPP_HW_BLK_SELECT,
-};
-
-static int validate_dma_cfg(struct dpu_reg_dma_setup_ops_cfg *cfg);
-static int validate_write_decode_sel(struct dpu_reg_dma_setup_ops_cfg *cfg);
-static int validate_write_reg(struct dpu_reg_dma_setup_ops_cfg *cfg);
-static int validate_write_multi_lut_reg(struct dpu_reg_dma_setup_ops_cfg *cfg);
-static int validate_last_cmd(struct dpu_reg_dma_setup_ops_cfg *cfg);
-static int write_decode_sel(struct dpu_reg_dma_setup_ops_cfg *cfg);
-static int write_single_reg(struct dpu_reg_dma_setup_ops_cfg *cfg);
-static int write_multi_reg_index(struct dpu_reg_dma_setup_ops_cfg *cfg);
-static int write_multi_reg_inc(struct dpu_reg_dma_setup_ops_cfg *cfg);
-static int write_multi_lut_reg(struct dpu_reg_dma_setup_ops_cfg *cfg);
-static int write_last_cmd(struct dpu_reg_dma_setup_ops_cfg *cfg);
-static int reset_reg_dma_buffer_v1(struct dpu_reg_dma_buffer *lut_buf);
-static int check_support_v1(enum dpu_reg_dma_features feature,
- enum dpu_reg_dma_blk blk, bool *is_supported);
-static int setup_payload_v1(struct dpu_reg_dma_setup_ops_cfg *cfg);
-static int kick_off_v1(struct dpu_reg_dma_kickoff_cfg *cfg);
-static int reset_v1(struct dpu_hw_ctl *ctl);
-static int last_cmd_v1(struct dpu_hw_ctl *ctl, enum dpu_reg_dma_queue q);
-static struct dpu_reg_dma_buffer *alloc_reg_dma_buf_v1(u32 size);
-static int dealloc_reg_dma_v1(struct dpu_reg_dma_buffer *lut_buf);
-
-static reg_dma_internal_ops write_dma_op_params[REG_DMA_SETUP_OPS_MAX] = {
- [HW_BLK_SELECT] = write_decode_sel,
- [REG_SINGLE_WRITE] = write_single_reg,
- [REG_BLK_WRITE_SINGLE] = write_multi_reg_inc,
- [REG_BLK_WRITE_INC] = write_multi_reg_index,
- [REG_BLK_WRITE_MULTIPLE] = write_multi_lut_reg,
-};
-
-static reg_dma_internal_ops validate_dma_op_params[REG_DMA_SETUP_OPS_MAX] = {
- [HW_BLK_SELECT] = validate_write_decode_sel,
- [REG_SINGLE_WRITE] = validate_write_reg,
- [REG_BLK_WRITE_SINGLE] = validate_write_reg,
- [REG_BLK_WRITE_INC] = validate_write_reg,
- [REG_BLK_WRITE_MULTIPLE] = validate_write_multi_lut_reg,
-};
-
-static struct dpu_reg_dma_buffer *last_cmd_buf;
-
-static void get_decode_sel(unsigned long blk, u32 *decode_sel)
-{
- int i = 0;
-
- *decode_sel = 0;
- for_each_set_bit(i, &blk, 31) {
- switch (BIT(i)) {
- case VIG0:
- *decode_sel |= BIT(0);
- break;
- case VIG1:
- *decode_sel |= BIT(1);
- break;
- case VIG2:
- *decode_sel |= BIT(2);
- break;
- case VIG3:
- *decode_sel |= BIT(3);
- break;
- case DSPP0:
- *decode_sel |= BIT(17);
- break;
- case DSPP1:
- *decode_sel |= BIT(18);
- break;
- case DSPP2:
- *decode_sel |= BIT(19);
- break;
- case DSPP3:
- *decode_sel |= BIT(20);
- break;
- case SSPP_IGC:
- *decode_sel |= BIT(4);
- break;
- case DSPP_IGC:
- *decode_sel |= BIT(21);
- break;
- default:
- DRM_ERROR("block not supported %lx\n", BIT(i));
- break;
- }
- }
-}
-
-static int write_multi_reg(struct dpu_reg_dma_setup_ops_cfg *cfg)
-{
- u8 *loc = NULL;
-
- loc = (u8 *)cfg->dma_buf->vaddr + cfg->dma_buf->index;
- memcpy(loc, cfg->data, cfg->data_size);
- cfg->dma_buf->index += cfg->data_size;
- cfg->dma_buf->next_op_allowed = REG_WRITE_OP | DECODE_SEL_OP;
- cfg->dma_buf->ops_completed |= REG_WRITE_OP;
-
- return 0;
-}
-
-int write_multi_reg_index(struct dpu_reg_dma_setup_ops_cfg *cfg)
-{
- u32 *loc = NULL;
-
- loc = (u32 *)((u8 *)cfg->dma_buf->vaddr +
- cfg->dma_buf->index);
- loc[0] = HW_INDEX_REG_WRITE_OPCODE;
- loc[0] |= (cfg->blk_offset & MAX_RELATIVE_OFF);
- loc[1] = SIZE_DWORD(cfg->data_size);
- cfg->dma_buf->index += ops_mem_size[cfg->ops];
-
- return write_multi_reg(cfg);
-}
-
-int write_multi_reg_inc(struct dpu_reg_dma_setup_ops_cfg *cfg)
-{
- u32 *loc = NULL;
-
- loc = (u32 *)((u8 *)cfg->dma_buf->vaddr +
- cfg->dma_buf->index);
- loc[0] = AUTO_INC_REG_WRITE_OPCODE;
- loc[0] |= (cfg->blk_offset & MAX_RELATIVE_OFF);
- loc[1] = SIZE_DWORD(cfg->data_size);
- cfg->dma_buf->index += ops_mem_size[cfg->ops];
-
- return write_multi_reg(cfg);
-}
-
-static int write_multi_lut_reg(struct dpu_reg_dma_setup_ops_cfg *cfg)
-{
- u32 *loc = NULL;
-
- loc = (u32 *)((u8 *)cfg->dma_buf->vaddr +
- cfg->dma_buf->index);
- loc[0] = BLK_REG_WRITE_OPCODE;
- loc[0] |= (cfg->blk_offset & MAX_RELATIVE_OFF);
- loc[1] = (cfg->inc) ? 0 : BIT(31);
- loc[1] |= (cfg->wrap_size & WRAP_MAX_SIZE) << 16;
- loc[1] |= ((SIZE_DWORD(cfg->data_size)) & MAX_DWORDS_SZ);
- cfg->dma_buf->next_op_allowed = REG_WRITE_OP;
- cfg->dma_buf->index += ops_mem_size[cfg->ops];
-
- return write_multi_reg(cfg);
-}
-
-static int write_single_reg(struct dpu_reg_dma_setup_ops_cfg *cfg)
-{
- u32 *loc = NULL;
-
- loc = (u32 *)((u8 *)cfg->dma_buf->vaddr +
- cfg->dma_buf->index);
- loc[0] = SINGLE_REG_WRITE_OPCODE;
- loc[0] |= (cfg->blk_offset & MAX_RELATIVE_OFF);
- loc[1] = *cfg->data;
- cfg->dma_buf->index += ops_mem_size[cfg->ops];
- cfg->dma_buf->ops_completed |= REG_WRITE_OP;
- cfg->dma_buf->next_op_allowed = REG_WRITE_OP | DECODE_SEL_OP;
-
- return 0;
-}
-
-static int write_decode_sel(struct dpu_reg_dma_setup_ops_cfg *cfg)
-{
- u32 *loc = NULL;
-
- loc = (u32 *)((u8 *)cfg->dma_buf->vaddr +
- cfg->dma_buf->index);
- loc[0] = REG_DMA_DECODE_SEL;
- get_decode_sel(cfg->blk, &loc[1]);
- cfg->dma_buf->index += sizeof(u32) * 2;
- cfg->dma_buf->ops_completed |= DECODE_SEL_OP;
- cfg->dma_buf->next_op_allowed = REG_WRITE_OP;
-
- return 0;
-}
-
-static int validate_write_multi_lut_reg(struct dpu_reg_dma_setup_ops_cfg *cfg)
-{
- int rc;
-
- rc = validate_write_reg(cfg);
- if (rc)
- return rc;
-
- if (cfg->wrap_size < WRAP_MIN_SIZE || cfg->wrap_size > WRAP_MAX_SIZE) {
- DRM_ERROR("invalid wrap sz %d min %d max %ld\n",
- cfg->wrap_size, WRAP_MIN_SIZE, WRAP_MAX_SIZE);
- rc = -EINVAL;
- }
-
- return rc;
-}
-
-static int validate_write_reg(struct dpu_reg_dma_setup_ops_cfg *cfg)
-{
- u32 remain_len, write_len;
-
- remain_len = BUFFER_SPACE_LEFT(cfg);
- write_len = ops_mem_size[cfg->ops] + cfg->data_size;
- if (remain_len < write_len) {
- DRM_ERROR("buffer is full sz %d needs %d bytes\n",
- remain_len, write_len);
- return -EINVAL;
- }
-
- if (!cfg->data) {
- DRM_ERROR("invalid data %pK size %d exp sz %d\n", cfg->data,
- cfg->data_size, write_len);
- return -EINVAL;
- }
- if ((SIZE_DWORD(cfg->data_size)) > MAX_DWORDS_SZ ||
- NOT_WORD_ALIGNED(cfg->data_size)) {
- DRM_ERROR("Invalid data size %d max %ld align %x\n",
- cfg->data_size, MAX_DWORDS_SZ,
- NOT_WORD_ALIGNED(cfg->data_size));
- return -EINVAL;
- }
-
- if (cfg->blk_offset > MAX_RELATIVE_OFF ||
- NOT_WORD_ALIGNED(cfg->blk_offset)) {
- DRM_ERROR("invalid offset %d max %ld align %x\n",
- cfg->blk_offset, MAX_RELATIVE_OFF,
- NOT_WORD_ALIGNED(cfg->blk_offset));
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int validate_write_decode_sel(struct dpu_reg_dma_setup_ops_cfg *cfg)
-{
- u32 remain_len;
-
- remain_len = BUFFER_SPACE_LEFT(cfg);
- if (remain_len < ops_mem_size[HW_BLK_SELECT]) {
- DRM_ERROR("buffer is full needs %d bytes\n",
- ops_mem_size[HW_BLK_SELECT]);
- return -EINVAL;
- }
-
- if (!cfg->blk) {
- DRM_ERROR("blk set as 0\n");
- return -EINVAL;
- }
- /* DSPP and VIG can't be combined */
- if ((cfg->blk & GRP_VIG_HW_BLK_SELECT) &&
- (cfg->blk & GRP_DSPP_HW_BLK_SELECT)) {
- DRM_ERROR("invalid blk combination %x\n",
- cfg->blk);
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int validate_dma_cfg(struct dpu_reg_dma_setup_ops_cfg *cfg)
-{
- int rc = 0;
- bool supported;
-
- if (!cfg || cfg->ops >= REG_DMA_SETUP_OPS_MAX || !cfg->dma_buf) {
- DRM_ERROR("invalid param cfg %pK ops %d dma_buf %pK\n",
- cfg, ((cfg) ? cfg->ops : REG_DMA_SETUP_OPS_MAX),
- ((cfg) ? cfg->dma_buf : NULL));
- return -EINVAL;
- }
-
- rc = check_support_v1(cfg->feature, cfg->blk, &supported);
- if (rc || !supported) {
- DRM_ERROR("check support failed rc %d supported %d\n",
- rc, supported);
- rc = -EINVAL;
- return rc;
- }
-
- if (cfg->dma_buf->index >= cfg->dma_buf->buffer_size ||
- NOT_WORD_ALIGNED(cfg->dma_buf->index)) {
- DRM_ERROR("Buf Overflow index %d max size %d align %x\n",
- cfg->dma_buf->index, cfg->dma_buf->buffer_size,
- NOT_WORD_ALIGNED(cfg->dma_buf->index));
- return -EINVAL;
- }
-
- if (cfg->dma_buf->iova & GUARD_BYTES || !cfg->dma_buf->vaddr) {
- DRM_ERROR("iova not aligned to %lx iova %llx kva %pK",
- ADDR_ALIGN, cfg->dma_buf->iova,
- cfg->dma_buf->vaddr);
- return -EINVAL;
- }
- if (!IS_OP_ALLOWED(cfg->ops, cfg->dma_buf->next_op_allowed)) {
- DRM_ERROR("invalid op %x allowed %x\n", cfg->ops,
- cfg->dma_buf->next_op_allowed);
- return -EINVAL;
- }
-
- if (!validate_dma_op_params[cfg->ops] ||
- !write_dma_op_params[cfg->ops]) {
- DRM_ERROR("invalid op %d validate %pK write %pK\n", cfg->ops,
- validate_dma_op_params[cfg->ops],
- write_dma_op_params[cfg->ops]);
- return -EINVAL;
- }
- return rc;
-}
-
-static int validate_kick_off_v1(struct dpu_reg_dma_kickoff_cfg *cfg)
-{
-
- if (!cfg || !cfg->ctl || !cfg->dma_buf) {
- DRM_ERROR("invalid cfg %pK ctl %pK dma_buf %pK\n",
- cfg, ((!cfg) ? NULL : cfg->ctl),
- ((!cfg) ? NULL : cfg->dma_buf));
- return -EINVAL;
- }
-
- if (cfg->ctl->idx < CTL_0 && cfg->ctl->idx >= CTL_MAX) {
- DRM_ERROR("invalid ctl idx %d\n", cfg->ctl->idx);
- return -EINVAL;
- }
-
- if (cfg->op >= REG_DMA_OP_MAX) {
- DRM_ERROR("invalid op %d\n", cfg->op);
- return -EINVAL;
- }
-
- if ((cfg->op == REG_DMA_WRITE) &&
- (!(cfg->dma_buf->ops_completed & DECODE_SEL_OP) ||
- !(cfg->dma_buf->ops_completed & REG_WRITE_OP))) {
- DRM_ERROR("incomplete write ops %x\n",
- cfg->dma_buf->ops_completed);
- return -EINVAL;
- }
-
- if (cfg->op == REG_DMA_READ && cfg->block_select >= DSPP_HIST_MAX) {
- DRM_ERROR("invalid block for read %d\n", cfg->block_select);
- return -EINVAL;
- }
-
- /* Only immediate triggers are supported now hence hardcode */
- cfg->trigger_mode = (cfg->op == REG_DMA_READ) ? (READ_TRIGGER) :
- (WRITE_TRIGGER);
-
- if (cfg->dma_buf->iova & GUARD_BYTES) {
- DRM_ERROR("Address is not aligned to %lx iova %llx", ADDR_ALIGN,
- cfg->dma_buf->iova);
- return -EINVAL;
- }
-
- if (cfg->queue_select >= DMA_CTL_QUEUE_MAX) {
- DRM_ERROR("invalid queue selected %d\n", cfg->queue_select);
- return -EINVAL;
- }
-
- if (SIZE_DWORD(cfg->dma_buf->index) > MAX_DWORDS_SZ ||
- !cfg->dma_buf->index) {
- DRM_ERROR("invalid dword size %zd max %ld\n",
- SIZE_DWORD(cfg->dma_buf->index), MAX_DWORDS_SZ);
- return -EINVAL;
- }
- return 0;
-}
-
-static int write_kick_off_v1(struct dpu_reg_dma_kickoff_cfg *cfg)
-{
- u32 cmd1;
- struct dpu_hw_blk_reg_map hw;
-
- memset(&hw, 0, sizeof(hw));
- cmd1 = (cfg->op == REG_DMA_READ) ?
- (dspp_read_sel[cfg->block_select] << 30) : 0;
- cmd1 |= (cfg->last_command) ? BIT(24) : 0;
- cmd1 |= (cfg->op == REG_DMA_READ) ? (2 << 22) : 0;
- cmd1 |= (cfg->op == REG_DMA_WRITE) ? (BIT(22)) : 0;
- cmd1 |= (SIZE_DWORD(cfg->dma_buf->index) & MAX_DWORDS_SZ);
-
- SET_UP_REG_DMA_REG(hw, reg_dma);
- DPU_REG_WRITE(&hw, REG_DMA_OP_MODE_OFF, BIT(0));
- DPU_REG_WRITE(&hw, reg_dma_ctl_queue_off[cfg->ctl->idx],
- cfg->dma_buf->iova);
- DPU_REG_WRITE(&hw, reg_dma_ctl_queue_off[cfg->ctl->idx] + 0x4,
- cmd1);
- if (cfg->last_command)
- DPU_REG_WRITE(&cfg->ctl->hw, REG_DMA_CTL_TRIGGER_OFF,
- queue_sel[cfg->queue_select]);
-
- return 0;
-}
-
-int init_v1(struct dpu_hw_reg_dma *cfg)
-{
- int i = 0;
-
- if (!cfg)
- return -EINVAL;
-
- reg_dma = cfg;
- if (!last_cmd_buf) {
- last_cmd_buf = alloc_reg_dma_buf_v1(REG_DMA_HEADERS_BUFFER_SZ);
- if (IS_ERR_OR_NULL(last_cmd_buf))
- return -EINVAL;
- }
- reg_dma->ops.check_support = check_support_v1;
- reg_dma->ops.setup_payload = setup_payload_v1;
- reg_dma->ops.kick_off = kick_off_v1;
- reg_dma->ops.reset = reset_v1;
- reg_dma->ops.alloc_reg_dma_buf = alloc_reg_dma_buf_v1;
- reg_dma->ops.dealloc_reg_dma = dealloc_reg_dma_v1;
- reg_dma->ops.reset_reg_dma_buf = reset_reg_dma_buffer_v1;
- reg_dma->ops.last_command = last_cmd_v1;
-
- reg_dma_ctl_queue_off[CTL_0] = REG_DMA_CTL0_QUEUE_0_CMD0_OFF;
- for (i = CTL_1; i < ARRAY_SIZE(reg_dma_ctl_queue_off); i++)
- reg_dma_ctl_queue_off[i] = reg_dma_ctl_queue_off[i - 1] +
- (sizeof(u32) * 4);
-
- return 0;
-}
-
-static int check_support_v1(enum dpu_reg_dma_features feature,
- enum dpu_reg_dma_blk blk,
- bool *is_supported)
-{
- int ret = 0;
-
- if (!is_supported)
- return -EINVAL;
-
- if (feature >= REG_DMA_FEATURES_MAX || blk >= MDSS) {
- *is_supported = false;
- return ret;
- }
-
- *is_supported = (blk & v1_supported[feature]) ? true : false;
- return ret;
-}
-
-static int setup_payload_v1(struct dpu_reg_dma_setup_ops_cfg *cfg)
-{
- int rc = 0;
-
- rc = validate_dma_cfg(cfg);
-
- if (!rc)
- rc = validate_dma_op_params[cfg->ops](cfg);
-
- if (!rc)
- rc = write_dma_op_params[cfg->ops](cfg);
-
- return rc;
-}
-
-
-static int kick_off_v1(struct dpu_reg_dma_kickoff_cfg *cfg)
-{
- int rc = 0;
-
- rc = validate_kick_off_v1(cfg);
- if (rc)
- return rc;
-
- rc = write_kick_off_v1(cfg);
- return rc;
-}
-
-int reset_v1(struct dpu_hw_ctl *ctl)
-{
- struct dpu_hw_blk_reg_map hw;
- u32 index, val;
-
- if (!ctl || ctl->idx > CTL_MAX) {
- DRM_ERROR("invalid ctl %pK ctl idx %d\n",
- ctl, ((ctl) ? ctl->idx : 0));
- return -EINVAL;
- }
-
- memset(&hw, 0, sizeof(hw));
- index = ctl->idx - CTL_0;
- SET_UP_REG_DMA_REG(hw, reg_dma);
- DPU_REG_WRITE(&hw, REG_DMA_OP_MODE_OFF, BIT(0));
- DPU_REG_WRITE(&hw, (REG_DMA_CTL0_RESET_OFF + index * sizeof(u32)),
- BIT(0));
-
- index = 0;
- do {
- udelay(1000);
- index++;
- val = DPU_REG_READ(&hw,
- (REG_DMA_CTL0_RESET_OFF + index * sizeof(u32)));
- } while (index < 2 && val);
-
- return 0;
-}
-
-static struct dpu_reg_dma_buffer *alloc_reg_dma_buf_v1(u32 size)
-{
- struct dpu_reg_dma_buffer *dma_buf = NULL;
- u32 iova_aligned, offset;
- u32 rsize = size + GUARD_BYTES;
- struct msm_drm_private *priv = reg_dma->drm_dev->dev_private;
- struct msm_gem_address_space *aspace = NULL;
- int rc = 0;
-
- if (!size || SIZE_DWORD(size) > MAX_DWORDS_SZ) {
- DRM_ERROR("invalid buffer size %d\n", size);
- return ERR_PTR(-EINVAL);
- }
-
- dma_buf = kzalloc(sizeof(*dma_buf), GFP_KERNEL);
- if (!dma_buf)
- return ERR_PTR(-ENOMEM);
-
- dma_buf->buf = msm_gem_new(reg_dma->drm_dev,
- rsize, MSM_BO_UNCACHED);
- if (IS_ERR_OR_NULL(dma_buf->buf)) {
- rc = -EINVAL;
- goto fail;
- }
-
- aspace = priv->kms->aspace;
- if (!aspace) {
- DRM_ERROR("failed to get aspace\n");
- rc = -EINVAL;
- goto free_gem;
- }
-
- dma_buf->aspace = aspace;
- rc = msm_gem_get_iova(dma_buf->buf, aspace, &dma_buf->iova);
- if (rc) {
- DRM_ERROR("failed to get the iova rc %d\n", rc);
- goto free_gem;
- }
-
- dma_buf->vaddr = msm_gem_get_vaddr(dma_buf->buf);
- if (IS_ERR_OR_NULL(dma_buf->vaddr)) {
- DRM_ERROR("failed to get va rc %d\n", rc);
- rc = -EINVAL;
- goto put_iova;
- }
-
- dma_buf->buffer_size = size;
- iova_aligned = (dma_buf->iova + GUARD_BYTES) & ALIGNED_OFFSET;
- offset = iova_aligned - dma_buf->iova;
- dma_buf->iova = dma_buf->iova + offset;
- dma_buf->vaddr = (void *)(((u8 *)dma_buf->vaddr) + offset);
- dma_buf->next_op_allowed = DECODE_SEL_OP;
-
- return dma_buf;
-
-put_iova:
- msm_gem_put_iova(dma_buf->buf, aspace);
-free_gem:
- mutex_lock(&reg_dma->drm_dev->struct_mutex);
- msm_gem_free_object(dma_buf->buf);
- mutex_unlock(&reg_dma->drm_dev->struct_mutex);
-fail:
- kfree(dma_buf);
- return ERR_PTR(rc);
-}
-
-static int dealloc_reg_dma_v1(struct dpu_reg_dma_buffer *dma_buf)
-{
- if (!dma_buf) {
- DRM_ERROR("invalid param reg_buf %pK\n", dma_buf);
- return -EINVAL;
- }
-
- if (dma_buf->buf) {
- msm_gem_put_iova(dma_buf->buf, 0);
- mutex_lock(&reg_dma->drm_dev->struct_mutex);
- msm_gem_free_object(dma_buf->buf);
- mutex_unlock(&reg_dma->drm_dev->struct_mutex);
- }
-
- kfree(dma_buf);
- return 0;
-}
-
-static int reset_reg_dma_buffer_v1(struct dpu_reg_dma_buffer *lut_buf)
-{
- if (!lut_buf)
- return -EINVAL;
-
- lut_buf->index = 0;
- lut_buf->ops_completed = 0;
- lut_buf->next_op_allowed = DECODE_SEL_OP;
- return 0;
-}
-
-static int validate_last_cmd(struct dpu_reg_dma_setup_ops_cfg *cfg)
-{
- u32 remain_len, write_len;
-
- remain_len = BUFFER_SPACE_LEFT(cfg);
- write_len = sizeof(u32);
- if (remain_len < write_len) {
- DRM_ERROR("buffer is full sz %d needs %d bytes\n",
- remain_len, write_len);
- return -EINVAL;
- }
- return 0;
-}
-
-static int write_last_cmd(struct dpu_reg_dma_setup_ops_cfg *cfg)
-{
- u32 *loc = NULL;
-
- loc = (u32 *)((u8 *)cfg->dma_buf->vaddr +
- cfg->dma_buf->index);
- loc[0] = REG_DMA_DECODE_SEL;
- loc[1] = 0;
- cfg->dma_buf->index = sizeof(u32) * 2;
- cfg->dma_buf->ops_completed = REG_WRITE_OP | DECODE_SEL_OP;
- cfg->dma_buf->next_op_allowed = REG_WRITE_OP;
-
- return 0;
-}
-
-static int last_cmd_v1(struct dpu_hw_ctl *ctl, enum dpu_reg_dma_queue q)
-{
- struct dpu_reg_dma_setup_ops_cfg cfg;
- struct dpu_reg_dma_kickoff_cfg kick_off;
-
- if (!last_cmd_buf || !ctl || q >= DMA_CTL_QUEUE_MAX) {
- DRM_ERROR("invalid param buf %pK ctl %pK q %d\n", last_cmd_buf,
- ctl, q);
- return -EINVAL;
- }
-
- if (!last_cmd_buf->iova) {
- DRM_DEBUG("iova not set, possible secure session\n");
- return 0;
- }
-
- cfg.dma_buf = last_cmd_buf;
- reset_reg_dma_buffer_v1(last_cmd_buf);
- if (validate_last_cmd(&cfg)) {
- DRM_ERROR("validate buf failed\n");
- return -EINVAL;
- }
-
- if (write_last_cmd(&cfg)) {
- DRM_ERROR("write buf failed\n");
- return -EINVAL;
- }
-
- kick_off.ctl = ctl;
- kick_off.queue_select = q;
- kick_off.trigger_mode = WRITE_IMMEDIATE;
- kick_off.last_command = 1;
- kick_off.op = REG_DMA_WRITE;
- kick_off.dma_buf = last_cmd_buf;
- if (kick_off_v1(&kick_off)) {
- DRM_ERROR("kick off last cmd failed\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-void deinit_v1(void)
-{
- if (last_cmd_buf)
- dealloc_reg_dma_v1(last_cmd_buf);
- last_cmd_buf = NULL;
-}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h
deleted file mode 100644
index 4d784eb..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef _DPU_HW_REG_DMA_V1_H
-#define _DPU_HW_REG_DMA_V1_H
-
-#include "dpu_reg_dma.h"
-
-/**
- * init_v1() - initialize the reg dma v1 driver by installing v1 ops
- * @reg_dma - reg_dma hw info structure exposing capabilities.
- */
-int init_v1(struct dpu_hw_reg_dma *reg_dma);
-
-/**
- * deinit_v1() - free up any resources allocated during the v1 reg dma init
- */
-void deinit_v1(void);
-#endif /* _DPU_HW_REG_DMA_V1_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c
deleted file mode 100644
index d21aa6f..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c
+++ /dev/null
@@ -1,943 +0,0 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <drm/msm_drm_pp.h>
-#include "dpu_reg_dma.h"
-#include "dpu_hw_reg_dma_v1_color_proc.h"
-#include "dpu_hw_color_proc_common_v4.h"
-
-/* Reserve space of 128 words for LUT dma payload set-up */
-#define REG_DMA_HEADERS_BUFFER_SZ (sizeof(u32) * 128)
-
-#define VLUT_MEM_SIZE ((128 * sizeof(u32)) + REG_DMA_HEADERS_BUFFER_SZ)
-#define VLUT_LEN (128 * sizeof(u32))
-#define PA_OP_MODE_OFF 0x800
-#define PA_LUTV_OPMODE_OFF 0x84c
-
-#define GAMUT_LUT_MEM_SIZE ((sizeof(struct drm_msm_3d_gamut)) + \
- REG_DMA_HEADERS_BUFFER_SZ)
-#define GAMUT_SCALE_OFF_LEN (GAMUT_3D_SCALE_OFF_SZ * \
- GAMUT_3D_SCALE_OFF_TBL_NUM * sizeof(u32))
-#define GAMUT_SCALE_OFF_LEN_12 (GAMUT_3D_SCALEB_OFF_SZ * sizeof(u32))
-
-#define GC_LUT_MEM_SIZE ((sizeof(struct drm_msm_pgc_lut)) + \
- REG_DMA_HEADERS_BUFFER_SZ)
-
-#define IGC_LUT_MEM_SIZE ((sizeof(struct drm_msm_igc_lut)) + \
- REG_DMA_HEADERS_BUFFER_SZ)
-
-#define PCC_LUT_ENTRIES (PCC_NUM_PLANES * PCC_NUM_COEFF)
-#define PCC_LEN (PCC_LUT_ENTRIES * sizeof(u32))
-#define PCC_MEM_SIZE (PCC_LEN + \
- REG_DMA_HEADERS_BUFFER_SZ)
-
-#define REG_MASK(n) ((BIT(n)) - 1)
-
-static struct dpu_reg_dma_buffer *dspp_buf[REG_DMA_FEATURES_MAX][DSPP_MAX];
-
-static u32 feature_map[DPU_DSPP_MAX] = {
- [DPU_DSPP_VLUT] = REG_DMA_FEATURES_MAX,
- [DPU_DSPP_GAMUT] = GAMUT,
- [DPU_DSPP_IGC] = IGC,
- [DPU_DSPP_PCC] = PCC,
- [DPU_DSPP_GC] = GC,
- [DPU_DSPP_HSIC] = REG_DMA_FEATURES_MAX,
- [DPU_DSPP_MEMCOLOR] = REG_DMA_FEATURES_MAX,
- [DPU_DSPP_SIXZONE] = REG_DMA_FEATURES_MAX,
- [DPU_DSPP_DITHER] = REG_DMA_FEATURES_MAX,
- [DPU_DSPP_HIST] = REG_DMA_FEATURES_MAX,
- [DPU_DSPP_AD] = REG_DMA_FEATURES_MAX,
-};
-
-static u32 feature_reg_dma_sz[DPU_DSPP_MAX] = {
- [DPU_DSPP_VLUT] = VLUT_MEM_SIZE,
- [DPU_DSPP_GAMUT] = GAMUT_LUT_MEM_SIZE,
- [DPU_DSPP_GC] = GC_LUT_MEM_SIZE,
- [DPU_DSPP_IGC] = IGC_LUT_MEM_SIZE,
- [DPU_DSPP_PCC] = PCC_MEM_SIZE,
-};
-
-static u32 dspp_mapping[DSPP_MAX] = {
- [DSPP_0] = DSPP0,
- [DSPP_1] = DSPP1,
- [DSPP_2] = DSPP2,
- [DSPP_3] = DSPP3,
-};
-
-#define REG_DMA_INIT_OPS(cfg, block, reg_dma_feature, feature_dma_buf) \
- do { \
- memset(&cfg, 0, sizeof(cfg)); \
- (cfg).blk = block; \
- (cfg).feature = reg_dma_feature; \
- (cfg).dma_buf = feature_dma_buf; \
- } while (0)
-
-#define REG_DMA_SETUP_OPS(cfg, block_off, data_ptr, data_len, op, \
- wrap_sz, wrap_inc) \
- do { \
- (cfg).ops = op; \
- (cfg).blk_offset = block_off; \
- (cfg).data_size = data_len; \
- (cfg).data = data_ptr; \
- (cfg).inc = wrap_inc; \
- (cfg).wrap_size = wrap_sz; \
- } while (0)
-
-#define REG_DMA_SETUP_KICKOFF(cfg, hw_ctl, feature_dma_buf, ops, ctl_q, \
- mode) \
- do { \
- memset(&cfg, 0, sizeof(cfg)); \
- (cfg).ctl = hw_ctl; \
- (cfg).dma_buf = feature_dma_buf; \
- (cfg).op = ops; \
- (cfg).queue_select = ctl_q; \
- (cfg).trigger_mode = mode; \
- } while (0)
-
-static int reg_dma_buf_init(struct dpu_reg_dma_buffer **buf, u32 sz);
-static int reg_dma_dspp_check(struct dpu_hw_dspp *ctx, void *cfg,
- enum dpu_reg_dma_features feature);
-static int reg_dma_blk_select(enum dpu_reg_dma_features feature,
- enum dpu_reg_dma_blk blk, struct dpu_reg_dma_buffer *dma_buf);
-static int reg_dma_write(enum dpu_reg_dma_setup_ops ops, u32 off, u32 data_sz,
- u32 *data, struct dpu_reg_dma_buffer *dma_buf,
- enum dpu_reg_dma_features feature,
- enum dpu_reg_dma_blk blk);
-static int reg_dma_kick_off(enum dpu_reg_dma_op op, enum dpu_reg_dma_queue q,
- enum dpu_reg_dma_trigger_mode mode,
- struct dpu_reg_dma_buffer *dma_buf, struct dpu_hw_ctl *ctl);
-
-static int reg_dma_buf_init(struct dpu_reg_dma_buffer **buf, u32 size)
-{
- struct dpu_hw_reg_dma_ops *dma_ops;
-
- dma_ops = dpu_reg_dma_get_ops();
- if (IS_ERR_OR_NULL(dma_ops))
- return -ENOTSUPP;
-
- if (!buf) {
- DRM_ERROR("invalid buf\n");
- return -EINVAL;
- }
-
- /* buffer already initialized */
- if (*buf)
- return 0;
-
- *buf = dma_ops->alloc_reg_dma_buf(size);
- if (IS_ERR_OR_NULL(*buf))
- return -EINVAL;
-
- return 0;
-}
-
-static int reg_dma_dspp_check(struct dpu_hw_dspp *ctx, void *cfg,
- enum dpu_reg_dma_features feature)
-{
- struct dpu_hw_reg_dma_ops *dma_ops;
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
-
- if (!cfg || !ctx) {
- DRM_ERROR("invalid cfg %pK ctx %pK\n", cfg, ctx);
- return -EINVAL;
- }
-
- dma_ops = dpu_reg_dma_get_ops();
- if (IS_ERR_OR_NULL(dma_ops))
- return -EINVAL;
-
- if (!hw_cfg->ctl || ctx->idx >= DSPP_MAX ||
- feature >= REG_DMA_FEATURES_MAX) {
- DRM_ERROR("invalid ctl %pK dspp idx %d feature %d\n",
- hw_cfg->ctl, ctx->idx, feature);
- return -EINVAL;
- }
-
- if (!dspp_buf[feature][ctx->idx]) {
- DRM_ERROR("invalid dma_buf\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int reg_dma_blk_select(enum dpu_reg_dma_features feature,
- enum dpu_reg_dma_blk blk, struct dpu_reg_dma_buffer *dma_buf)
-{
- struct dpu_hw_reg_dma_ops *dma_ops;
- struct dpu_reg_dma_setup_ops_cfg dma_write_cfg;
- int rc = 0;
-
- dma_ops = dpu_reg_dma_get_ops();
- dma_ops->reset_reg_dma_buf(dma_buf);
- memset(&dma_write_cfg, 0, sizeof(dma_write_cfg));
- dma_write_cfg.blk = blk;
- dma_write_cfg.feature = feature;
- dma_write_cfg.ops = HW_BLK_SELECT;
- dma_write_cfg.dma_buf = dma_buf;
-
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc)
- DRM_ERROR("write decode select failed ret %d\n", rc);
-
- return rc;
-}
-
-static int reg_dma_write(enum dpu_reg_dma_setup_ops ops, u32 off, u32 data_sz,
- u32 *data, struct dpu_reg_dma_buffer *dma_buf,
- enum dpu_reg_dma_features feature,
- enum dpu_reg_dma_blk blk)
-{
- struct dpu_hw_reg_dma_ops *dma_ops;
- struct dpu_reg_dma_setup_ops_cfg dma_write_cfg;
- int rc;
-
- dma_ops = dpu_reg_dma_get_ops();
- memset(&dma_write_cfg, 0, sizeof(dma_write_cfg));
-
- dma_write_cfg.ops = ops;
- dma_write_cfg.blk_offset = off;
- dma_write_cfg.data_size = data_sz;
- dma_write_cfg.data = data;
- dma_write_cfg.dma_buf = dma_buf;
- dma_write_cfg.feature = feature;
- dma_write_cfg.blk = blk;
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc)
- DRM_ERROR("write single reg failed ret %d\n", rc);
-
- return rc;
-}
-
-static int reg_dma_kick_off(enum dpu_reg_dma_op op, enum dpu_reg_dma_queue q,
- enum dpu_reg_dma_trigger_mode mode,
- struct dpu_reg_dma_buffer *dma_buf, struct dpu_hw_ctl *ctl)
-{
- struct dpu_reg_dma_kickoff_cfg kick_off;
- struct dpu_hw_reg_dma_ops *dma_ops;
- int rc;
-
- dma_ops = dpu_reg_dma_get_ops();
- memset(&kick_off, 0, sizeof(kick_off));
- kick_off.ctl = ctl;
- kick_off.dma_buf = dma_buf;
- kick_off.op = op;
- kick_off.queue_select = q;
- kick_off.trigger_mode = mode;
- rc = dma_ops->kick_off(&kick_off);
- if (rc)
- DRM_ERROR("failed to kick off ret %d\n", rc);
-
- return rc;
-}
-
-int reg_dmav1_init_dspp_op_v4(int feature, enum dpu_dspp idx)
-{
- int rc = -ENOTSUPP;
- struct dpu_hw_reg_dma_ops *dma_ops;
- bool is_supported = false;
- u32 blk;
-
- if (feature >= DPU_DSPP_MAX || idx >= DSPP_MAX) {
- DRM_ERROR("invalid feature %x max %x dspp idx %x max %xd\n",
- feature, DPU_DSPP_MAX, idx, DSPP_MAX);
- return rc;
- }
-
- if (feature_map[feature] >= REG_DMA_FEATURES_MAX) {
- DRM_ERROR("invalid feature map %d for feature %d\n",
- feature_map[feature], feature);
- return -ENOTSUPP;
- }
-
- dma_ops = dpu_reg_dma_get_ops();
- if (IS_ERR_OR_NULL(dma_ops))
- return -ENOTSUPP;
-
- blk = (feature_map[feature] == IGC) ? DSPP_IGC : dspp_mapping[idx];
- rc = dma_ops->check_support(feature_map[feature], blk, &is_supported);
- if (!rc)
- rc = (is_supported) ? 0 : -ENOTSUPP;
-
- if (!rc)
- rc = reg_dma_buf_init(&dspp_buf[feature_map[feature]][idx],
- feature_reg_dma_sz[feature]);
-
- return rc;
-}
-
-int reg_dmav1_init_sspp_op_v4(int feature, enum dpu_sspp idx)
-{
- return -ENOTSUPP;
-}
-
-void reg_dmav1_setup_dspp_vlutv18(struct dpu_hw_dspp *ctx, void *cfg)
-{
- struct drm_msm_pa_vlut *payload = NULL;
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
- u32 op_mode;
- u32 *data = NULL;
- int i, j, rc = 0;
-
- rc = reg_dma_dspp_check(ctx, cfg, VLUT);
- if (rc)
- return;
-
- op_mode = DPU_REG_READ(&ctx->hw, PA_OP_MODE_OFF);
- if (!hw_cfg->payload) {
- DRM_DEBUG_DRIVER("Disable vlut feature\n");
- DPU_REG_WRITE(&ctx->hw, PA_LUTV_OPMODE_OFF, 0);
- if (op_mode & (~(BIT(20))))
- op_mode = 0;
- DPU_REG_WRITE(&ctx->hw, PA_OP_MODE_OFF, op_mode);
- return;
- }
-
- rc = reg_dma_blk_select(VLUT, dspp_mapping[ctx->idx],
- dspp_buf[VLUT][ctx->idx]);
- if (rc) {
- DRM_ERROR("write decode select failed ret %d\n", rc);
- return;
- }
-
- data = kzalloc(VLUT_LEN, GFP_KERNEL);
- if (!data)
- return;
-
- payload = hw_cfg->payload;
- DRM_DEBUG_DRIVER("Enable vlut feature flags %llx\n", payload->flags);
- for (i = 0, j = 0; i < ARRAY_SIZE(payload->val); i += 2, j++)
- data[j] = (payload->val[i] & REG_MASK(10)) |
- ((payload->val[i + 1] & REG_MASK(10)) << 16);
-
- rc = reg_dma_write(REG_BLK_WRITE_SINGLE, ctx->cap->sblk->vlut.base,
- VLUT_LEN, data,
- dspp_buf[VLUT][ctx->idx], VLUT,
- dspp_mapping[ctx->idx]);
- if (rc) {
- DRM_ERROR("write single reg failed ret %d\n", rc);
- goto exit;
- }
-
- rc = reg_dma_kick_off(REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE,
- dspp_buf[VLUT][ctx->idx], hw_cfg->ctl);
- if (rc) {
- DRM_ERROR("failed to kick off ret %d\n", rc);
- goto exit;
- }
- DPU_REG_WRITE(&ctx->hw, PA_LUTV_OPMODE_OFF, BIT(0));
- DPU_REG_WRITE(&ctx->hw, PA_OP_MODE_OFF, op_mode | BIT(20));
-
-exit:
- kfree(data);
-}
-
-static int dpu_gamut_get_mode_info(struct drm_msm_3d_gamut *payload,
- u32 *tbl_len, u32 *tbl_off, u32 *opcode, u32 *scale_off)
-{
- int rc = 0;
-
- if (payload->mode > GAMUT_3D_MODE_13) {
- DRM_ERROR("invalid mode %d", payload->mode);
- return -EINVAL;
- }
-
- switch (payload->mode) {
- case GAMUT_3D_MODE_17:
- *tbl_len = GAMUT_3D_MODE17_TBL_SZ * sizeof(u32) * 2;
- *tbl_off = 0;
- *scale_off = GAMUT_SCALEA_OFFSET_OFF;
- *opcode = gamut_mode_17 << 2;
- break;
- case GAMUT_3D_MODE_5:
- *tbl_len = GAMUT_3D_MODE5_TBL_SZ * sizeof(u32) * 2;
- *tbl_off = GAMUT_MODE_5_OFF;
- *scale_off = GAMUT_SCALEB_OFFSET_OFF;
- *opcode = gamut_mode_5 << 2;
- break;
- case GAMUT_3D_MODE_13:
- *tbl_len = GAMUT_3D_MODE13_TBL_SZ * sizeof(u32) * 2;
- *opcode = (*opcode & (BIT(4) - 1)) >> 2;
- if (*opcode == gamut_mode_13a)
- *opcode = gamut_mode_13b;
- else
- *opcode = gamut_mode_13a;
- *tbl_off = (*opcode == gamut_mode_13a) ? 0 :
- GAMUT_MODE_13B_OFF;
- *scale_off = (*opcode == gamut_mode_13a) ?
- GAMUT_SCALEA_OFFSET_OFF : GAMUT_SCALEB_OFFSET_OFF;
- *opcode <<= 2;
- break;
- default:
- rc = -EINVAL;
- break;
- }
- if (payload->flags & GAMUT_3D_MAP_EN)
- *opcode |= GAMUT_MAP_EN;
- *opcode |= GAMUT_EN;
-
- return rc;
-}
-
-static void dspp_3d_gamutv4_off(struct dpu_hw_dspp *ctx, void *cfg)
-{
- struct dpu_reg_dma_kickoff_cfg kick_off;
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
- u32 op_mode = 0;
- struct dpu_hw_reg_dma_ops *dma_ops;
- struct dpu_reg_dma_setup_ops_cfg dma_write_cfg;
- int rc;
-
- dma_ops = dpu_reg_dma_get_ops();
- dma_ops->reset_reg_dma_buf(dspp_buf[GAMUT][ctx->idx]);
-
- REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx], GAMUT,
- dspp_buf[GAMUT][ctx->idx]);
-
- REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("write decode select failed ret %d\n", rc);
- return;
- }
-
- REG_DMA_SETUP_OPS(dma_write_cfg,
- ctx->cap->sblk->gamut.base,
- &op_mode, sizeof(op_mode), REG_SINGLE_WRITE, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("opmode write single reg failed ret %d\n", rc);
- return;
- }
-
- REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, dspp_buf[GAMUT][ctx->idx],
- REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);
- rc = dma_ops->kick_off(&kick_off);
- if (rc)
- DRM_ERROR("failed to kick off ret %d\n", rc);
-}
-
-void reg_dmav1_setup_dspp_3d_gamutv4(struct dpu_hw_dspp *ctx, void *cfg)
-{
- struct drm_msm_3d_gamut *payload;
- struct dpu_reg_dma_kickoff_cfg kick_off;
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
- u32 op_mode, reg, tbl_len, tbl_off, scale_off, i;
- u32 scale_tbl_len, scale_tbl_off;
- u32 *scale_data;
- struct dpu_reg_dma_setup_ops_cfg dma_write_cfg;
- struct dpu_hw_reg_dma_ops *dma_ops;
- int rc;
-
- rc = reg_dma_dspp_check(ctx, cfg, GAMUT);
- if (rc)
- return;
-
- op_mode = DPU_REG_READ(&ctx->hw, ctx->cap->sblk->gamut.base);
- if (!hw_cfg->payload) {
- DRM_DEBUG_DRIVER("disable gamut feature\n");
- dspp_3d_gamutv4_off(ctx, cfg);
- return;
- }
-
- if (hw_cfg->len != sizeof(struct drm_msm_3d_gamut)) {
- DRM_ERROR("invalid size of payload len %d exp %zd\n",
- hw_cfg->len, sizeof(struct drm_msm_3d_gamut));
- return;
- }
- payload = hw_cfg->payload;
- rc = dpu_gamut_get_mode_info(payload, &tbl_len, &tbl_off, &op_mode,
- &scale_off);
- if (rc) {
- DRM_ERROR("invalid mode info rc %d\n", rc);
- return;
- }
-
- dma_ops = dpu_reg_dma_get_ops();
- dma_ops->reset_reg_dma_buf(dspp_buf[GAMUT][ctx->idx]);
-
- REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx], GAMUT,
- dspp_buf[GAMUT][ctx->idx]);
-
- REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("write decode select failed ret %d\n", rc);
- return;
- }
- for (i = 0; i < GAMUT_3D_TBL_NUM; i++) {
- reg = GAMUT_TABLE0_SEL << i;
- reg |= ((tbl_off) & (BIT(11) - 1));
- REG_DMA_SETUP_OPS(dma_write_cfg,
- ctx->cap->sblk->gamut.base + GAMUT_TABLE_SEL_OFF,
- &reg, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("write tbl sel reg failed ret %d\n", rc);
- return;
- }
- REG_DMA_SETUP_OPS(dma_write_cfg,
- ctx->cap->sblk->gamut.base + GAMUT_LOWER_COLOR_OFF,
- &payload->col[i][0].c2_c1, tbl_len,
- REG_BLK_WRITE_MULTIPLE, 2, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("write color reg failed ret %d\n", rc);
- return;
- }
- }
-
- if (op_mode & GAMUT_MAP_EN) {
- if (scale_off == GAMUT_SCALEA_OFFSET_OFF)
- scale_tbl_len = GAMUT_SCALE_OFF_LEN;
- else
- scale_tbl_len = GAMUT_SCALE_OFF_LEN_12;
-
- for (i = 0; i < GAMUT_3D_SCALE_OFF_TBL_NUM; i++) {
- scale_tbl_off = ctx->cap->sblk->gamut.base + scale_off +
- (i * scale_tbl_len);
- scale_data = &payload->scale_off[i][0];
- REG_DMA_SETUP_OPS(dma_write_cfg, scale_tbl_off,
- scale_data, scale_tbl_len,
- REG_BLK_WRITE_SINGLE, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("write scale/off reg failed ret %d\n",
- rc);
- return;
- }
- }
- }
-
- REG_DMA_SETUP_OPS(dma_write_cfg,
- ctx->cap->sblk->gamut.base,
- &op_mode, sizeof(op_mode), REG_SINGLE_WRITE, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("opmode write single reg failed ret %d\n", rc);
- return;
- }
-
- REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, dspp_buf[GAMUT][ctx->idx],
- REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);
- rc = dma_ops->kick_off(&kick_off);
- if (rc)
- DRM_ERROR("failed to kick off ret %d\n", rc);
-}
-
-void reg_dmav1_setup_dspp_gcv18(struct dpu_hw_dspp *ctx, void *cfg)
-{
- struct drm_msm_pgc_lut *lut_cfg;
- struct dpu_hw_reg_dma_ops *dma_ops;
- struct dpu_reg_dma_kickoff_cfg kick_off;
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
- struct dpu_reg_dma_setup_ops_cfg dma_write_cfg;
- int rc, i = 0;
- u32 reg;
-
- rc = reg_dma_dspp_check(ctx, cfg, GC);
- if (rc)
- return;
-
- if (!hw_cfg->payload) {
- DRM_DEBUG_DRIVER("disable pgc feature\n");
- DPU_REG_WRITE(&ctx->hw, ctx->cap->sblk->gc.base, 0);
- return;
- }
-
- if (hw_cfg->len != sizeof(struct drm_msm_pgc_lut)) {
- DRM_ERROR("invalid size of payload len %d exp %zd\n",
- hw_cfg->len, sizeof(struct drm_msm_pgc_lut));
- return;
- }
- lut_cfg = hw_cfg->payload;
-
- dma_ops = dpu_reg_dma_get_ops();
- dma_ops->reset_reg_dma_buf(dspp_buf[GC][ctx->idx]);
-
- REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx], GC,
- dspp_buf[GC][ctx->idx]);
-
- REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("write decode select failed ret %d\n", rc);
- return;
- }
-
- for (i = 0; i < GC_TBL_NUM; i++) {
- reg = 0;
- REG_DMA_SETUP_OPS(dma_write_cfg,
- ctx->cap->sblk->gc.base + GC_C0_INDEX_OFF +
- (i * sizeof(u32) * 2),
- &reg, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("index init failed ret %d\n", rc);
- return;
- }
-
- REG_DMA_SETUP_OPS(dma_write_cfg,
- ctx->cap->sblk->gc.base + GC_C0_OFF +
- (i * sizeof(u32) * 2),
- lut_cfg->c0 + (ARRAY_SIZE(lut_cfg->c0) * i),
- PGC_TBL_LEN * sizeof(u32),
- REG_BLK_WRITE_INC, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("lut write failed ret %d\n", rc);
- return;
- }
- }
-
- reg = BIT(0);
- REG_DMA_SETUP_OPS(dma_write_cfg,
- ctx->cap->sblk->gc.base + GC_LUT_SWAP_OFF,
- &reg, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("setting swap offset failed ret %d\n", rc);
- return;
- }
-
- reg = GC_EN | ((lut_cfg->flags & PGC_8B_ROUND) ? GC_8B_ROUND_EN : 0);
- REG_DMA_SETUP_OPS(dma_write_cfg,
- ctx->cap->sblk->gc.base,
- &reg, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("enabling gamma correction failed ret %d\n", rc);
- return;
- }
-
- REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, dspp_buf[GC][ctx->idx],
- REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);
- rc = dma_ops->kick_off(&kick_off);
- if (rc) {
- DRM_ERROR("failed to kick off ret %d\n", rc);
- return;
- }
-}
-
-static void _dspp_igcv31_off(struct dpu_hw_dspp *ctx, void *cfg)
-{
- struct dpu_reg_dma_kickoff_cfg kick_off;
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
- struct dpu_hw_reg_dma_ops *dma_ops;
- struct dpu_reg_dma_setup_ops_cfg dma_write_cfg;
- int rc;
- u32 reg;
-
- dma_ops = dpu_reg_dma_get_ops();
- dma_ops->reset_reg_dma_buf(dspp_buf[IGC][ctx->idx]);
-
- REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx], IGC,
- dspp_buf[IGC][ctx->idx]);
-
- REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("write decode select failed ret %d\n", rc);
- return;
- }
-
- reg = IGC_DIS;
- REG_DMA_SETUP_OPS(dma_write_cfg,
- ctx->cap->sblk->igc.base + IGC_OPMODE_OFF,
- &reg, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("setting opcode failed ret %d\n", rc);
- return;
- }
-
- REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, dspp_buf[IGC][ctx->idx],
- REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);
- rc = dma_ops->kick_off(&kick_off);
- if (rc)
- DRM_ERROR("failed to kick off ret %d\n", rc);
-}
-
-void reg_dmav1_setup_dspp_igcv31(struct dpu_hw_dspp *ctx, void *cfg)
-{
- struct drm_msm_igc_lut *lut_cfg;
- struct dpu_hw_reg_dma_ops *dma_ops;
- struct dpu_reg_dma_kickoff_cfg kick_off;
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
- struct dpu_reg_dma_setup_ops_cfg dma_write_cfg;
- int rc, i = 0, j = 0;
- u32 *addr = NULL;
- u32 offset = 0;
- u32 reg;
-
- rc = reg_dma_dspp_check(ctx, cfg, IGC);
- if (rc)
- return;
-
- if (!hw_cfg->payload) {
- DRM_DEBUG_DRIVER("disable igc feature\n");
- _dspp_igcv31_off(ctx, cfg);
- return;
- }
-
- if (hw_cfg->len != sizeof(struct drm_msm_igc_lut)) {
- DRM_ERROR("invalid size of payload len %d exp %zd\n",
- hw_cfg->len, sizeof(struct drm_msm_igc_lut));
- return;
- }
-
- lut_cfg = hw_cfg->payload;
-
- dma_ops = dpu_reg_dma_get_ops();
- dma_ops->reset_reg_dma_buf(dspp_buf[IGC][ctx->idx]);
-
- REG_DMA_INIT_OPS(dma_write_cfg, DSPP_IGC, IGC, dspp_buf[IGC][ctx->idx]);
-
- REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("write decode select failed ret %d\n", rc);
- return;
- }
-
- for (i = 0; i < IGC_TBL_NUM; i++) {
- addr = lut_cfg->c0 + (i * ARRAY_SIZE(lut_cfg->c0));
- offset = IGC_C0_OFF + (i * sizeof(u32));
-
- for (j = 0; j < IGC_TBL_LEN; j++) {
- addr[j] &= IGC_DATA_MASK;
- addr[j] |= IGC_DSPP_SEL_MASK(ctx->idx - 1);
- if (j == 0)
- addr[j] |= IGC_INDEX_UPDATE;
- }
-
- REG_DMA_SETUP_OPS(dma_write_cfg, offset, addr,
- IGC_TBL_LEN * sizeof(u32),
- REG_BLK_WRITE_INC, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("lut write failed ret %d\n", rc);
- return;
- }
- }
-
- REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx], IGC,
- dspp_buf[IGC][ctx->idx]);
-
- REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("write decode select failed ret %d\n", rc);
- return;
- }
-
- if (lut_cfg->flags & IGC_DITHER_ENABLE) {
- reg = lut_cfg->strength & IGC_DITHER_DATA_MASK;
- REG_DMA_SETUP_OPS(dma_write_cfg,
- ctx->cap->sblk->igc.base + IGC_DITHER_OFF,
- &reg, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("dither strength failed ret %d\n", rc);
- return;
- }
- }
-
- reg = IGC_EN;
- REG_DMA_SETUP_OPS(dma_write_cfg,
- ctx->cap->sblk->igc.base + IGC_OPMODE_OFF,
- &reg, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("setting opcode failed ret %d\n", rc);
- return;
- }
-
- REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, dspp_buf[IGC][ctx->idx],
- REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);
- rc = dma_ops->kick_off(&kick_off);
- if (rc)
- DRM_ERROR("failed to kick off ret %d\n", rc);
-}
-
-static void _dspp_pccv4_off(struct dpu_hw_dspp *ctx, void *cfg)
-{
- struct dpu_reg_dma_kickoff_cfg kick_off;
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
- struct dpu_hw_reg_dma_ops *dma_ops;
- struct dpu_reg_dma_setup_ops_cfg dma_write_cfg;
- int rc;
- u32 reg;
-
- dma_ops = dpu_reg_dma_get_ops();
- dma_ops->reset_reg_dma_buf(dspp_buf[PCC][ctx->idx]);
-
- REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx], PCC,
- dspp_buf[PCC][ctx->idx]);
-
- REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("write decode select failed ret %d\n", rc);
- return;
- }
-
- reg = PCC_DIS;
- REG_DMA_SETUP_OPS(dma_write_cfg,
- ctx->cap->sblk->pcc.base,
- &reg, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("setting opcode failed ret %d\n", rc);
- return;
- }
-
- REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, dspp_buf[PCC][ctx->idx],
- REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);
- rc = dma_ops->kick_off(&kick_off);
- if (rc)
- DRM_ERROR("failed to kick off ret %d\n", rc);
-}
-
-void reg_dmav1_setup_dspp_pccv4(struct dpu_hw_dspp *ctx, void *cfg)
-{
- struct dpu_hw_reg_dma_ops *dma_ops;
- struct dpu_reg_dma_kickoff_cfg kick_off;
- struct dpu_hw_cp_cfg *hw_cfg = cfg;
- struct dpu_reg_dma_setup_ops_cfg dma_write_cfg;
- struct drm_msm_pcc *pcc_cfg;
- struct drm_msm_pcc_coeff *coeffs = NULL;
- u32 *data = NULL;
- int rc, i = 0;
- u32 reg = 0;
-
- rc = reg_dma_dspp_check(ctx, cfg, PCC);
- if (rc)
- return;
-
- if (!hw_cfg->payload) {
- DRM_DEBUG_DRIVER("disable pcc feature\n");
- _dspp_pccv4_off(ctx, cfg);
- return;
- }
-
- if (hw_cfg->len != sizeof(struct drm_msm_pcc)) {
- DRM_ERROR("invalid size of payload len %d exp %zd\n",
- hw_cfg->len, sizeof(struct drm_msm_pcc));
- return;
- }
-
- pcc_cfg = hw_cfg->payload;
-
- dma_ops = dpu_reg_dma_get_ops();
- dma_ops->reset_reg_dma_buf(dspp_buf[PCC][ctx->idx]);
-
- REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx],
- PCC, dspp_buf[PCC][ctx->idx]);
-
- REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("write decode select failed ret %d\n", rc);
- return;
- }
-
- data = kzalloc(PCC_LEN, GFP_KERNEL);
- if (!data)
- return;
-
- for (i = 0; i < PCC_NUM_PLANES; i++) {
- switch (i) {
- case 0:
- coeffs = &pcc_cfg->r;
- data[i + 24] = pcc_cfg->r_rr;
- data[i + 27] = pcc_cfg->r_gg;
- data[i + 30] = pcc_cfg->r_bb;
- break;
- case 1:
- coeffs = &pcc_cfg->g;
- data[i + 24] = pcc_cfg->g_rr;
- data[i + 27] = pcc_cfg->g_gg;
- data[i + 30] = pcc_cfg->g_bb;
- break;
- case 2:
- coeffs = &pcc_cfg->b;
- data[i + 24] = pcc_cfg->b_rr;
- data[i + 27] = pcc_cfg->b_gg;
- data[i + 30] = pcc_cfg->b_bb;
- break;
- default:
- DRM_ERROR("invalid pcc plane: %d\n", i);
- goto exit;
- }
-
- data[i] = coeffs->c;
- data[i + 3] = coeffs->r;
- data[i + 6] = coeffs->g;
- data[i + 9] = coeffs->b;
- data[i + 12] = coeffs->rg;
- data[i + 15] = coeffs->rb;
- data[i + 18] = coeffs->gb;
- data[i + 21] = coeffs->rgb;
- }
-
- REG_DMA_SETUP_OPS(dma_write_cfg,
- ctx->cap->sblk->pcc.base + PCC_C_OFF,
- data, PCC_LEN,
- REG_BLK_WRITE_SINGLE, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("write pcc lut failed ret %d\n", rc);
- goto exit;
- }
-
- reg = PCC_EN;
- REG_DMA_SETUP_OPS(dma_write_cfg,
- ctx->cap->sblk->pcc.base,
- &reg, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
- rc = dma_ops->setup_payload(&dma_write_cfg);
- if (rc) {
- DRM_ERROR("setting opcode failed ret %d\n", rc);
- goto exit;
- }
-
- REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, dspp_buf[PCC][ctx->idx],
- REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);
- rc = dma_ops->kick_off(&kick_off);
- if (rc)
- DRM_ERROR("failed to kick off ret %d\n", rc);
-
-exit:
- kfree(data);
-}
-
-int reg_dmav1_deinit_dspp_ops(enum dpu_dspp idx)
-{
- int i;
- struct dpu_hw_reg_dma_ops *dma_ops;
-
- dma_ops = dpu_reg_dma_get_ops();
- if (IS_ERR_OR_NULL(dma_ops))
- return -ENOTSUPP;
-
- if (idx >= DSPP_MAX) {
- DRM_ERROR("invalid dspp idx %x max %xd\n", idx, DSPP_MAX);
- return -EINVAL;
- }
-
- for (i = 0; i < REG_DMA_FEATURES_MAX; i++) {
- if (!dspp_buf[i][idx])
- continue;
- dma_ops->dealloc_reg_dma(dspp_buf[i][idx]);
- dspp_buf[i][idx] = NULL;
- }
- return 0;
-}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h
deleted file mode 100644
index 5c33399..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef _DPU_HW_REG_DMA_V1_COLOR_PROC_H
-#define _DPU_HW_REG_DMA_V1_COLOR_PROC_H
-
-#include "dpu_hw_util.h"
-#include "dpu_hw_catalog.h"
-#include "dpu_hw_dspp.h"
-
-/**
- * reg_dmav1_init_dspp_op_v4() - initialize the dspp feature op for dpu v4
- * using reg dma v1.
- * @feature: dspp feature
- * idx: dspp idx
- */
-int reg_dmav1_init_dspp_op_v4(int feature, enum dpu_dspp idx);
-
-/**
- * reg_dma_init_sspp_op_v4() - initialize the sspp feature op for dpu v4
- * @feature: sspp feature
- * @idx: sspp idx
- */
-int reg_dmav1_init_sspp_op_v4(int feature, enum dpu_sspp idx);
-
-/**
- * reg_dmav1_setup_dspp_vlutv18() - vlut v18 implementation using reg dma v1.
- * @ctx: dspp ctx info
- * @cfg: pointer to struct dpu_hw_cp_cfg
- */
-void reg_dmav1_setup_dspp_vlutv18(struct dpu_hw_dspp *ctx, void *cfg);
-
-/**
- * reg_dmav1_setup_3d_gamutv4() - gamut v4 implementation using reg dma v1.
- * @ctx: dspp ctx info
- * @cfg: pointer to struct dpu_hw_cp_cfg
- */
-void reg_dmav1_setup_dspp_3d_gamutv4(struct dpu_hw_dspp *ctx, void *cfg);
-
-/**
- * reg_dmav1_setup_dspp_gcv18() - gc v18 implementation using reg dma v1.
- * @ctx: dspp ctx info
- * @cfg: pointer to struct dpu_hw_cp_cfg
- */
-void reg_dmav1_setup_dspp_gcv18(struct dpu_hw_dspp *ctx, void *cfg);
-
-/**
- * reg_dmav1_setup_dspp_igcv31() - igc v31 implementation using reg dma v1.
- * @ctx: dspp ctx info
- * @cfg: pointer to struct dpu_hw_cp_cfg
- */
-void reg_dmav1_setup_dspp_igcv31(struct dpu_hw_dspp *ctx, void *cfg);
-
-/**
- * reg_dmav1_setup_dspp_pccv4() - pcc v4 implementation using reg dma v1.
- * @ctx: dspp ctx info
- * @cfg: pointer to struct dpu_hw_cp_cfg
- */
-void reg_dmav1_setup_dspp_pccv4(struct dpu_hw_dspp *ctx, void *cfg);
-
-/**
- * reg_dmav1_deinit_dspp_ops() - deinitialize the dspp feature op for dpu v4
- * which were initialized.
- * @idx: dspp idx
- */
-int reg_dmav1_deinit_dspp_ops(enum dpu_dspp idx);
-#endif /* _DPU_HW_REG_DMA_V1_COLOR_PROC_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index e02a938..6640906 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -14,7 +14,6 @@
#include "dpu_hw_catalog.h"
#include "dpu_hw_lm.h"
#include "dpu_hw_sspp.h"
-#include "dpu_hw_color_processing.h"
#include "dpu_dbg.h"
#include "dpu_kms.h"

@@ -165,15 +164,6 @@ static inline int _sspp_subblk_offset(struct dpu_hw_pipe *ctx,
case DPU_SSPP_CSC_10BIT:
*idx = sblk->csc_blk.base;
break;
- case DPU_SSPP_HSIC:
- *idx = sblk->hsic_blk.base;
- break;
- case DPU_SSPP_PCC:
- *idx = sblk->pcc_blk.base;
- break;
- case DPU_SSPP_MEMCOLOR:
- *idx = sblk->memcolor_blk.base;
- break;
default:
rc = -EINVAL;
}
@@ -413,64 +403,6 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx,
tot_req_pixels[3]);
}

-static void _dpu_hw_sspp_setup_scaler(struct dpu_hw_pipe *ctx,
- struct dpu_hw_pipe_cfg *sspp,
- struct dpu_hw_pixel_ext *pe,
- void *scaler_cfg)
-{
- struct dpu_hw_blk_reg_map *c;
- int config_h = 0x0;
- int config_v = 0x0;
- u32 idx;
-
- (void)sspp;
- (void)scaler_cfg;
- if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED2, &idx) || !pe)
- return;
-
- c = &ctx->hw;
-
- /* enable scaler(s) if valid filter set */
- if (pe->horz_filter[DPU_SSPP_COMP_0] < DPU_SCALE_FILTER_MAX)
- config_h |= pe->horz_filter[DPU_SSPP_COMP_0] << 8;
- if (pe->horz_filter[DPU_SSPP_COMP_1_2] < DPU_SCALE_FILTER_MAX)
- config_h |= pe->horz_filter[DPU_SSPP_COMP_1_2] << 12;
- if (pe->horz_filter[DPU_SSPP_COMP_3] < DPU_SCALE_FILTER_MAX)
- config_h |= pe->horz_filter[DPU_SSPP_COMP_3] << 16;
-
- if (config_h)
- config_h |= BIT(0);
-
- if (pe->vert_filter[DPU_SSPP_COMP_0] < DPU_SCALE_FILTER_MAX)
- config_v |= pe->vert_filter[DPU_SSPP_COMP_0] << 10;
- if (pe->vert_filter[DPU_SSPP_COMP_1_2] < DPU_SCALE_FILTER_MAX)
- config_v |= pe->vert_filter[DPU_SSPP_COMP_1_2] << 14;
- if (pe->vert_filter[DPU_SSPP_COMP_3] < DPU_SCALE_FILTER_MAX)
- config_v |= pe->vert_filter[DPU_SSPP_COMP_3] << 18;
-
- if (config_v)
- config_v |= BIT(1);
-
- DPU_REG_WRITE(c, SCALE_CONFIG + idx, config_h | config_v);
- DPU_REG_WRITE(c, COMP0_3_INIT_PHASE_X + idx,
- pe->init_phase_x[DPU_SSPP_COMP_0]);
- DPU_REG_WRITE(c, COMP0_3_INIT_PHASE_Y + idx,
- pe->init_phase_y[DPU_SSPP_COMP_0]);
- DPU_REG_WRITE(c, COMP0_3_PHASE_STEP_X + idx,
- pe->phase_step_x[DPU_SSPP_COMP_0]);
- DPU_REG_WRITE(c, COMP0_3_PHASE_STEP_Y + idx,
- pe->phase_step_y[DPU_SSPP_COMP_0]);
-
- DPU_REG_WRITE(c, COMP1_2_INIT_PHASE_X + idx,
- pe->init_phase_x[DPU_SSPP_COMP_1_2]);
- DPU_REG_WRITE(c, COMP1_2_INIT_PHASE_Y + idx,
- pe->init_phase_y[DPU_SSPP_COMP_1_2]);
- DPU_REG_WRITE(c, COMP1_2_PHASE_STEP_X + idx,
- pe->phase_step_x[DPU_SSPP_COMP_1_2]);
- DPU_REG_WRITE(c, COMP1_2_PHASE_STEP_Y + idx,
- pe->phase_step_y[DPU_SSPP_COMP_1_2]);
-}
-
static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx,
struct dpu_hw_pipe_cfg *sspp,
struct dpu_hw_pixel_ext *pe,
@@ -509,7 +441,6 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,
struct dpu_hw_blk_reg_map *c;
u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
- u32 decimation = 0;
u32 idx;

if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !cfg)
@@ -560,13 +491,6 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,
}
}

- /* program scaler, phase registers, if pipes supporting scaling */
- if (ctx->cap->features & DPU_SSPP_SCALER) {
- /* program decimation */
- decimation = ((1 << cfg->horz_decimation) - 1) << 8;
- decimation |= ((1 << cfg->vert_decimation) - 1);
- }
-
/* rectangle register programming */
DPU_REG_WRITE(c, src_size_off + idx, src_size);
DPU_REG_WRITE(c, src_xy_off + idx, src_xy);
@@ -575,52 +499,6 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx,

DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0);
DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1);
- DPU_REG_WRITE(c, SSPP_DECIMATION_CONFIG + idx, decimation);
-}
-
-/**
- * _dpu_hw_sspp_setup_excl_rect() - set exclusion rect configs
- * @ctx: Pointer to pipe context
- * @excl_rect: Exclusion rect configs
- */
-static void _dpu_hw_sspp_setup_excl_rect(struct dpu_hw_pipe *ctx,
- struct dpu_rect *excl_rect,
- enum dpu_sspp_multirect_index rect_index)
-{
- struct dpu_hw_blk_reg_map *c;
- u32 size, xy;
- u32 idx;
- u32 reg_xy, reg_size;
- u32 excl_ctrl, enable_bit;
-
- if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !excl_rect)
- return;
-
- if (rect_index == DPU_SSPP_RECT_0 || rect_index == DPU_SSPP_RECT_SOLO) {
- reg_xy = SSPP_EXCL_REC_XY;
- reg_size = SSPP_EXCL_REC_SIZE;
- enable_bit = BIT(0);
- } else {
- reg_xy = SSPP_EXCL_REC_XY_REC1;
- reg_size = SSPP_EXCL_REC_SIZE_REC1;
- enable_bit = BIT(1);
- }
-
- c = &ctx->hw;
-
- xy = (excl_rect->y << 16) | (excl_rect->x);
- size = (excl_rect->h << 16) | (excl_rect->w);
-
- excl_ctrl = DPU_REG_READ(c, SSPP_EXCL_REC_CTL + idx);
- if (!size) {
- DPU_REG_WRITE(c, SSPP_EXCL_REC_CTL + idx,
- excl_ctrl & ~enable_bit);
- } else {
- DPU_REG_WRITE(c, SSPP_EXCL_REC_CTL + idx,
- excl_ctrl | enable_bit);
- DPU_REG_WRITE(c, reg_size + idx, size);
- DPU_REG_WRITE(c, reg_xy + idx, xy);
- }
}

static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx,
@@ -667,24 +545,6 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
dpu_hw_csc_setup(&ctx->hw, idx, data, csc10);
}

-static void dpu_hw_sspp_setup_sharpening(struct dpu_hw_pipe *ctx,
- struct dpu_hw_sharp_cfg *cfg)
-{
- struct dpu_hw_blk_reg_map *c;
- u32 idx;
-
- if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED2, &idx) || !cfg ||
- !test_bit(DPU_SSPP_SCALER_QSEED2, &ctx->cap->features))
- return;
-
- c = &ctx->hw;
-
- DPU_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx, cfg->strength);
- DPU_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx + 0x4, cfg->edge_thr);
- DPU_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx + 0x8, cfg->smooth_thr);
- DPU_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx + 0xC, cfg->noise_thr);
-}
-
static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum
dpu_sspp_multirect_index rect_index)
{
@@ -754,57 +614,6 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl);
}

-static void dpu_hw_sspp_setup_ts_prefill(struct dpu_hw_pipe *ctx,
- struct dpu_hw_pipe_ts_cfg *cfg,
- enum dpu_sspp_multirect_index index)
-{
- u32 idx;
- u32 ts_offset, ts_prefill_offset;
- u32 ts_count = 0, ts_bytes = 0;
- const struct dpu_sspp_cfg *cap;
-
- if (!ctx || !cfg || !ctx->cap)
- return;
-
- if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
- return;
-
- cap = ctx->cap;
-
- if (index == DPU_SSPP_RECT_0 &&
- test_bit(DPU_SSPP_TS_PREFILL, &cap->features)) {
- ts_offset = SSPP_TRAFFIC_SHAPER;
- ts_prefill_offset = SSPP_TRAFFIC_SHAPER_PREFILL;
- } else if (index == DPU_SSPP_RECT_1 &&
- test_bit(DPU_SSPP_TS_PREFILL_REC1, &cap->features)) {
- ts_offset = SSPP_TRAFFIC_SHAPER_REC1;
- ts_prefill_offset = SSPP_TRAFFIC_SHAPER_REC1_PREFILL;
- } else {
- return;
- }
-
- if (cfg->time) {
- /* this does mult_frac in a 64-bit safe manner */
- u64 rate = TS_CLK * 1000000ULL;
- u32 rem;
- u64 quot = div_u64_rem(rate, cfg->time, &rem);
-
- ts_bytes = (quot * cfg->size) +
- div_u64(rem * cfg->size, cfg->time);
-
- if (ts_bytes > SSPP_TRAFFIC_SHAPER_BPC_MAX)
- ts_bytes = SSPP_TRAFFIC_SHAPER_BPC_MAX;
- }
-
- if (ts_bytes) {
- ts_count = DIV_ROUND_UP_ULL(cfg->size, ts_bytes);
- ts_bytes |= BIT(31) | BIT(27);
- }
-
- DPU_REG_WRITE(&ctx->hw, ts_offset, ts_bytes);
- DPU_REG_WRITE(&ctx->hw, ts_prefill_offset, ts_count);
-}
-
static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
struct dpu_hw_pipe_cdp_cfg *cfg)
{
@@ -840,9 +649,6 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c,
c->ops.setup_pe = dpu_hw_sspp_setup_pe_config;
}

- if (test_bit(DPU_SSPP_EXCL_RECT, &features))
- c->ops.setup_excl_rect = _dpu_hw_sspp_setup_excl_rect;
-
if (test_bit(DPU_SSPP_QOS, &features)) {
c->ops.setup_danger_safe_lut =
dpu_hw_sspp_setup_danger_safe_lut;
@@ -850,18 +656,10 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c,
c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl;
}

- if (test_bit(DPU_SSPP_TS_PREFILL, &features))
- c->ops.setup_ts_prefill = dpu_hw_sspp_setup_ts_prefill;
-
if (test_bit(DPU_SSPP_CSC, &features) ||
test_bit(DPU_SSPP_CSC_10BIT, &features))
c->ops.setup_csc = dpu_hw_sspp_setup_csc;

- if (test_bit(DPU_SSPP_SCALER_QSEED2, &features)) {
- c->ops.setup_sharpening = dpu_hw_sspp_setup_sharpening;
- c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler;
- }
-
if (dpu_hw_sspp_multirect_enabled(c->cap))
c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;

@@ -870,24 +668,6 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c,
c->ops.get_scaler_ver = _dpu_hw_sspp_get_scaler3_ver;
}

- if (test_bit(DPU_SSPP_HSIC, &features)) {
- /* TODO: add version based assignment here as inline or macro */
- if (c->cap->sblk->hsic_blk.version ==
- (DPU_COLOR_PROCESS_VER(0x1, 0x7))) {
- c->ops.setup_pa_hue = dpu_setup_pipe_pa_hue_v1_7;
- c->ops.setup_pa_sat = dpu_setup_pipe_pa_sat_v1_7;
- c->ops.setup_pa_val = dpu_setup_pipe_pa_val_v1_7;
- c->ops.setup_pa_cont = dpu_setup_pipe_pa_cont_v1_7;
- }
- }
-
- if (test_bit(DPU_SSPP_MEMCOLOR, &features)) {
- if (c->cap->sblk->memcolor_blk.version ==
- (DPU_COLOR_PROCESS_VER(0x1, 0x7)))
- c->ops.setup_pa_memcolor =
- dpu_setup_pipe_pa_memcol_v1_7;
- }
-
if (test_bit(DPU_SSPP_CDP, &features))
c->ops.setup_cdp = dpu_hw_sspp_setup_cdp;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index a32ecc6..0bb5ecb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -18,7 +18,6 @@
#include "dpu_hw_util.h"
#include "dpu_hw_blk.h"
#include "dpu_formats.h"
-#include "dpu_color_processing.h"

struct dpu_hw_pipe;

@@ -160,12 +159,6 @@ struct dpu_hw_pixel_ext {
* @src_rect: src ROI, caller takes into account the different operations
* such as decimation, flip etc to program this field
* @dest_rect: destination ROI.
- * @ horz_decimation : horizontal decimation factor( 0, 2, 4, 8, 16)
- * @ vert_decimation : vertical decimation factor( 0, 2, 4, 8, 16)
- * 2: Read 1 line/pixel drop 1 line/pixel
- * 4: Read 1 line/pixel drop 3 lines/pixels
- * 8: Read 1 line/pixel drop 7 lines/pixels
- * 16: Read 1 line/pixel drop 15 line/pixels
* @index: index of the rectangle of SSPP
* @mode: parallel or time multiplex multirect mode
*/
@@ -173,8 +166,6 @@ struct dpu_hw_pipe_cfg {
struct dpu_hw_fmt_layout layout;
struct dpu_rect src_rect;
struct dpu_rect dst_rect;
- u8 horz_decimation;
- u8 vert_decimation;
enum dpu_sspp_multirect_index index;
enum dpu_sspp_multirect_mode mode;
};
@@ -269,16 +260,6 @@ struct dpu_hw_sspp_ops {
struct dpu_hw_pixel_ext *pe_ext);

/**
- * setup_excl_rect - setup pipe exclusion rectangle
- * @ctx: Pointer to pipe context
- * @excl_rect: Pointer to exclclusion rect structure
- * @index: rectangle index in multirect
- */
- void (*setup_excl_rect)(struct dpu_hw_pipe *ctx,
- struct dpu_rect *excl_rect,
- enum dpu_sspp_multirect_index index);
-
- /**
* setup_sourceaddress - setup pipe source addresses
* @ctx: Pointer to pipe context
* @cfg: Pointer to pipe config structure
@@ -324,50 +305,6 @@ struct dpu_hw_sspp_ops {
void (*setup_sharpening)(struct dpu_hw_pipe *ctx,
struct dpu_hw_sharp_cfg *cfg);

-
- /**
- * setup_pa_hue(): Setup source hue adjustment
- * @ctx: Pointer to pipe context
- * @cfg: Pointer to hue data
- */
- void (*setup_pa_hue)(struct dpu_hw_pipe *ctx, void *cfg);
-
- /**
- * setup_pa_sat(): Setup source saturation adjustment
- * @ctx: Pointer to pipe context
- * @cfg: Pointer to saturation data
- */
- void (*setup_pa_sat)(struct dpu_hw_pipe *ctx, void *cfg);
-
- /**
- * setup_pa_val(): Setup source value adjustment
- * @ctx: Pointer to pipe context
- * @cfg: Pointer to value data
- */
- void (*setup_pa_val)(struct dpu_hw_pipe *ctx, void *cfg);
-
- /**
- * setup_pa_cont(): Setup source contrast adjustment
- * @ctx: Pointer to pipe context
- * @cfg: Pointer contrast data
- */
- void (*setup_pa_cont)(struct dpu_hw_pipe *ctx, void *cfg);
-
- /**
- * setup_pa_memcolor - setup source color processing
- * @ctx: Pointer to pipe context
- * @type: Memcolor type (Skin, sky or foliage)
- * @cfg: Pointer to memory color config data
- */
- void (*setup_pa_memcolor)(struct dpu_hw_pipe *ctx,
- enum dpu_memcolor_type type, void *cfg);
-
- /**
- * setup_igc - setup inverse gamma correction
- * @ctx: Pointer to pipe context
- */
- void (*setup_igc)(struct dpu_hw_pipe *ctx);
-
/**
* setup_danger_safe_lut - setup danger safe LUTs
* @ctx: Pointer to pipe context
@@ -422,16 +359,6 @@ struct dpu_hw_sspp_ops {
u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx);

/**
- * setup_ts_prefill - setup prefill traffic shaper
- * @ctx: Pointer to pipe context
- * @cfg: Pointer to traffic shaper configuration
- * @index: rectangle index in multirect
- */
- void (*setup_ts_prefill)(struct dpu_hw_pipe *ctx,
- struct dpu_hw_pipe_ts_cfg *cfg,
- enum dpu_sspp_multirect_index index);
-
- /**
* setup_cdp - setup client driven prefetch
* @ctx: Pointer to pipe context
* @cfg: Pointer to cdp configuration
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index 019a8fa..1ba571e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -11,7 +11,6 @@
*/
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__

-#include <uapi/drm/dpu_drm.h>
#include "msm_drv.h"
#include "dpu_kms.h"
#include "dpu_hw_mdss.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index d92cafb..42f1b22 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -158,6 +158,162 @@ struct dpu_hw_scaler3_lut_cfg {
size_t sep_len;
};

+/**
+ * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
+ * @num_ext_pxls_lr: Number of total horizontal pixels
+ * @num_ext_pxls_tb: Number of total vertical lines
+ * @left_ftch: Number of extra pixels to overfetch from left
+ * @right_ftch: Number of extra pixels to overfetch from right
+ * @top_ftch: Number of extra lines to overfetch from top
+ * @btm_ftch: Number of extra lines to overfetch from bottom
+ * @left_rpt: Number of extra pixels to repeat from left
+ * @right_rpt: Number of extra pixels to repeat from right
+ * @top_rpt: Number of extra lines to repeat from top
+ * @btm_rpt: Number of extra lines to repeat from bottom
+ */
+struct dpu_drm_pix_ext_v1 {
+ /*
+ * Number of pixels ext in left, right, top and bottom direction
+ * for all color components.
+ */
+ int32_t num_ext_pxls_lr[DPU_MAX_PLANES];
+ int32_t num_ext_pxls_tb[DPU_MAX_PLANES];
+
+ /*
+ * Number of pixels needs to be overfetched in left, right, top
+ * and bottom directions from source image for scaling.
+ */
+ int32_t left_ftch[DPU_MAX_PLANES];
+ int32_t right_ftch[DPU_MAX_PLANES];
+ int32_t top_ftch[DPU_MAX_PLANES];
+ int32_t btm_ftch[DPU_MAX_PLANES];
+ /*
+ * Number of pixels needs to be repeated in left, right, top and
+ * bottom directions for scaling.
+ */
+ int32_t left_rpt[DPU_MAX_PLANES];
+ int32_t right_rpt[DPU_MAX_PLANES];
+ int32_t top_rpt[DPU_MAX_PLANES];
+ int32_t btm_rpt[DPU_MAX_PLANES];
+
+};
+
+/**
+ * struct dpu_drm_de_v1 - version 1 of detail enhancer structure
+ * @enable: Enables/disables detail enhancer
+ * @sharpen_level1: Sharpening strength for noise
+ * @sharpen_level2: Sharpening strength for context
+ * @clip: Clip coefficient
+ * @limit: Detail enhancer limit factor
+ * @thr_quiet: Quite zone threshold
+ * @thr_dieout: Die-out zone threshold
+ * @thr_low: Linear zone left threshold
+ * @thr_high: Linear zone right threshold
+ * @prec_shift: Detail enhancer precision
+ * @adjust_a: Mapping curves A coefficients
+ * @adjust_b: Mapping curves B coefficients
+ * @adjust_c: Mapping curves C coefficients
+ */
+struct dpu_drm_de_v1 {
+ uint32_t enable;
+ int16_t sharpen_level1;
+ int16_t sharpen_level2;
+ uint16_t clip;
+ uint16_t limit;
+ uint16_t thr_quiet;
+ uint16_t thr_dieout;
+ uint16_t thr_low;
+ uint16_t thr_high;
+ uint16_t prec_shift;
+ int16_t adjust_a[DPU_MAX_DE_CURVES];
+ int16_t adjust_b[DPU_MAX_DE_CURVES];
+ int16_t adjust_c[DPU_MAX_DE_CURVES];
+};
+
+/**
+ * struct dpu_drm_scaler_v2 - version 2 of struct dpu_drm_scaler
+ * @enable: Scaler enable
+ * @dir_en: Detail enhancer enable
+ * @pe: Pixel extension settings
+ * @horz_decimate: Horizontal decimation factor
+ * @vert_decimate: Vertical decimation factor
+ * @init_phase_x: Initial scaler phase values for x
+ * @phase_step_x: Phase step values for x
+ * @init_phase_y: Initial scaler phase values for y
+ * @phase_step_y: Phase step values for y
+ * @preload_x: Horizontal preload value
+ * @preload_y: Vertical preload value
+ * @src_width: Source width
+ * @src_height: Source height
+ * @dst_width: Destination width
+ * @dst_height: Destination height
+ * @y_rgb_filter_cfg: Y/RGB plane filter configuration
+ * @uv_filter_cfg: UV plane filter configuration
+ * @alpha_filter_cfg: Alpha filter configuration
+ * @blend_cfg: Selection of blend coefficients
+ * @lut_flag: LUT configuration flags
+ * @dir_lut_idx: 2d 4x4 LUT index
+ * @y_rgb_cir_lut_idx: Y/RGB circular LUT index
+ * @uv_cir_lut_idx: UV circular LUT index
+ * @y_rgb_sep_lut_idx: Y/RGB separable LUT index
+ * @uv_sep_lut_idx: UV separable LUT index
+ * @de: Detail enhancer settings
+ */
+struct dpu_drm_scaler_v2 {
+ /*
+ * General definitions
+ */
+ uint32_t enable;
+ uint32_t dir_en;
+
+ /*
+ * Pix ext settings
+ */
+ struct dpu_drm_pix_ext_v1 pe;
+
+ /*
+ * Decimation settings
+ */
+ uint32_t horz_decimate;
+ uint32_t vert_decimate;
+
+ /*
+ * Phase settings
+ */
+ int32_t init_phase_x[DPU_MAX_PLANES];
+ int32_t phase_step_x[DPU_MAX_PLANES];
+ int32_t init_phase_y[DPU_MAX_PLANES];
+ int32_t phase_step_y[DPU_MAX_PLANES];
+
+ uint32_t preload_x[DPU_MAX_PLANES];
+ uint32_t preload_y[DPU_MAX_PLANES];
+ uint32_t src_width[DPU_MAX_PLANES];
+ uint32_t src_height[DPU_MAX_PLANES];
+
+ uint32_t dst_width;
+ uint32_t dst_height;
+
+ uint32_t y_rgb_filter_cfg;
+ uint32_t uv_filter_cfg;
+ uint32_t alpha_filter_cfg;
+ uint32_t blend_cfg;
+
+ uint32_t lut_flag;
+ uint32_t dir_lut_idx;
+
+ /* for Y(RGB) and UV planes*/
+ uint32_t y_rgb_cir_lut_idx;
+ uint32_t uv_cir_lut_idx;
+ uint32_t y_rgb_sep_lut_idx;
+ uint32_t uv_sep_lut_idx;
+
+ /*
+ * Detail enhancer settings
+ */
+ struct dpu_drm_de_v1 de;
+};
+
+
u32 *dpu_hw_util_get_log_mask_ptr(void);

void dpu_reg_write(struct dpu_hw_blk_reg_map *c,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index db66566..fe614c0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -35,7 +35,6 @@
#include "dpu_encoder.h"
#include "dpu_plane.h"
#include "dpu_crtc.h"
-#include "dpu_reg_dma.h"

#define CREATE_TRACE_POINTS
#include "dpu_trace.h"
@@ -1064,8 +1063,6 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
if (dpu_kms->mmio)
msm_iounmap(dpu_kms->pdev, dpu_kms->mmio);
dpu_kms->mmio = NULL;
-
- dpu_reg_dma_deinit();
}

static void dpu_kms_destroy(struct msm_kms *kms)
@@ -1511,14 +1508,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
goto power_error;
}

- /* Initialize reg dma block which is a singleton */
- rc = dpu_reg_dma_init(dpu_kms->reg_dma, dpu_kms->catalog,
- dpu_kms->dev);
- if (rc) {
- DPU_ERROR("failed: reg dma init failed\n");
- goto power_error;
- }
-
rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio,
dpu_kms->dev);
if (rc) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 3b2c609..e81cb1f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -20,9 +20,6 @@

#include <linux/debugfs.h>
#include <linux/dma-buf.h>
-#include <uapi/drm/dpu_drm.h>
-#include <uapi/drm/msm_drm_pp.h>
-
#include "msm_prop.h"
#include "msm_drv.h"

@@ -34,7 +31,6 @@
#include "dpu_crtc.h"
#include "dpu_vbif.h"
#include "dpu_plane.h"
-#include "dpu_color_processing.h"

static bool suspend_blank = true;
module_param(suspend_blank, bool, 0400);
@@ -93,8 +89,6 @@ enum dpu_plane_qos {
/*
* struct dpu_plane - local dpu plane structure
* @aspace: address space pointer
- * @csc_cfg: Decoded user configuration for csc
- * @csc_usr_ptr: Points to csc_cfg if valid user config available
* @csc_ptr: Points to dpu_csc_cfg structure to use for current
* @mplane_list: List of multirect planes of the same pipe
* @catalog: Points to dpu catalog structure
@@ -112,7 +106,6 @@ struct dpu_plane {

struct dpu_hw_pipe *pipe_hw;
struct dpu_hw_pipe_cfg pipe_cfg;
- struct dpu_hw_sharp_cfg sharp_cfg;
struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
uint32_t color_fill;
bool is_error;
@@ -120,16 +113,11 @@ struct dpu_plane {
bool is_virtual;
struct list_head mplane_list;
struct dpu_mdss_cfg *catalog;
- bool revalidate;

- struct dpu_csc_cfg csc_cfg;
- struct dpu_csc_cfg *csc_usr_ptr;
struct dpu_csc_cfg *csc_ptr;

const struct dpu_sspp_sub_blks *pipe_sblk;
-
char pipe_name[DPU_NAME_SIZE];
-
struct msm_property_info property_info;
struct msm_property_data property_data[PLANE_PROP_COUNT];
struct drm_property_blob *blob_info;
@@ -442,17 +430,6 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
&pdpu->pipe_qos_cfg);
}

-void dpu_plane_set_revalidate(struct drm_plane *plane, bool enable)
-{
- struct dpu_plane *pdpu;
-
- if (!plane)
- return;
-
- pdpu = to_dpu_plane(plane);
- pdpu->revalidate = enable;
-}
-
int dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
{
struct dpu_plane *pdpu;
@@ -576,55 +553,6 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
}

/**
- * _dpu_plane_set_ts_prefill - set prefill with traffic shaper
- * @plane: Pointer to drm plane
- * @pstate: Pointer to dpu plane state
- */
-static void _dpu_plane_set_ts_prefill(struct drm_plane *plane,
- struct dpu_plane_state *pstate)
-{
- struct dpu_plane *pdpu;
- struct dpu_hw_pipe_ts_cfg cfg;
- struct msm_drm_private *priv;
- struct dpu_kms *dpu_kms;
-
- if (!plane || !plane->dev) {
- DPU_ERROR("invalid arguments");
- return;
- }
-
- priv = plane->dev->dev_private;
- if (!priv || !priv->kms) {
- DPU_ERROR("invalid KMS reference\n");
- return;
- }
-
- dpu_kms = to_dpu_kms(priv->kms);
- pdpu = to_dpu_plane(plane);
- if (!pdpu->pipe_hw) {
- DPU_ERROR("invalid pipe reference\n");
- return;
- }
-
- if (!pdpu->pipe_hw || !pdpu->pipe_hw->ops.setup_ts_prefill)
- return;
-
- _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_VBLANK_AMORTIZE);
-
- memset(&cfg, 0, sizeof(cfg));
- cfg.size = dpu_plane_get_property(pstate,
- PLANE_PROP_PREFILL_SIZE);
- cfg.time = dpu_plane_get_property(pstate,
- PLANE_PROP_PREFILL_TIME);
-
- DPU_DEBUG("plane%d size:%llu time:%llu\n",
- plane->base.id, cfg.size, cfg.time);
- DPU_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
- pdpu->pipe_hw->ops.setup_ts_prefill(pdpu->pipe_hw, &cfg,
- pstate->multirect_index);
-}
-
-/**
* _dpu_plane_get_aspace: gets the address space
*/
static int _dpu_plane_get_aspace(
@@ -701,36 +629,6 @@ static inline void _dpu_plane_set_scanout(struct drm_plane *plane,
}
}

-static int _dpu_plane_setup_scaler3_lut(struct dpu_plane *pdpu,
- struct dpu_plane_state *pstate)
-{
- struct dpu_hw_scaler3_cfg *cfg;
- int ret = 0;
-
- if (!pdpu || !pstate) {
- DPU_ERROR("invalid args\n");
- return -EINVAL;
- }
-
- cfg = &pstate->scaler3_cfg;
-
- cfg->dir_lut = msm_property_get_blob(
- &pdpu->property_info,
- &pstate->property_state, &cfg->dir_len,
- PLANE_PROP_SCALER_LUT_ED);
- cfg->cir_lut = msm_property_get_blob(
- &pdpu->property_info,
- &pstate->property_state, &cfg->cir_len,
- PLANE_PROP_SCALER_LUT_CIR);
- cfg->sep_lut = msm_property_get_blob(
- &pdpu->property_info,
- &pstate->property_state, &cfg->sep_len,
- PLANE_PROP_SCALER_LUT_SEP);
- if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
- ret = -ENODATA;
- return ret;
-}
-
static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
struct dpu_plane_state *pstate,
uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
@@ -738,7 +636,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
const struct dpu_format *fmt,
uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
{
- uint32_t decimated, i;
+ uint32_t i;

if (!pdpu || !pstate || !scale_cfg || !fmt || !chroma_subsmpl_h ||
!chroma_subsmpl_v) {
@@ -752,14 +650,10 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
memset(scale_cfg, 0, sizeof(*scale_cfg));
memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext));

- decimated = DECIMATED_DIMENSION(src_w,
- pdpu->pipe_cfg.horz_decimation);
scale_cfg->phase_step_x[DPU_SSPP_COMP_0] =
- mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
- decimated = DECIMATED_DIMENSION(src_h,
- pdpu->pipe_cfg.vert_decimation);
+ mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w);
scale_cfg->phase_step_y[DPU_SSPP_COMP_0] =
- mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
+ mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h);

scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] =
@@ -778,10 +672,8 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
scale_cfg->phase_step_y[DPU_SSPP_COMP_0];

for (i = 0; i < DPU_MAX_PLANES; i++) {
- scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
- pdpu->pipe_cfg.horz_decimation);
- scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h,
- pdpu->pipe_cfg.vert_decimation);
+ scale_cfg->src_width[i] = src_w;
+ scale_cfg->src_height[i] = src_h;
if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) {
scale_cfg->src_width[i] /= chroma_subsmpl_h;
scale_cfg->src_height[i] /= chroma_subsmpl_v;
@@ -807,154 +699,6 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
scale_cfg->enable = 1;
}

-/**
- * _dpu_plane_setup_scaler2 - determine default scaler phase steps/filter type
- * @pdpu: Pointer to DPU plane object
- * @src: Source size
- * @dst: Destination size
- * @phase_steps: Pointer to output array for phase steps
- * @filter: Pointer to output array for filter type
- * @fmt: Pointer to format definition
- * @chroma_subsampling: Subsampling amount for chroma channel
- *
- * Returns: 0 on success
- */
-static int _dpu_plane_setup_scaler2(struct dpu_plane *pdpu,
- uint32_t src, uint32_t dst, uint32_t *phase_steps,
- enum dpu_hw_filter *filter, const struct dpu_format *fmt,
- uint32_t chroma_subsampling)
-{
- if (!pdpu || !phase_steps || !filter || !fmt) {
- DPU_ERROR(
- "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
- pdpu != 0, phase_steps != 0, filter != 0, fmt != 0);
- return -EINVAL;
- }
-
- /* calculate phase steps, leave init phase as zero */
- phase_steps[DPU_SSPP_COMP_0] =
- mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
- phase_steps[DPU_SSPP_COMP_1_2] =
- phase_steps[DPU_SSPP_COMP_0] / chroma_subsampling;
- phase_steps[DPU_SSPP_COMP_2] = phase_steps[DPU_SSPP_COMP_1_2];
- phase_steps[DPU_SSPP_COMP_3] = phase_steps[DPU_SSPP_COMP_0];
-
- /* calculate scaler config, if necessary */
- if (DPU_FORMAT_IS_YUV(fmt) || src != dst) {
- filter[DPU_SSPP_COMP_3] =
- (src <= dst) ? DPU_SCALE_FILTER_BIL :
- DPU_SCALE_FILTER_PCMN;
-
- if (DPU_FORMAT_IS_YUV(fmt)) {
- filter[DPU_SSPP_COMP_0] = DPU_SCALE_FILTER_CA;
- filter[DPU_SSPP_COMP_1_2] = filter[DPU_SSPP_COMP_3];
- } else {
- filter[DPU_SSPP_COMP_0] = filter[DPU_SSPP_COMP_3];
- filter[DPU_SSPP_COMP_1_2] =
- DPU_SCALE_FILTER_NEAREST;
- }
- } else {
- /* disable scaler */
- filter[DPU_SSPP_COMP_0] = DPU_SCALE_FILTER_MAX;
- filter[DPU_SSPP_COMP_1_2] = DPU_SCALE_FILTER_MAX;
- filter[DPU_SSPP_COMP_3] = DPU_SCALE_FILTER_MAX;
- }
- return 0;
-}
-
-/**
- * _dpu_plane_setup_pixel_ext - determine default pixel extension values
- * @pdpu: Pointer to DPU plane object
- * @src: Source size
- * @dst: Destination size
- * @decimated_src: Source size after decimation, if any
- * @phase_steps: Pointer to output array for phase steps
- * @out_src: Output array for pixel extension values
- * @out_edge1: Output array for pixel extension first edge
- * @out_edge2: Output array for pixel extension second edge
- * @filter: Pointer to array for filter type
- * @fmt: Pointer to format definition
- * @chroma_subsampling: Subsampling amount for chroma channel
- * @post_compare: Whether to chroma subsampled source size for comparisions
- */
-static void _dpu_plane_setup_pixel_ext(struct dpu_plane *pdpu,
- uint32_t src, uint32_t dst, uint32_t decimated_src,
- uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
- int *out_edge2, enum dpu_hw_filter *filter,
- const struct dpu_format *fmt, uint32_t chroma_subsampling,
- bool post_compare)
-{
- int64_t edge1, edge2, caf;
- uint32_t src_work;
- int i, tmp;
-
- if (pdpu && phase_steps && out_src && out_edge1 &&
- out_edge2 && filter && fmt) {
- /* handle CAF for YUV formats */
- if (DPU_FORMAT_IS_YUV(fmt) && *filter == DPU_SCALE_FILTER_CA)
- caf = PHASE_STEP_UNIT_SCALE;
- else
- caf = 0;
-
- for (i = 0; i < DPU_MAX_PLANES; i++) {
- src_work = decimated_src;
- if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2)
- src_work /= chroma_subsampling;
- if (post_compare)
- src = src_work;
- if (!DPU_FORMAT_IS_YUV(fmt) && (src == dst)) {
- /* unity */
- edge1 = 0;
- edge2 = 0;
- } else if (dst >= src) {
- /* upscale */
- edge1 = (1 << PHASE_RESIDUAL);
- edge1 -= caf;
- edge2 = (1 << PHASE_RESIDUAL);
- edge2 += (dst - 1) * *(phase_steps + i);
- edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
- edge2 += caf;
- edge2 = -(edge2);
- } else {
- /* downscale */
- edge1 = 0;
- edge2 = (dst - 1) * *(phase_steps + i);
- edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
- edge2 += *(phase_steps + i);
- edge2 = -(edge2);
- }
-
- /* only enable CAF for luma plane */
- caf = 0;
-
- /* populate output arrays */
- *(out_src + i) = src_work;
-
- /* edge updates taken from __pxl_extn_helper */
- if (edge1 >= 0) {
- tmp = (uint32_t)edge1;
- tmp >>= PHASE_STEP_SHIFT;
- *(out_edge1 + i) = -tmp;
- } else {
- tmp = (uint32_t)(-edge1);
- *(out_edge1 + i) =
- (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
- PHASE_STEP_SHIFT;
- }
- if (edge2 >= 0) {
- tmp = (uint32_t)edge2;
- tmp >>= PHASE_STEP_SHIFT;
- *(out_edge2 + i) = -tmp;
- } else {
- tmp = (uint32_t)(-edge2);
- *(out_edge2 + i) =
- (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
- PHASE_STEP_SHIFT;
- }
- }
- }
-}
-
static inline void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
{
static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {
@@ -991,10 +735,7 @@ static inline void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
return;
}

- /* revert to kernel default if override not available */
- if (pdpu->csc_usr_ptr)
- pdpu->csc_ptr = pdpu->csc_usr_ptr;
- else if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features)
+ if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features)
pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L;
else
pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L;
@@ -1005,60 +746,6 @@ static inline void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
pdpu->csc_ptr->csc_mv[2]);
}

-static void dpu_color_process_plane_setup(struct drm_plane *plane)
-{
- struct dpu_plane *pdpu;
- struct dpu_plane_state *pstate;
- uint32_t hue, saturation, value, contrast;
- struct drm_msm_memcol *memcol = NULL;
- size_t memcol_sz = 0;
-
- pdpu = to_dpu_plane(plane);
- pstate = to_dpu_plane_state(plane->state);
-
- hue = (uint32_t) dpu_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
- if (pdpu->pipe_hw->ops.setup_pa_hue)
- pdpu->pipe_hw->ops.setup_pa_hue(pdpu->pipe_hw, &hue);
- saturation = (uint32_t) dpu_plane_get_property(pstate,
- PLANE_PROP_SATURATION_ADJUST);
- if (pdpu->pipe_hw->ops.setup_pa_sat)
- pdpu->pipe_hw->ops.setup_pa_sat(pdpu->pipe_hw, &saturation);
- value = (uint32_t) dpu_plane_get_property(pstate,
- PLANE_PROP_VALUE_ADJUST);
- if (pdpu->pipe_hw->ops.setup_pa_val)
- pdpu->pipe_hw->ops.setup_pa_val(pdpu->pipe_hw, &value);
- contrast = (uint32_t) dpu_plane_get_property(pstate,
- PLANE_PROP_CONTRAST_ADJUST);
- if (pdpu->pipe_hw->ops.setup_pa_cont)
- pdpu->pipe_hw->ops.setup_pa_cont(pdpu->pipe_hw, &contrast);
-
- if (pdpu->pipe_hw->ops.setup_pa_memcolor) {
- /* Skin memory color setup */
- memcol = msm_property_get_blob(&pdpu->property_info,
- &pstate->property_state,
- &memcol_sz,
- PLANE_PROP_SKIN_COLOR);
- pdpu->pipe_hw->ops.setup_pa_memcolor(pdpu->pipe_hw,
- MEMCOLOR_SKIN, memcol);
-
- /* Sky memory color setup */
- memcol = msm_property_get_blob(&pdpu->property_info,
- &pstate->property_state,
- &memcol_sz,
- PLANE_PROP_SKY_COLOR);
- pdpu->pipe_hw->ops.setup_pa_memcolor(pdpu->pipe_hw,
- MEMCOLOR_SKY, memcol);
-
- /* Foliage memory color setup */
- memcol = msm_property_get_blob(&pdpu->property_info,
- &pstate->property_state,
- &memcol_sz,
- PLANE_PROP_FOLIAGE_COLOR);
- pdpu->pipe_hw->ops.setup_pa_memcolor(pdpu->pipe_hw,
- MEMCOLOR_FOLIAGE, memcol);
- }
-}
-
static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
struct dpu_plane_state *pstate,
const struct dpu_format *fmt, bool color_fill)
@@ -1074,99 +761,20 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,

pe = &pstate->pixel_ext;

- pdpu->pipe_cfg.horz_decimation =
- dpu_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
- pdpu->pipe_cfg.vert_decimation =
- dpu_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
-
/* don't chroma subsample if decimating */
- chroma_subsmpl_h = pdpu->pipe_cfg.horz_decimation ? 1 :
+ chroma_subsmpl_h =
drm_format_horz_chroma_subsampling(fmt->base.pixel_format);
- chroma_subsmpl_v = pdpu->pipe_cfg.vert_decimation ? 1 :
+ chroma_subsmpl_v =
drm_format_vert_chroma_subsampling(fmt->base.pixel_format);

- /* update scaler */
- if (pdpu->features & BIT(DPU_SSPP_SCALER_QSEED3)) {
- int rc;
-
- if (!color_fill && !pdpu->debugfs_default_scale)
- rc = _dpu_plane_setup_scaler3_lut(pdpu, pstate);
- else
- rc = -EINVAL;
- if (rc || pstate->scaler_check_state !=
- DPU_PLANE_SCLCHECK_SCALER_V2) {
- /* calculate default config for QSEED3 */
- _dpu_plane_setup_scaler3(pdpu, pstate,
- pdpu->pipe_cfg.src_rect.w,
- pdpu->pipe_cfg.src_rect.h,
- pdpu->pipe_cfg.dst_rect.w,
- pdpu->pipe_cfg.dst_rect.h,
- &pstate->scaler3_cfg, fmt,
- chroma_subsmpl_h, chroma_subsmpl_v);
- }
- } else if (pstate->scaler_check_state != DPU_PLANE_SCLCHECK_SCALER_V1 ||
- color_fill || pdpu->debugfs_default_scale) {
- uint32_t deci_dim, i;
-
- /* calculate default configuration for QSEED2 */
- memset(pe, 0, sizeof(struct dpu_hw_pixel_ext));
-
- DPU_DEBUG_PLANE(pdpu, "default config\n");
- deci_dim = DECIMATED_DIMENSION(pdpu->pipe_cfg.src_rect.w,
- pdpu->pipe_cfg.horz_decimation);
- _dpu_plane_setup_scaler2(pdpu,
- deci_dim,
- pdpu->pipe_cfg.dst_rect.w,
- pe->phase_step_x,
- pe->horz_filter, fmt, chroma_subsmpl_h);
-
- if (DPU_FORMAT_IS_YUV(fmt))
- deci_dim &= ~0x1;
- _dpu_plane_setup_pixel_ext(pdpu, pdpu->pipe_cfg.src_rect.w,
- pdpu->pipe_cfg.dst_rect.w, deci_dim,
- pe->phase_step_x,
- pe->roi_w,
- pe->num_ext_pxls_left,
- pe->num_ext_pxls_right, pe->horz_filter, fmt,
- chroma_subsmpl_h, 0);
-
- deci_dim = DECIMATED_DIMENSION(pdpu->pipe_cfg.src_rect.h,
- pdpu->pipe_cfg.vert_decimation);
- _dpu_plane_setup_scaler2(pdpu,
- deci_dim,
- pdpu->pipe_cfg.dst_rect.h,
- pe->phase_step_y,
- pe->vert_filter, fmt, chroma_subsmpl_v);
- _dpu_plane_setup_pixel_ext(pdpu, pdpu->pipe_cfg.src_rect.h,
- pdpu->pipe_cfg.dst_rect.h, deci_dim,
- pe->phase_step_y,
- pe->roi_h,
- pe->num_ext_pxls_top,
- pe->num_ext_pxls_btm, pe->vert_filter, fmt,
- chroma_subsmpl_v, 1);
-
- for (i = 0; i < DPU_MAX_PLANES; i++) {
- if (pe->num_ext_pxls_left[i] >= 0)
- pe->left_rpt[i] = pe->num_ext_pxls_left[i];
- else
- pe->left_ftch[i] = pe->num_ext_pxls_left[i];
-
- if (pe->num_ext_pxls_right[i] >= 0)
- pe->right_rpt[i] = pe->num_ext_pxls_right[i];
- else
- pe->right_ftch[i] = pe->num_ext_pxls_right[i];
-
- if (pe->num_ext_pxls_top[i] >= 0)
- pe->top_rpt[i] = pe->num_ext_pxls_top[i];
- else
- pe->top_ftch[i] = pe->num_ext_pxls_top[i];
-
- if (pe->num_ext_pxls_btm[i] >= 0)
- pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
- else
- pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
- }
- }
+ /* update scaler. calculate default config for QSEED3 */
+ _dpu_plane_setup_scaler3(pdpu, pstate,
+ pdpu->pipe_cfg.src_rect.w,
+ pdpu->pipe_cfg.src_rect.h,
+ pdpu->pipe_cfg.dst_rect.w,
+ pdpu->pipe_cfg.dst_rect.h,
+ &pstate->scaler3_cfg, fmt,
+ chroma_subsmpl_h, chroma_subsmpl_v);
}

/**
@@ -1463,189 +1071,6 @@ static void dpu_plane_cleanup_fb(struct drm_plane *plane,
msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
}

-static void _dpu_plane_sspp_atomic_check_mode_changed(struct dpu_plane *pdpu,
- struct drm_plane_state *state,
- struct drm_plane_state *old_state)
-{
- struct dpu_plane_state *pstate = to_dpu_plane_state(state);
- struct dpu_plane_state *old_pstate = to_dpu_plane_state(old_state);
- struct drm_framebuffer *fb, *old_fb;
-
- /* no need to check it again */
- if (pstate->dirty == DPU_PLANE_DIRTY_ALL)
- return;
-
- if (!dpu_plane_enabled(state) || !dpu_plane_enabled(old_state)
- || pdpu->is_error) {
- DPU_DEBUG_PLANE(pdpu,
- "enabling/disabling full modeset required\n");
- pstate->dirty |= DPU_PLANE_DIRTY_ALL;
- } else if (to_dpu_plane_state(old_state)->pending) {
- DPU_DEBUG_PLANE(pdpu, "still pending\n");
- pstate->dirty |= DPU_PLANE_DIRTY_ALL;
- } else if (pstate->multirect_index != old_pstate->multirect_index ||
- pstate->multirect_mode != old_pstate->multirect_mode) {
- DPU_DEBUG_PLANE(pdpu, "multirect config updated\n");
- pstate->dirty |= DPU_PLANE_DIRTY_ALL;
- } else if (state->crtc_w != old_state->crtc_w ||
- state->crtc_h != old_state->crtc_h ||
- state->crtc_x != old_state->crtc_x ||
- state->crtc_y != old_state->crtc_y) {
- DPU_DEBUG_PLANE(pdpu, "crtc rect updated\n");
- pstate->dirty |= DPU_PLANE_DIRTY_RECTS;
- } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
- pstate->excl_rect.h != old_pstate->excl_rect.h ||
- pstate->excl_rect.x != old_pstate->excl_rect.x ||
- pstate->excl_rect.y != old_pstate->excl_rect.y) {
- DPU_DEBUG_PLANE(pdpu, "excl_rect updated\n");
- pstate->dirty |= DPU_PLANE_DIRTY_RECTS;
- }
-
- fb = state->fb;
- old_fb = old_state->fb;
-
- if (!fb || !old_fb) {
- DPU_DEBUG_PLANE(pdpu, "can't compare fb handles\n");
- } else if (fb->format->format != old_fb->format->format) {
- DPU_DEBUG_PLANE(pdpu, "format change\n");
- pstate->dirty |= DPU_PLANE_DIRTY_FORMAT | DPU_PLANE_DIRTY_RECTS;
- } else {
- uint64_t new_mod = fb->modifier;
- uint64_t old_mod = old_fb->modifier;
- uint32_t *new_pitches = fb->pitches;
- uint32_t *old_pitches = old_fb->pitches;
- uint32_t *new_offset = fb->offsets;
- uint32_t *old_offset = old_fb->offsets;
- int i;
-
- if (new_mod != old_mod) {
- DPU_DEBUG_PLANE(pdpu,
- "format modifiers change\"\
- new_mode:%llu old_mode:%llu\n",
- new_mod, old_mod);
- pstate->dirty |= DPU_PLANE_DIRTY_FORMAT |
- DPU_PLANE_DIRTY_RECTS;
- }
-
- for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
- if (new_pitches[i] != old_pitches[i]) {
- DPU_DEBUG_PLANE(pdpu,
- "pitches change plane:%d\"\
- old_pitches:%u new_pitches:%u\n",
- i, old_pitches[i], new_pitches[i]);
- pstate->dirty |= DPU_PLANE_DIRTY_RECTS;
- break;
- }
- }
- for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
- if (new_offset[i] != old_offset[i]) {
- DPU_DEBUG_PLANE(pdpu,
- "offset change plane:%d\"\
- old_offset:%u new_offset:%u\n",
- i, old_offset[i], new_offset[i]);
- pstate->dirty |= DPU_PLANE_DIRTY_FORMAT |
- DPU_PLANE_DIRTY_RECTS;
- break;
- }
- }
- }
-}
-
-static int _dpu_plane_validate_scaler_v2(struct dpu_plane *pdpu,
- struct dpu_plane_state *pstate,
- const struct dpu_format *fmt,
- uint32_t img_w, uint32_t img_h,
- uint32_t src_w, uint32_t src_h,
- uint32_t deci_w, uint32_t deci_h)
-{
- int i;
-
- if (!pdpu || !pstate || !fmt) {
- DPU_ERROR_PLANE(pdpu, "invalid arguments\n");
- return -EINVAL;
- }
-
- /* don't run checks unless scaler data was changed */
- if (pstate->scaler_check_state != DPU_PLANE_SCLCHECK_SCALER_V2_CHECK)
- return 0;
-
- pstate->scaler_check_state = DPU_PLANE_SCLCHECK_INVALID;
-
- for (i = 0; i < DPU_MAX_PLANES; i++) {
- uint32_t hor_req_pixels, hor_fetch_pixels;
- uint32_t vert_req_pixels, vert_fetch_pixels;
- uint32_t src_w_tmp, src_h_tmp;
-
- /* re-use color plane 1's config for plane 2 */
- if (i == 2)
- continue;
-
- src_w_tmp = src_w;
- src_h_tmp = src_h;
-
- /*
- * For chroma plane, width is half for the following sub sampled
- * formats. Except in case of decimation, where hardware avoids
- * 1 line of decimation instead of downsampling.
- */
- if (i == 1) {
- if (!deci_w &&
- (fmt->chroma_sample == DPU_CHROMA_420 ||
- fmt->chroma_sample == DPU_CHROMA_H2V1))
- src_w_tmp >>= 1;
- if (!deci_h &&
- (fmt->chroma_sample == DPU_CHROMA_420 ||
- fmt->chroma_sample == DPU_CHROMA_H1V2))
- src_h_tmp >>= 1;
- }
-
- hor_req_pixels = pstate->pixel_ext.roi_w[i];
- vert_req_pixels = pstate->pixel_ext.roi_h[i];
-
- hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
- (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
- (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
- deci_w);
- vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
- (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
- (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
- deci_h);
-
- if ((hor_req_pixels != hor_fetch_pixels) ||
- (hor_fetch_pixels > img_w) ||
- (vert_req_pixels != vert_fetch_pixels) ||
- (vert_fetch_pixels > img_h)) {
- DPU_ERROR_PLANE(pdpu,
- "req %d/%d, fetch %d/%d, src %dx%d\n",
- hor_req_pixels, vert_req_pixels,
- hor_fetch_pixels, vert_fetch_pixels,
- img_w, img_h);
- return -EINVAL;
- }
-
- /*
- * Alpha plane can only be scaled using bilinear or pixel
- * repeat/drop, src_width and src_height are only specified
- * for Y and UV plane
- */
- if (i != 3 &&
- (hor_req_pixels != pstate->scaler3_cfg.src_width[i] ||
- vert_req_pixels != pstate->scaler3_cfg.src_height[i])) {
- DPU_ERROR_PLANE(pdpu,
- "roi[%d] %d/%d, scaler src %dx%d, src %dx%d\n",
- i, pstate->pixel_ext.roi_w[i],
- pstate->pixel_ext.roi_h[i],
- pstate->scaler3_cfg.src_width[i],
- pstate->scaler3_cfg.src_height[i],
- src_w, src_h);
- return -EINVAL;
- }
- }
-
- pstate->scaler_check_state = DPU_PLANE_SCLCHECK_SCALER_V2;
- return 0;
-}
-
static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
@@ -1654,7 +1079,6 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
struct dpu_plane_state *pstate;
const struct dpu_format *fmt;
struct dpu_rect src, dst;
- uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
uint32_t max_upscale, max_downscale, min_src_size, max_linewidth;
bool q16_data = true;

@@ -1674,18 +1098,12 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
goto exit;
}

- deci_w = dpu_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
- deci_h = dpu_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
-
/* src values are in Q16 fixed point, convert to integer */
POPULATE_RECT(&src, state->src_x, state->src_y, state->src_w,
state->src_h, q16_data);
POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
state->crtc_h, !q16_data);

- src_deci_w = DECIMATED_DIMENSION(src.w, deci_w);
- src_deci_h = DECIMATED_DIMENSION(src.h, deci_h);
-
max_upscale = pdpu->pipe_sblk->maxupscale;
max_downscale = pdpu->pipe_sblk->maxdwnscale;
max_linewidth = pdpu->pipe_sblk->common->maxlinewidth;
@@ -1694,7 +1112,7 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
dpu_plane_enabled(plane->state), dpu_plane_enabled(state));

if (!dpu_plane_enabled(state))
- goto modeset_update;
+ goto exit;

fmt = to_dpu_format(msm_framebuffer_format(state->fb));

@@ -1732,18 +1150,6 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
ret = -EINVAL;

/* decimation validation */
- } else if (deci_w || deci_h) {
- if ((deci_w > pdpu->pipe_sblk->common->maxhdeciexp) ||
- (deci_h > pdpu->pipe_sblk->common->maxvdeciexp)) {
- DPU_ERROR_PLANE(pdpu,
- "too much decimation requested\n");
- ret = -EINVAL;
- } else if (fmt->fetch_mode != DPU_FETCH_LINEAR) {
- DPU_ERROR_PLANE(pdpu,
- "decimation requires linear fetch\n");
- ret = -EINVAL;
- }
-
} else if (!(pdpu->features & DPU_SSPP_SCALER) &&
((src.w != dst.w) || (src.h != dst.h))) {
DPU_ERROR_PLANE(pdpu,
@@ -1752,57 +1158,23 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
ret = -EINVAL;

/* check decimated source width */
- } else if (src_deci_w > max_linewidth) {
+ } else if (src.w > max_linewidth) {
DPU_ERROR_PLANE(pdpu,
- "invalid src w:%u, deci w:%u, line w:%u\n",
- src.w, src_deci_w, max_linewidth);
+ "invalid src w:%u, line w:%u\n",
+ src.w, max_linewidth);
ret = -E2BIG;

/* check max scaler capability */
- } else if (((src_deci_w * max_upscale) < dst.w) ||
- ((src_deci_h * max_upscale) < dst.h) ||
- ((dst.w * max_downscale) < src_deci_w) ||
- ((dst.h * max_downscale) < src_deci_h)) {
+ } else if (((src.w * max_upscale) < dst.w) ||
+ ((src.h * max_upscale) < dst.h) ||
+ ((dst.w * max_downscale) < src.w) ||
+ ((dst.h * max_downscale) < src.h)) {
DPU_ERROR_PLANE(pdpu,
"too much scaling requested %ux%u->%ux%u\n",
- src_deci_w, src_deci_h, dst.w, dst.h);
+ src.w, src.h, dst.w, dst.h);
ret = -E2BIG;
- } else if (_dpu_plane_validate_scaler_v2(pdpu, pstate, fmt,
- state->fb->width,
- state->fb->height,
- src.w, src.h, deci_w, deci_h)) {
- ret = -EINVAL;
}

- /* check excl rect configs */
- if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
- struct dpu_rect intersect;
-
- /*
- * Check exclusion rect against src rect.
- * it must intersect with source rect.
- */
- dpu_kms_rect_intersect(&src, &pstate->excl_rect, &intersect);
- if (intersect.w != pstate->excl_rect.w ||
- intersect.h != pstate->excl_rect.h ||
- DPU_FORMAT_IS_YUV(fmt)) {
- DPU_ERROR_PLANE(pdpu,
- "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
- pstate->excl_rect.x, pstate->excl_rect.y,
- pstate->excl_rect.w, pstate->excl_rect.h,
- src.x, src.y, src.w, src.h,
- (char *)&fmt->base.pixel_format);
- ret = -EINVAL;
- }
- DPU_DEBUG_PLANE(pdpu, "excl_rect: {%d,%d,%d,%d}\n",
- pstate->excl_rect.x, pstate->excl_rect.y,
- pstate->excl_rect.w, pstate->excl_rect.h);
- }
-
-modeset_update:
- if (!ret)
- _dpu_plane_sspp_atomic_check_mode_changed(pdpu,
- state, plane->state);
exit:
return ret;
}
@@ -1895,7 +1267,6 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
struct drm_framebuffer *fb;
struct dpu_rect src, dst;
bool q16_data = true;
- int idx;

if (!plane) {
DPU_ERROR("invalid plane\n");
@@ -1925,150 +1296,69 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
fmt = to_dpu_format(msm_framebuffer_format(fb));
nplanes = fmt->num_planes;

- /* force reprogramming of all the parameters, if the flag is set */
- if (pdpu->revalidate) {
- DPU_DEBUG("plane:%d - reconfigure all the parameters\n",
- plane->base.id);
- pstate->dirty = DPU_PLANE_DIRTY_ALL;
- pdpu->revalidate = false;
- }
-
- /* determine what needs to be refreshed */
- while ((idx = msm_property_pop_dirty(&pdpu->property_info,
- &pstate->property_state)) >= 0) {
- switch (idx) {
- case PLANE_PROP_SCALER_V1:
- case PLANE_PROP_SCALER_V2:
- case PLANE_PROP_SCALER_LUT_ED:
- case PLANE_PROP_SCALER_LUT_CIR:
- case PLANE_PROP_SCALER_LUT_SEP:
- case PLANE_PROP_H_DECIMATE:
- case PLANE_PROP_V_DECIMATE:
- case PLANE_PROP_SRC_CONFIG:
- case PLANE_PROP_ZPOS:
- case PLANE_PROP_EXCL_RECT_V1:
- pstate->dirty |= DPU_PLANE_DIRTY_RECTS;
- break;
- case PLANE_PROP_CSC_V1:
- pstate->dirty |= DPU_PLANE_DIRTY_FORMAT;
- break;
- case PLANE_PROP_COLOR_FILL:
- /* potentially need to refresh everything */
- pstate->dirty = DPU_PLANE_DIRTY_ALL;
- break;
- case PLANE_PROP_INFO:
- case PLANE_PROP_ALPHA:
- case PLANE_PROP_BLEND_OP:
- /* no special action required */
- break;
- case PLANE_PROP_PREFILL_SIZE:
- case PLANE_PROP_PREFILL_TIME:
- pstate->dirty |= DPU_PLANE_DIRTY_PERF;
- break;
- default:
- /* unknown property, refresh everything */
- pstate->dirty |= DPU_PLANE_DIRTY_ALL;
- DPU_ERROR("executing full mode set, prp_idx %d\n", idx);
- break;
- }
- }
-
- /**
- * since plane_atomic_check is invoked before crtc_atomic_check
- * in the commit sequence, all the parameters for updating the
- * plane dirty flag will not be available during
- * plane_atomic_check as some features params are updated
- * in crtc_atomic_check (eg.:sDMA). So check for mode_change
- * before sspp update.
- */
- _dpu_plane_sspp_atomic_check_mode_changed(pdpu, state,
- old_state);
-
- if (pstate->dirty & DPU_PLANE_DIRTY_RECTS)
- memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg));
+ memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg));

_dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb);

- /* early out if nothing dirty */
- if (!pstate->dirty)
- return 0;
pstate->pending = true;

pdpu->is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
_dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);

/* update roi config */
- if (pstate->dirty & DPU_PLANE_DIRTY_RECTS) {
- POPULATE_RECT(&src, state->src_x, state->src_y,
- state->src_w, state->src_h, q16_data);
- POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
- state->crtc_w, state->crtc_h, !q16_data);
-
- DPU_DEBUG_PLANE(pdpu,
- "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
- fb->base.id, src.x, src.y, src.w, src.h,
- crtc->base.id, dst.x, dst.y, dst.w, dst.h,
- (char *)&fmt->base.pixel_format,
- DPU_FORMAT_IS_UBWC(fmt));
-
- if (dpu_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
- BIT(DPU_DRM_DEINTERLACE)) {
- DPU_DEBUG_PLANE(pdpu, "deinterlace\n");
- for (idx = 0; idx < DPU_MAX_PLANES; ++idx)
- pdpu->pipe_cfg.layout.plane_pitch[idx] <<= 1;
- src.h /= 2;
- src.y = DIV_ROUND_UP(src.y, 2);
- src.y &= ~0x1;
- }
-
- pdpu->pipe_cfg.src_rect = src;
- pdpu->pipe_cfg.dst_rect = dst;
+ POPULATE_RECT(&src, state->src_x, state->src_y,
+ state->src_w, state->src_h, q16_data);
+ POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
+ state->crtc_w, state->crtc_h, !q16_data);
+
+ DPU_DEBUG_PLANE(pdpu,
+ "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
+ fb->base.id, src.x, src.y, src.w, src.h,
+ crtc->base.id, dst.x, dst.y, dst.w, dst.h,
+ (char *)&fmt->base.pixel_format,
+ DPU_FORMAT_IS_UBWC(fmt));

- _dpu_plane_setup_scaler(pdpu, pstate, fmt, false);

- /* check for color fill */
- pdpu->color_fill = (uint32_t)dpu_plane_get_property(pstate,
- PLANE_PROP_COLOR_FILL);
- if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
- /* skip remaining processing on color fill */
- pstate->dirty = 0x0;
- } else if (pdpu->pipe_hw->ops.setup_rects) {
- pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
- &pdpu->pipe_cfg,
- pstate->multirect_index);
- }
+ pdpu->pipe_cfg.src_rect = src;
+ pdpu->pipe_cfg.dst_rect = dst;

- if (pdpu->pipe_hw->ops.setup_pe &&
- (pstate->multirect_index != DPU_SSPP_RECT_1))
- pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
- &pstate->pixel_ext);
+ _dpu_plane_setup_scaler(pdpu, pstate, fmt, false);

- /**
- * when programmed in multirect mode, scalar block will be
- * bypassed. Still we need to update alpha and bitwidth
- * ONLY for RECT0
- */
- if (pdpu->pipe_hw->ops.setup_scaler &&
- pstate->multirect_index != DPU_SSPP_RECT_1)
- pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
- &pdpu->pipe_cfg, &pstate->pixel_ext,
- &pstate->scaler3_cfg);
-
- /* update excl rect */
- if (pdpu->pipe_hw->ops.setup_excl_rect)
- pdpu->pipe_hw->ops.setup_excl_rect(pdpu->pipe_hw,
- &pstate->excl_rect,
- pstate->multirect_index);
+ /* override for color fill */
+ if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
+ /* skip remaining processing on color fill */
+ return 0;
+ }

- if (pdpu->pipe_hw->ops.setup_multirect)
- pdpu->pipe_hw->ops.setup_multirect(
- pdpu->pipe_hw,
- pstate->multirect_index,
- pstate->multirect_mode);
+ if (pdpu->pipe_hw->ops.setup_rects) {
+ pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
+ &pdpu->pipe_cfg,
+ pstate->multirect_index);
}

- if ((pstate->dirty & DPU_PLANE_DIRTY_FORMAT) &&
- pdpu->pipe_hw->ops.setup_format) {
+ if (pdpu->pipe_hw->ops.setup_pe &&
+ (pstate->multirect_index != DPU_SSPP_RECT_1))
+ pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
+ &pstate->pixel_ext);
+
+ /**
+ * when programmed in multirect mode, scalar block will be
+ * bypassed. Still we need to update alpha and bitwidth
+ * ONLY for RECT0
+ */
+ if (pdpu->pipe_hw->ops.setup_scaler &&
+ pstate->multirect_index != DPU_SSPP_RECT_1)
+ pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
+ &pdpu->pipe_cfg, &pstate->pixel_ext,
+ &pstate->scaler3_cfg);
+
+ if (pdpu->pipe_hw->ops.setup_multirect)
+ pdpu->pipe_hw->ops.setup_multirect(
+ pdpu->pipe_hw,
+ pstate->multirect_index,
+ pstate->multirect_mode);
+
+ if (pdpu->pipe_hw->ops.setup_format) {
src_flags = 0x0;

/* update format */
@@ -2099,35 +1389,16 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
pdpu->csc_ptr = 0;
}

- dpu_color_process_plane_setup(plane);
-
- /* update sharpening */
- if ((pstate->dirty & DPU_PLANE_DIRTY_SHARPEN) &&
- pdpu->pipe_hw->ops.setup_sharpening) {
- pdpu->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
- pdpu->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
- pdpu->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
- pdpu->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
-
- pdpu->pipe_hw->ops.setup_sharpening(pdpu->pipe_hw,
- &pdpu->sharp_cfg);
- }
-
_dpu_plane_set_qos_lut(plane, fb);
_dpu_plane_set_danger_lut(plane, fb);

if (plane->type != DRM_PLANE_TYPE_CURSOR) {
_dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL);
_dpu_plane_set_ot_limit(plane, crtc);
- if (pstate->dirty & DPU_PLANE_DIRTY_PERF)
- _dpu_plane_set_ts_prefill(plane, pstate);
}

_dpu_plane_set_qos_remap(plane);

- /* clear dirty */
- pstate->dirty = 0x0;
-
return 0;
}

@@ -2206,13 +1477,6 @@ void dpu_plane_restore(struct drm_plane *plane)

pdpu = to_dpu_plane(plane);

- /*
- * Revalidate is only true here if idle PC occurred and
- * there is no plane state update in current commit cycle.
- */
- if (!pdpu->revalidate)
- return;
-
DPU_DEBUG_PLANE(pdpu, "\n");

/* last plane state is same as current state */
@@ -2223,21 +1487,9 @@ void dpu_plane_restore(struct drm_plane *plane)
static void _dpu_plane_install_properties(struct drm_plane *plane,
struct dpu_mdss_cfg *catalog, u32 master_plane_id)
{
- static const struct drm_prop_enum_list e_blend_op[] = {
- {DPU_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
- {DPU_DRM_BLEND_OP_OPAQUE, "opaque"},
- {DPU_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
- {DPU_DRM_BLEND_OP_COVERAGE, "coverage"}
- };
- static const struct drm_prop_enum_list e_src_config[] = {
- {DPU_DRM_DEINTERLACE, "deinterlace"}
- };
- const struct dpu_format_extended *format_list;
- struct dpu_kms_info *info;
struct dpu_plane *pdpu = to_dpu_plane(plane);
int zpos_max = 255;
int zpos_def = 0;
- char feature_name[256];

if (!plane || !pdpu) {
DPU_ERROR("invalid plane\n");
@@ -2267,353 +1519,6 @@ static void _dpu_plane_install_properties(struct drm_plane *plane,

msm_property_install_range(&pdpu->property_info, "zpos",
0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
-
- msm_property_install_range(&pdpu->property_info, "alpha",
- 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
-
- if (!master_plane_id) {
- if (pdpu->pipe_sblk->common->maxhdeciexp) {
- msm_property_install_range(&pdpu->property_info,
- "h_decimate", 0x0, 0,
- pdpu->pipe_sblk->common->maxhdeciexp, 0,
- PLANE_PROP_H_DECIMATE);
- }
-
- if (pdpu->pipe_sblk->common->maxvdeciexp) {
- msm_property_install_range(&pdpu->property_info,
- "v_decimate", 0x0, 0,
- pdpu->pipe_sblk->common->maxvdeciexp, 0,
- PLANE_PROP_V_DECIMATE);
- }
-
- if (pdpu->features & BIT(DPU_SSPP_SCALER_QSEED3)) {
- msm_property_install_range(
- &pdpu->property_info, "scaler_v2",
- 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
- msm_property_install_blob(&pdpu->property_info,
- "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
- msm_property_install_blob(&pdpu->property_info,
- "lut_cir", 0,
- PLANE_PROP_SCALER_LUT_CIR);
- msm_property_install_blob(&pdpu->property_info,
- "lut_sep", 0,
- PLANE_PROP_SCALER_LUT_SEP);
- } else if (pdpu->features & DPU_SSPP_SCALER) {
- msm_property_install_range(
- &pdpu->property_info, "scaler_v1", 0x0,
- 0, ~0, 0, PLANE_PROP_SCALER_V1);
- }
-
- if (pdpu->features & BIT(DPU_SSPP_CSC) ||
- pdpu->features & BIT(DPU_SSPP_CSC_10BIT))
- msm_property_install_volatile_range(
- &pdpu->property_info, "csc_v1", 0x0,
- 0, ~0, 0, PLANE_PROP_CSC_V1);
-
- if (pdpu->features & BIT(DPU_SSPP_HSIC)) {
- snprintf(feature_name, sizeof(feature_name), "%s%d",
- "DPU_SSPP_HUE_V",
- pdpu->pipe_sblk->hsic_blk.version >> 16);
- msm_property_install_range(&pdpu->property_info,
- feature_name, 0, 0, 0xFFFFFFFF, 0,
- PLANE_PROP_HUE_ADJUST);
- snprintf(feature_name, sizeof(feature_name), "%s%d",
- "DPU_SSPP_SATURATION_V",
- pdpu->pipe_sblk->hsic_blk.version >> 16);
- msm_property_install_range(&pdpu->property_info,
- feature_name, 0, 0, 0xFFFFFFFF, 0,
- PLANE_PROP_SATURATION_ADJUST);
- snprintf(feature_name, sizeof(feature_name), "%s%d",
- "DPU_SSPP_VALUE_V",
- pdpu->pipe_sblk->hsic_blk.version >> 16);
- msm_property_install_range(&pdpu->property_info,
- feature_name, 0, 0, 0xFFFFFFFF, 0,
- PLANE_PROP_VALUE_ADJUST);
- snprintf(feature_name, sizeof(feature_name), "%s%d",
- "DPU_SSPP_CONTRAST_V",
- pdpu->pipe_sblk->hsic_blk.version >> 16);
- msm_property_install_range(&pdpu->property_info,
- feature_name, 0, 0, 0xFFFFFFFF, 0,
- PLANE_PROP_CONTRAST_ADJUST);
- }
- }
-
- if (pdpu->features & BIT(DPU_SSPP_EXCL_RECT))
- msm_property_install_volatile_range(&pdpu->property_info,
- "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
-
- msm_property_install_enum(&pdpu->property_info, "blend_op", 0x0, 0,
- e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP);
-
- msm_property_install_enum(&pdpu->property_info, "src_config", 0x0, 1,
- e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG);
-
- if (pdpu->pipe_hw->ops.setup_solidfill)
- msm_property_install_range(&pdpu->property_info, "color_fill",
- 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
-
- msm_property_install_range(&pdpu->property_info,
- "prefill_size", 0x0, 0, ~0, 0,
- PLANE_PROP_PREFILL_SIZE);
- msm_property_install_range(&pdpu->property_info,
- "prefill_time", 0x0, 0, ~0, 0,
- PLANE_PROP_PREFILL_TIME);
-
- info = kzalloc(sizeof(struct dpu_kms_info), GFP_KERNEL);
- if (!info) {
- DPU_ERROR("failed to allocate info memory\n");
- return;
- }
-
- msm_property_install_blob(&pdpu->property_info, "capabilities",
- DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
- dpu_kms_info_reset(info);
-
- if (!master_plane_id) {
- format_list = pdpu->pipe_sblk->format_list;
- } else {
- format_list = pdpu->pipe_sblk->virt_format_list;
- dpu_kms_info_add_keyint(info, "primary_smart_plane_id",
- master_plane_id);
- }
-
- if (format_list) {
- dpu_kms_info_start(info, "pixel_formats");
- while (format_list->fourcc_format) {
- dpu_kms_info_append_format(info,
- format_list->fourcc_format,
- format_list->modifier);
- ++format_list;
- }
- dpu_kms_info_stop(info);
- }
-
- if (pdpu->pipe_hw && pdpu->pipe_hw->ops.get_scaler_ver)
- dpu_kms_info_add_keyint(info, "scaler_step_ver",
- pdpu->pipe_hw->ops.get_scaler_ver(pdpu->pipe_hw));
-
- dpu_kms_info_add_keyint(info, "max_linewidth",
- pdpu->pipe_sblk->common->maxlinewidth);
- dpu_kms_info_add_keyint(info, "max_upscale",
- pdpu->pipe_sblk->maxupscale);
- dpu_kms_info_add_keyint(info, "max_downscale",
- pdpu->pipe_sblk->maxdwnscale);
- dpu_kms_info_add_keyint(info, "max_horizontal_deci",
- pdpu->pipe_sblk->common->maxhdeciexp);
- dpu_kms_info_add_keyint(info, "max_vertical_deci",
- pdpu->pipe_sblk->common->maxvdeciexp);
- dpu_kms_info_add_keyint(info, "max_per_pipe_bw",
- pdpu->pipe_sblk->max_per_pipe_bw * 1000LL);
- msm_property_set_blob(&pdpu->property_info, &pdpu->blob_info,
- info->data, DPU_KMS_INFO_DATALEN(info),
- PLANE_PROP_INFO);
-
- kfree(info);
-
- if (pdpu->features & BIT(DPU_SSPP_MEMCOLOR)) {
- snprintf(feature_name, sizeof(feature_name), "%s%d",
- "DPU_SSPP_SKIN_COLOR_V",
- pdpu->pipe_sblk->memcolor_blk.version >> 16);
- msm_property_install_blob(&pdpu->property_info, feature_name, 0,
- PLANE_PROP_SKIN_COLOR);
- snprintf(feature_name, sizeof(feature_name), "%s%d",
- "DPU_SSPP_SKY_COLOR_V",
- pdpu->pipe_sblk->memcolor_blk.version >> 16);
- msm_property_install_blob(&pdpu->property_info, feature_name, 0,
- PLANE_PROP_SKY_COLOR);
- snprintf(feature_name, sizeof(feature_name), "%s%d",
- "DPU_SSPP_FOLIAGE_COLOR_V",
- pdpu->pipe_sblk->memcolor_blk.version >> 16);
- msm_property_install_blob(&pdpu->property_info, feature_name, 0,
- PLANE_PROP_FOLIAGE_COLOR);
- }
-}
-
-static inline void _dpu_plane_set_csc_v1(struct dpu_plane *pdpu, void *usr_ptr)
-{
- struct dpu_drm_csc_v1 csc_v1;
- int i;
-
- if (!pdpu) {
- DPU_ERROR("invalid plane\n");
- return;
- }
-
- pdpu->csc_usr_ptr = NULL;
- if (!usr_ptr) {
- DPU_DEBUG_PLANE(pdpu, "csc data removed\n");
- return;
- }
-
- if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
- DPU_ERROR_PLANE(pdpu, "failed to copy csc data\n");
- return;
- }
-
- /* populate from user space */
- for (i = 0; i < DPU_CSC_MATRIX_COEFF_SIZE; ++i)
- pdpu->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
- for (i = 0; i < DPU_CSC_BIAS_SIZE; ++i) {
- pdpu->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
- pdpu->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
- }
- for (i = 0; i < DPU_CSC_CLAMP_SIZE; ++i) {
- pdpu->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
- pdpu->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
- }
- pdpu->csc_usr_ptr = &pdpu->csc_cfg;
-}
-
-static inline void _dpu_plane_set_scaler_v1(struct dpu_plane *pdpu,
- struct dpu_plane_state *pstate, void *usr)
-{
- struct dpu_drm_scaler_v1 scale_v1;
- struct dpu_hw_pixel_ext *pe;
- int i;
-
- if (!pdpu || !pstate) {
- DPU_ERROR("invalid argument(s)\n");
- return;
- }
-
- pstate->scaler_check_state = DPU_PLANE_SCLCHECK_NONE;
- if (!usr) {
- DPU_DEBUG_PLANE(pdpu, "scale data removed\n");
- return;
- }
-
- if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
- DPU_ERROR_PLANE(pdpu, "failed to copy scale data\n");
- return;
- }
-
- /* force property to be dirty, even if the pointer didn't change */
- msm_property_set_dirty(&pdpu->property_info,
- &pstate->property_state, PLANE_PROP_SCALER_V1);
-
- /* populate from user space */
- pe = &pstate->pixel_ext;
- memset(pe, 0, sizeof(struct dpu_hw_pixel_ext));
- for (i = 0; i < DPU_MAX_PLANES; i++) {
- pe->init_phase_x[i] = scale_v1.init_phase_x[i];
- pe->phase_step_x[i] = scale_v1.phase_step_x[i];
- pe->init_phase_y[i] = scale_v1.init_phase_y[i];
- pe->phase_step_y[i] = scale_v1.phase_step_y[i];
-
- pe->horz_filter[i] = scale_v1.horz_filter[i];
- pe->vert_filter[i] = scale_v1.vert_filter[i];
- }
- for (i = 0; i < DPU_MAX_PLANES; i++) {
- pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
- pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
- pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
- pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
- pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
-
- pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
- pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
- pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
- pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
- pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
- }
-
- pstate->scaler_check_state = DPU_PLANE_SCLCHECK_SCALER_V1;
-
- DPU_EVT32_VERBOSE(DRMID(&pdpu->base));
- DPU_DEBUG_PLANE(pdpu, "user property data copied\n");
-}
-
-static inline void _dpu_plane_set_scaler_v2(struct dpu_plane *pdpu,
- struct dpu_plane_state *pstate, void *usr)
-{
- struct dpu_drm_scaler_v2 scale_v2;
- struct dpu_hw_pixel_ext *pe;
- int i;
- struct dpu_hw_scaler3_cfg *cfg;
-
- if (!pdpu || !pstate) {
- DPU_ERROR("invalid argument(s)\n");
- return;
- }
-
- cfg = &pstate->scaler3_cfg;
- pstate->scaler_check_state = DPU_PLANE_SCLCHECK_NONE;
- if (!usr) {
- DPU_DEBUG_PLANE(pdpu, "scale data removed\n");
- return;
- }
-
- if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
- DPU_ERROR_PLANE(pdpu, "failed to copy scale data\n");
- return;
- }
-
- /* detach/ignore user data if 'disabled' */
- if (!scale_v2.enable) {
- DPU_DEBUG_PLANE(pdpu, "scale data removed\n");
- return;
- }
-
- /* force property to be dirty, even if the pointer didn't change */
- msm_property_set_dirty(&pdpu->property_info,
- &pstate->property_state, PLANE_PROP_SCALER_V2);
-
- /* populate from user space */
- dpu_set_scaler_v2(cfg, &scale_v2);
-
- pe = &pstate->pixel_ext;
- memset(pe, 0, sizeof(struct dpu_hw_pixel_ext));
-
- for (i = 0; i < DPU_MAX_PLANES; i++) {
- pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
- pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
- pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
- pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
- pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
-
- pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
- pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
- pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
- pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
- pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
- }
- pstate->scaler_check_state = DPU_PLANE_SCLCHECK_SCALER_V2_CHECK;
-
- DPU_EVT32_VERBOSE(DRMID(&pdpu->base), cfg->enable, cfg->de.enable,
- cfg->src_width[0], cfg->src_height[0],
- cfg->dst_width, cfg->dst_height);
- DPU_DEBUG_PLANE(pdpu, "user property data copied\n");
-}
-
-static void _dpu_plane_set_excl_rect_v1(struct dpu_plane *pdpu,
- struct dpu_plane_state *pstate, void *usr_ptr)
-{
- struct drm_clip_rect excl_rect_v1;
-
- if (!pdpu) {
- DPU_ERROR("invalid plane\n");
- return;
- }
-
- if (!usr_ptr) {
- DPU_DEBUG_PLANE(pdpu, "invalid excl_rect user data\n");
- return;
- }
-
- if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
- DPU_ERROR_PLANE(pdpu, "failed to copy excl_rect data\n");
- return;
- }
-
- /* populate from user space */
- pstate->excl_rect.x = excl_rect_v1.x1;
- pstate->excl_rect.y = excl_rect_v1.y1;
- pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
- pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
-
- DPU_DEBUG_PLANE(pdpu, "excl_rect: {%d,%d,%d,%d}\n",
- pstate->excl_rect.x, pstate->excl_rect.y,
- pstate->excl_rect.w, pstate->excl_rect.h);
}

static int dpu_plane_atomic_set_property(struct drm_plane *plane,
@@ -2622,7 +1527,7 @@ static int dpu_plane_atomic_set_property(struct drm_plane *plane,
{
struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL;
struct dpu_plane_state *pstate;
- int idx, ret = -EINVAL;
+ int ret = -EINVAL;

DPU_DEBUG_PLANE(pdpu, "\n");

@@ -2634,31 +1539,6 @@ static int dpu_plane_atomic_set_property(struct drm_plane *plane,
pstate = to_dpu_plane_state(state);
ret = msm_property_atomic_set(&pdpu->property_info,
&pstate->property_state, property, val);
- if (!ret) {
- idx = msm_property_index(&pdpu->property_info,
- property);
- switch (idx) {
- case PLANE_PROP_CSC_V1:
- _dpu_plane_set_csc_v1(pdpu,
- u64_to_user_ptr(val));
- break;
- case PLANE_PROP_SCALER_V1:
- _dpu_plane_set_scaler_v1(pdpu, pstate,
- u64_to_user_ptr(val));
- break;
- case PLANE_PROP_SCALER_V2:
- _dpu_plane_set_scaler_v2(pdpu, pstate,
- u64_to_user_ptr(val));
- break;
- case PLANE_PROP_EXCL_RECT_V1:
- _dpu_plane_set_excl_rect_v1(pdpu, pstate,
- u64_to_user_ptr(val));
- break;
- default:
- /* nothing to do */
- break;
- }
- }
}

DPU_DEBUG_PLANE(pdpu, "%s[%d] <= 0x%llx ret=%d\n",
@@ -2770,7 +1650,6 @@ static void dpu_plane_destroy_state(struct drm_plane *plane,
msm_property_duplicate_state(&pdpu->property_info, old_state, pstate,
&pstate->property_state, pstate->property_values);

- pstate->dirty = 0x0;
pstate->pending = false;

__drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
@@ -3168,6 +2047,8 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
if (ret)
goto clean_sspp;

+ pdpu->catalog = kms->catalog;
+
/* success! finalize initialization */
drm_plane_helper_add(plane, &dpu_plane_helper_funcs);

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 25b6b15..a06c8b4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -26,32 +26,6 @@
#include "dpu_hw_mdss.h"
#include "dpu_hw_sspp.h"

-/* dirty bits for update function */
-#define DPU_PLANE_DIRTY_RECTS 0x1
-#define DPU_PLANE_DIRTY_FORMAT 0x2
-#define DPU_PLANE_DIRTY_SHARPEN 0x4
-#define DPU_PLANE_DIRTY_PERF 0x8
-#define DPU_PLANE_DIRTY_ALL 0xFFFFFFFF
-
-/**
- * enum dpu_plane_sclcheck_state - User scaler data status
- *
- * @DPU_PLANE_SCLCHECK_NONE: No user data provided
- * @DPU_PLANE_SCLCHECK_INVALID: Invalid user data provided
- * @DPU_PLANE_SCLCHECK_SCALER_V1: Valid scaler v1 data
- * @DPU_PLANE_SCLCHECK_SCALER_V1_CHECK: Unchecked scaler v1 data
- * @DPU_PLANE_SCLCHECK_SCALER_V2: Valid scaler v2 data
- * @DPU_PLANE_SCLCHECK_SCALER_V2_CHECK: Unchecked scaler v2 data
- */
-enum dpu_plane_sclcheck_state {
- DPU_PLANE_SCLCHECK_NONE,
- DPU_PLANE_SCLCHECK_INVALID,
- DPU_PLANE_SCLCHECK_SCALER_V1,
- DPU_PLANE_SCLCHECK_SCALER_V1_CHECK,
- DPU_PLANE_SCLCHECK_SCALER_V2,
- DPU_PLANE_SCLCHECK_SCALER_V2_CHECK,
-};
-
/**
* struct dpu_plane_state: Define dpu extension of drm plane state object
* @base: base drm plane state object
@@ -60,8 +34,6 @@ enum dpu_plane_sclcheck_state {
* @aspace: pointer to address space for input/output buffers
* @input_fence: dereferenced input fence pointer
* @stage: assigned by crtc blender
- * @excl_rect: exclusion rect values
- * @dirty: bitmask for which pipe h/w config functions need to be updated
* @multirect_index: index of the rectangle of SSPP
* @multirect_mode: parallel or time multiplex multirect mode
* @pending: whether the current update is still pending
@@ -77,8 +49,6 @@ struct dpu_plane_state {
struct msm_gem_address_space *aspace;
void *input_fence;
enum dpu_stage stage;
- struct dpu_rect excl_rect;
- uint32_t dirty;
uint32_t multirect_index;
uint32_t multirect_mode;
bool pending;
@@ -86,7 +56,6 @@ struct dpu_plane_state {
/* scaler configuration */
struct dpu_hw_scaler3_cfg scaler3_cfg;
struct dpu_hw_pixel_ext pixel_ext;
- enum dpu_plane_sclcheck_state scaler_check_state;

struct dpu_hw_pipe_cdp_cfg cdp_cfg;
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c
deleted file mode 100644
index b81e071..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "dpu_reg_dma.h"
-#include "dpu_hw_reg_dma_v1.h"
-#include "dpu_dbg.h"
-
-static int default_check_support(enum dpu_reg_dma_features feature,
- enum dpu_reg_dma_blk blk,
- bool *is_supported)
-{
-
- if (!is_supported)
- return -EINVAL;
-
- *is_supported = false;
- return 0;
-}
-
-static int default_setup_payload(struct dpu_reg_dma_setup_ops_cfg *cfg)
-{
- DRM_ERROR("not implemented\n");
- return -EINVAL;
-}
-
-static int default_kick_off(struct dpu_reg_dma_kickoff_cfg *cfg)
-{
- DRM_ERROR("not implemented\n");
- return -EINVAL;
-
-}
-
-static int default_reset(struct dpu_hw_ctl *ctl)
-{
- DRM_ERROR("not implemented\n");
- return -EINVAL;
-}
-
-struct dpu_reg_dma_buffer *default_alloc_reg_dma_buf(u32 size)
-{
- DRM_ERROR("not implemented\n");
- return ERR_PTR(-EINVAL);
-}
-
-int default_dealloc_reg_dma(struct dpu_reg_dma_buffer *lut_buf)
-{
- DRM_ERROR("not implemented\n");
- return -EINVAL;
-}
-
-static int default_buf_reset_reg_dma(struct dpu_reg_dma_buffer *lut_buf)
-{
- DRM_ERROR("not implemented\n");
- return -EINVAL;
-}
-
-static int default_last_command(struct dpu_hw_ctl *ctl,
- enum dpu_reg_dma_queue q)
-{
- return 0;
-}
-
-static struct dpu_hw_reg_dma reg_dma = {
- .ops = {default_check_support, default_setup_payload,
- default_kick_off, default_reset, default_alloc_reg_dma_buf,
- default_dealloc_reg_dma, default_buf_reset_reg_dma,
- default_last_command},
-};
-
-int dpu_reg_dma_init(void __iomem *addr, struct dpu_mdss_cfg *m,
- struct drm_device *dev)
-{
- int rc = 0;
-
- if (!addr || !m || !dev) {
- DRM_DEBUG("invalid addr %pK catalog %pK dev %pK\n", addr, m,
- dev);
- return 0;
- }
-
- reg_dma.drm_dev = dev;
- reg_dma.caps = &m->dma_cfg;
- reg_dma.addr = addr;
-
- if (!m->reg_dma_count)
- return 0;
-
- switch (reg_dma.caps->version) {
- case 1:
- rc = init_v1(&reg_dma);
- if (rc)
- DRM_DEBUG("init v1 dma ops failed\n");
- else
- dpu_dbg_reg_register_base("reg_dma", addr,
- reg_dma.caps->len);
- break;
- default:
- break;
- }
-
- return 0;
-}
-
-struct dpu_hw_reg_dma_ops *dpu_reg_dma_get_ops(void)
-{
- return &reg_dma.ops;
-}
-
-void dpu_reg_dma_deinit(void)
-{
- struct dpu_hw_reg_dma op = {
- .ops = {default_check_support, default_setup_payload,
- default_kick_off, default_reset, default_alloc_reg_dma_buf,
- default_dealloc_reg_dma, default_buf_reset_reg_dma,
- default_last_command},
- };
-
- if (!reg_dma.drm_dev || !reg_dma.caps)
- return;
-
- switch (reg_dma.caps->version) {
- case 1:
- deinit_v1();
- break;
- default:
- break;
- }
- memset(&reg_dma, 0, sizeof(reg_dma));
- memcpy(&reg_dma.ops, &op.ops, sizeof(op.ops));
-}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h
deleted file mode 100644
index 1fb92ed..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DPU_REG_DMA_H
-#define _DPU_REG_DMA_H
-
-#include "msm_drv.h"
-#include "dpu_hw_catalog.h"
-#include "dpu_hw_mdss.h"
-#include "dpu_hw_top.h"
-#include "dpu_hw_util.h"
-
-/**
- * enum dpu_reg_dma_op - defines operations supported by reg dma
- * @REG_DMA_READ: Read the histogram into buffer provided
- * @REG_DMA_WRITE: Write the reg dma configuration into MDP block
- * @REG_DMA_OP_MAX: Max operation which indicates that op is invalid
- */
-enum dpu_reg_dma_op {
- REG_DMA_READ,
- REG_DMA_WRITE,
- REG_DMA_OP_MAX
-};
-
-/**
- * enum dpu_reg_dma_read_sel - defines the blocks for histogram read
- * @DSPP0_HIST: select dspp0
- * @DSPP1_HIST: select dspp1
- * @DSPP2_HIST: select dspp2
- * @DSPP3_HIST: select dspp3
- * @DSPP_HIST_MAX: invalid selection
- */
-enum dpu_reg_dma_read_sel {
- DSPP0_HIST,
- DSPP1_HIST,
- DSPP2_HIST,
- DSPP3_HIST,
- DSPP_HIST_MAX,
-};
-
-/**
- * enum dpu_reg_dma_features - defines features supported by reg dma
- * @QSEED: qseed feature
- * @GAMUT: gamut feature
- * @IGC: inverse gamma correction
- * @PCC: polynomical color correction
- * @VLUT: PA vlut
- * @MEM_COLOR: memory color
- * @SIX_ZONE: six zone
- * @HSIC: Hue, saturation and contrast
- * @GC: gamma correction
- * @REG_DMA_FEATURES_MAX: invalid selection
- */
-enum dpu_reg_dma_features {
- QSEED,
- GAMUT,
- IGC,
- PCC,
- VLUT,
- MEM_COLOR,
- SIX_ZONE,
- HSIC,
- GC,
- REG_DMA_FEATURES_MAX,
-};
-
-/**
- * enum dpu_reg_dma_queue - defines reg dma write queue values
- * @DMA_CTL_QUEUE0: select queue0
- * @DMA_CTL_QUEUE1: select queue1
- * @DMA_CTL_QUEUE_MAX: invalid selection
- */
-enum dpu_reg_dma_queue {
- DMA_CTL_QUEUE0,
- DMA_CTL_QUEUE1,
- DMA_CTL_QUEUE_MAX,
-};
-
-/**
- * enum dpu_reg_dma_trigger_mode - defines reg dma ops trigger mode
- * @WRITE_IMMEDIATE: trigger write op immediately
- * @WRITE_TRIGGER: trigger write op when sw trigger is issued
- * @READ_IMMEDIATE: trigger read op immediately
- * @READ_TRIGGER: trigger read op when sw trigger is issued
- * @TIGGER_MAX: invalid trigger selection
- */
-enum dpu_reg_dma_trigger_mode {
- WRITE_IMMEDIATE,
- WRITE_TRIGGER,
- READ_IMMEDIATE,
- READ_TRIGGER,
- TIGGER_MAX,
-};
-
-/**
- * enum dpu_reg_dma_setup_ops - defines reg dma write configuration
- * @HW_BLK_SELECT: op for selecting the hardware block
- * @REG_SINGLE_WRITE: op for writing single register value
- * at the address provided
- * @REG_BLK_WRITE_SINGLE: op for writing multiple registers using hw index
- * register
- * @REG_BLK_WRITE_INC: op for writing multiple registers using auto address
- * increment
- * @REG_BLK_WRITE_MULTIPLE: op for writing hw index based registers at
- * non-consecutive location
- * @REG_DMA_SETUP_OPS_MAX: invalid operation
- */
-enum dpu_reg_dma_setup_ops {
- HW_BLK_SELECT,
- REG_SINGLE_WRITE,
- REG_BLK_WRITE_SINGLE,
- REG_BLK_WRITE_INC,
- REG_BLK_WRITE_MULTIPLE,
- REG_DMA_SETUP_OPS_MAX,
-};
-
-/**
- * enum dpu_reg_dma_blk - defines blocks for which reg dma op should be
- * performed
- * @VIG0: select vig0 block
- * @VIG1: select vig1 block
- * @VIG2: select vig2 block
- * @VIG3: select vig3 block
- * @LM0: select lm0 block
- * @LM1: select lm1 block
- * @LM2: select lm2 block
- * @LM3: select lm3 block
- * @DSPP0: select dspp0 block
- * @DSPP1: select dspp1 block
- * @DSPP2: select dspp2 block
- * @DSPP3: select dspp3 block
- * @DMA0: select dma0 block
- * @DMA1: select dma1 block
- * @DMA2: select dma2 block
- * @DMA3: select dma3 block
- * @SSPP_IGC: select sspp igc block
- * @DSPP_IGC: select dspp igc block
- * @MDSS: select mdss block
- */
-enum dpu_reg_dma_blk {
- VIG0 = BIT(0),
- VIG1 = BIT(1),
- VIG2 = BIT(2),
- VIG3 = BIT(3),
- LM0 = BIT(4),
- LM1 = BIT(5),
- LM2 = BIT(6),
- LM3 = BIT(7),
- DSPP0 = BIT(8),
- DSPP1 = BIT(9),
- DSPP2 = BIT(10),
- DSPP3 = BIT(11),
- DMA0 = BIT(12),
- DMA1 = BIT(13),
- DMA2 = BIT(14),
- DMA3 = BIT(15),
- SSPP_IGC = BIT(16),
- DSPP_IGC = BIT(17),
- MDSS = BIT(31)
-};
-
-/**
- * struct dpu_reg_dma_buffer - defines reg dma buffer structure.
- * @drm_gem_object *buf: drm gem handle for the buffer
- * @asapce : pointer to address space
- * @buffer_size: buffer size
- * @index: write pointer index
- * @iova: device address
- * @vaddr: cpu address
- * @next_op_allowed: operation allowed on the buffer
- * @ops_completed: operations completed on buffer
- */
-struct dpu_reg_dma_buffer {
- struct drm_gem_object *buf;
- struct msm_gem_address_space *aspace;
- u32 buffer_size;
- u32 index;
- u64 iova;
- void *vaddr;
- u32 next_op_allowed;
- u32 ops_completed;
-};
-
-/**
- * struct dpu_reg_dma_setup_ops_cfg - defines structure for reg dma ops on the
- * reg dma buffer.
- * @dpu_reg_dma_setup_ops ops: ops to be performed
- * @dpu_reg_dma_blk blk: block on which op needs to be performed
- * @dpu_reg_dma_features feature: feature on which op needs to be done
- * @wrap_size: valid for REG_BLK_WRITE_MULTIPLE, indicates reg index location
- * size
- * @inc: valid for REG_BLK_WRITE_MULTIPLE indicates whether reg index location
- * needs an increment or decrement.
- * 0 - decrement
- * 1 - increment
- * @blk_offset: offset for blk, valid for HW_BLK_SELECT op only
- * @dpu_reg_dma_buffer *dma_buf: reg dma buffer on which op needs to be
- * performed
- * @data: pointer to payload which has to be written into reg dma buffer for
- * selected op.
- * @data_size: size of payload in data
- */
-struct dpu_reg_dma_setup_ops_cfg {
- enum dpu_reg_dma_setup_ops ops;
- enum dpu_reg_dma_blk blk;
- enum dpu_reg_dma_features feature;
- u32 wrap_size;
- u32 inc;
- u32 blk_offset;
- struct dpu_reg_dma_buffer *dma_buf;
- u32 *data;
- u32 data_size;
-};
-
-/**
- * struct dpu_reg_dma_kickoff_cfg - commit reg dma buffer to hw engine
- * @ctl: ctl for which reg dma buffer needs to be committed.
- * @dma_buf: reg dma buffer with iova address and size info
- * @block_select: histogram read select
- * @trigger_mode: reg dma ops trigger mode
- * @queue_select: queue on which reg dma buffer will be submitted
- * @last_command: last command for this vsync
- */
-struct dpu_reg_dma_kickoff_cfg {
- struct dpu_hw_ctl *ctl;
- enum dpu_reg_dma_op op;
- struct dpu_reg_dma_buffer *dma_buf;
- enum dpu_reg_dma_read_sel block_select;
- enum dpu_reg_dma_trigger_mode trigger_mode;
- enum dpu_reg_dma_queue queue_select;
- u32 last_command;
-};
-
-/**
- * struct dpu_hw_reg_dma_ops - ops supported by reg dma frame work, based on
- * version of reg dma appropriate ops will be
- * installed during driver probe.
- * @check_support: checks if reg dma is supported on this platform for a
- * feature
- * @setup_payload: setup reg dma buffer based on ops and payload provided by
- * client
- * @kick_off: submit the reg dma buffer to hw enginge
- * @reset: reset the reg dma hw enginge for a ctl
- * @alloc_reg_dma_buf: allocate reg dma buffer
- * @dealloc_reg_dma: de-allocate reg dma buffer
- * @reset_reg_dma_buf: reset the buffer to init state
- * @last_command: notify control that last command is queued
- */
-struct dpu_hw_reg_dma_ops {
- int (*check_support)(enum dpu_reg_dma_features feature,
- enum dpu_reg_dma_blk blk,
- bool *is_supported);
- int (*setup_payload)(struct dpu_reg_dma_setup_ops_cfg *cfg);
- int (*kick_off)(struct dpu_reg_dma_kickoff_cfg *cfg);
- int (*reset)(struct dpu_hw_ctl *ctl);
- struct dpu_reg_dma_buffer* (*alloc_reg_dma_buf)(u32 size);
- int (*dealloc_reg_dma)(struct dpu_reg_dma_buffer *lut_buf);
- int (*reset_reg_dma_buf)(struct dpu_reg_dma_buffer *buf);
- int (*last_command)(struct dpu_hw_ctl *ctl, enum dpu_reg_dma_queue q);
-};
-
-/**
- * struct dpu_hw_reg_dma - structure to hold reg dma hw info
- * @drm_dev: drm driver dev handle
- * @caps: reg dma hw caps on the platform
- * @ops: reg dma ops supported on the platform
- * @addr: reg dma hw block base address
- */
-struct dpu_hw_reg_dma {
- struct drm_device *drm_dev;
- const struct dpu_reg_dma_cfg *caps;
- struct dpu_hw_reg_dma_ops ops;
- void __iomem *addr;
-};
-
-/**
- * dpu_reg_dma_init() - function called to initialize reg dma during dpu
- * drm driver probe. If reg dma is supported by dpu
- * ops for reg dma version will be installed.
- * if reg dma is not supported by dpu default ops will
- * be installed. check_support of default ops will
- * return false, hence the clients should fall back to
- * AHB programming.
- * @addr: reg dma block base address
- * @m: catalog which contains dpu hw capabilities and offsets
- * @dev: drm driver device handle
- */
-int dpu_reg_dma_init(void __iomem *addr, struct dpu_mdss_cfg *m,
- struct drm_device *dev);
-
-/**
- * dpu_reg_dma_get_ops() - singleton module, ops is returned to the clients
- * who call this api.
- */
-struct dpu_hw_reg_dma_ops *dpu_reg_dma_get_ops(void);
-
-/**
- * dpu_reg_dma_deinit() - de-initialize the reg dma
- */
-void dpu_reg_dma_deinit(void);
-#endif /* _DPU_REG_DMA_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index bddce41..b550d7d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -17,7 +17,6 @@
#include "dpu_hw_lm.h"
#include "dpu_hw_ctl.h"
#include "dpu_hw_cdm.h"
-#include "dpu_hw_dspp.h"
#include "dpu_hw_ds.h"
#include "dpu_hw_pingpong.h"
#include "dpu_hw_intf.h"
@@ -28,7 +27,6 @@

#define RM_RQ_LOCK(r) ((r)->top_ctrl & BIT(DPU_RM_TOPCTL_RESERVE_LOCK))
#define RM_RQ_CLEAR(r) ((r)->top_ctrl & BIT(DPU_RM_TOPCTL_RESERVE_CLEAR))
-#define RM_RQ_DSPP(r) ((r)->top_ctrl & BIT(DPU_RM_TOPCTL_DSPP))
#define RM_RQ_DS(r) ((r)->top_ctrl & BIT(DPU_RM_TOPCTL_DS))
#define RM_IS_TOPOLOGY_MATCH(t, r) ((t).num_lm == (r).num_lm && \
(t).num_comp_enc == (r).num_enc && \
@@ -236,9 +234,6 @@ static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw)
case DPU_HW_BLK_LM:
dpu_hw_lm_destroy(hw);
break;
- case DPU_HW_BLK_DSPP:
- dpu_hw_dspp_destroy(hw);
- break;
case DPU_HW_BLK_DS:
dpu_hw_ds_destroy(hw);
break;
@@ -318,9 +313,6 @@ static int _dpu_rm_hw_blk_create(
case DPU_HW_BLK_LM:
hw = dpu_hw_lm_init(id, mmio, cat);
break;
- case DPU_HW_BLK_DSPP:
- hw = dpu_hw_dspp_init(id, mmio, cat);
- break;
case DPU_HW_BLK_DS:
hw = dpu_hw_ds_init(id, mmio, cat);
break;
@@ -428,15 +420,6 @@ int dpu_rm_init(struct dpu_rm *rm,
}
}

- for (i = 0; i < cat->dspp_count; i++) {
- rc = _dpu_rm_hw_blk_create(rm, cat, mmio, DPU_HW_BLK_DSPP,
- cat->dspp[i].id, &cat->dspp[i]);
- if (rc) {
- DPU_ERROR("failed: dspp hw not available\n");
- goto fail;
- }
- }
-
if (cat->mdp[0].has_dest_scaler) {
for (i = 0; i < cat->ds_count; i++) {
rc = _dpu_rm_hw_blk_create(rm, cat, mmio, DPU_HW_BLK_DS,
@@ -500,16 +483,14 @@ int dpu_rm_init(struct dpu_rm *rm,
/**
* _dpu_rm_check_lm_and_get_connected_blks - check if proposed layer mixer meets
* proposed use case requirements, incl. hardwired dependent blocks like
- * pingpong, and dspp.
+ * pingpong
* @rm: dpu resource manager handle
* @rsvp: reservation currently being created
* @reqs: proposed use case requirements
* @lm: proposed layer mixer, function checks if lm, and all other hardwired
- * blocks connected to the lm (pp, dspp) are available and appropriate
- * @dspp: output parameter, dspp block attached to the layer mixer.
- * NULL if dspp was not available, or not matching requirements.
+ * blocks connected to the lm (pp) is available and appropriate
* @pp: output parameter, pingpong block attached to the layer mixer.
- * NULL if dspp was not available, or not matching requirements.
+ * NULL if pp was not available, or not matching requirements.
* @primary_lm: if non-null, this function check if lm is compatible primary_lm
* as well as satisfying all other requirements
* @Return: true if lm matches all requirements, false otherwise
@@ -519,21 +500,19 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
struct dpu_rm_rsvp *rsvp,
struct dpu_rm_requirements *reqs,
struct dpu_rm_hw_blk *lm,
- struct dpu_rm_hw_blk **dspp,
struct dpu_rm_hw_blk **ds,
struct dpu_rm_hw_blk **pp,
struct dpu_rm_hw_blk *primary_lm)
{
const struct dpu_lm_cfg *lm_cfg = to_dpu_hw_mixer(lm->hw)->cap;
struct dpu_rm_hw_iter iter;
- bool is_valid_dspp, is_valid_ds, ret;
+ bool is_valid_ds;

- *dspp = NULL;
*ds = NULL;
*pp = NULL;

- DPU_DEBUG("check lm %d: dspp %d ds %d pp %d\n",
- lm_cfg->id, lm_cfg->dspp,
+ DPU_DEBUG("check lm %d ds %d pp %d\n",
+ lm_cfg->id,
lm_cfg->ds, lm_cfg->pingpong);

/* Check if this layer mixer is a peer of the proposed primary LM */
@@ -548,28 +527,13 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
}
}

- is_valid_dspp = (lm_cfg->dspp != DSPP_MAX) ? true : false;
is_valid_ds = (lm_cfg->ds != DS_MAX) ? true : false;

- /**
- * RM_RQ_X: specification of which LMs to choose
- * is_valid_X: indicates whether LM is tied with block X
- * ret: true if given LM matches the user requirement, false otherwise
- */
- if (RM_RQ_DSPP(reqs) && RM_RQ_DS(reqs))
- ret = (is_valid_dspp && is_valid_ds);
- else if (RM_RQ_DSPP(reqs))
- ret = is_valid_dspp;
- else if (RM_RQ_DS(reqs))
- ret = is_valid_ds;
- else
- ret = !(is_valid_dspp || is_valid_ds);
+ if (RM_RQ_DS(reqs) && !is_valid_ds) {
+ DPU_DEBUG("fail:lm(%d)req_ds(%d)ds(%d)\n",
+ lm_cfg->id, (bool)(RM_RQ_DS(reqs)), lm_cfg->ds);

- if (!ret) {
- DPU_DEBUG("fail:lm(%d)req_dspp(%d)dspp(%d)req_ds(%d)ds(%d)\n",
- lm_cfg->id, (bool)(RM_RQ_DSPP(reqs)), lm_cfg->dspp,
- (bool)(RM_RQ_DS(reqs)), lm_cfg->ds);
- return ret;
+ return false;
}

/* Already reserved? */
@@ -578,28 +542,6 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
return false;
}

- if (lm_cfg->dspp != DSPP_MAX) {
- dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_DSPP);
- while (_dpu_rm_get_hw_locked(rm, &iter)) {
- if (iter.blk->id == lm_cfg->dspp) {
- *dspp = iter.blk;
- break;
- }
- }
-
- if (!*dspp) {
- DPU_DEBUG("lm %d failed to retrieve dspp %d\n", lm->id,
- lm_cfg->dspp);
- return false;
- }
-
- if (RESERVED_BY_OTHER(*dspp, rsvp)) {
- DPU_DEBUG("lm %d dspp %d already reserved\n",
- lm->id, (*dspp)->id);
- return false;
- }
- }
-
if (lm_cfg->ds != DS_MAX) {
dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_DS);
while (_dpu_rm_get_hw_locked(rm, &iter)) {
@@ -638,7 +580,6 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
if (RESERVED_BY_OTHER(*pp, rsvp)) {
DPU_DEBUG("lm %d pp %d already reserved\n", lm->id,
(*pp)->id);
- *dspp = NULL;
*ds = NULL;
return false;
}
@@ -653,7 +594,6 @@ static int _dpu_rm_reserve_lms(

{
struct dpu_rm_hw_blk *lm[MAX_BLOCKS];
- struct dpu_rm_hw_blk *dspp[MAX_BLOCKS];
struct dpu_rm_hw_blk *ds[MAX_BLOCKS];
struct dpu_rm_hw_blk *pp[MAX_BLOCKS];
struct dpu_rm_hw_iter iter_i, iter_j;
@@ -670,7 +610,6 @@ static int _dpu_rm_reserve_lms(
while (lm_count != reqs->topology->num_lm &&
_dpu_rm_get_hw_locked(rm, &iter_i)) {
memset(&lm, 0, sizeof(lm));
- memset(&dspp, 0, sizeof(dspp));
memset(&ds, 0, sizeof(ds));
memset(&pp, 0, sizeof(pp));

@@ -678,8 +617,7 @@ static int _dpu_rm_reserve_lms(
lm[lm_count] = iter_i.blk;

if (!_dpu_rm_check_lm_and_get_connected_blks(
- rm, rsvp, reqs, lm[lm_count],
- &dspp[lm_count], &ds[lm_count],
+ rm, rsvp, reqs, lm[lm_count], &ds[lm_count],
&pp[lm_count], NULL))
continue;

@@ -695,8 +633,8 @@ static int _dpu_rm_reserve_lms(

if (!_dpu_rm_check_lm_and_get_connected_blks(
rm, rsvp, reqs, iter_j.blk,
- &dspp[lm_count], &ds[lm_count],
- &pp[lm_count], iter_i.blk))
+ &ds[lm_count], &pp[lm_count],
+ iter_i.blk))
continue;

lm[lm_count] = iter_j.blk;
@@ -715,14 +653,11 @@ static int _dpu_rm_reserve_lms(

lm[i]->rsvp_nxt = rsvp;
pp[i]->rsvp_nxt = rsvp;
- if (dspp[i])
- dspp[i]->rsvp_nxt = rsvp;

if (ds[i])
ds[i]->rsvp_nxt = rsvp;

DPU_EVT32(lm[i]->type, rsvp->enc_id, lm[i]->id, pp[i]->id,
- dspp[i] ? dspp[i]->id : 0,
ds[i] ? ds[i]->id : 0);
}

@@ -889,18 +824,7 @@ static int _dpu_rm_make_next_rsvp(
rsvp->topology = reqs->topology->top_name;
list_add_tail(&rsvp->list, &rm->rsvps);

- /*
- * Assign LMs and blocks whose usage is tied to them: DSPP & Pingpong.
- * Do assignment preferring to give away low-resource mixers first:
- * - Check mixers without DSPPs
- * - Only then allow to grab from mixers with DSPP capability
- */
ret = _dpu_rm_reserve_lms(rm, rsvp, reqs);
- if (ret && !RM_RQ_DSPP(reqs)) {
- reqs->top_ctrl |= BIT(DPU_RM_TOPCTL_DSPP);
- ret = _dpu_rm_reserve_lms(rm, rsvp, reqs);
- }
-
if (ret) {
DPU_ERROR("unable to find appropriate mixers\n");
return ret;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 4c77874..ef3f67b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -45,13 +45,11 @@ enum dpu_rm_topology_name {
* release any reservation held by this display.
* Normal behavior would not impact the
* reservation list during the AtomicTest phase.
- * @DPU_RM_TOPCTL_DSPP: Require layer mixers with DSPP capabilities
* @DPU_RM_TOPCTL_DS : Require layer mixers with DS capabilities
*/
enum dpu_rm_topology_control {
DPU_RM_TOPCTL_RESERVE_LOCK,
DPU_RM_TOPCTL_RESERVE_CLEAR,
- DPU_RM_TOPCTL_DSPP,
DPU_RM_TOPCTL_DS,
};

diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index b73112a..5770ac0 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -74,39 +74,11 @@ struct msm_file_private {
};

enum msm_mdp_plane_property {
- /* blob properties, always put these first */
- PLANE_PROP_SCALER_V1,
- PLANE_PROP_SCALER_V2,
- PLANE_PROP_CSC_V1,
- PLANE_PROP_INFO,
- PLANE_PROP_SCALER_LUT_ED,
- PLANE_PROP_SCALER_LUT_CIR,
- PLANE_PROP_SCALER_LUT_SEP,
- PLANE_PROP_SKIN_COLOR,
- PLANE_PROP_SKY_COLOR,
- PLANE_PROP_FOLIAGE_COLOR,
- PLANE_PROP_ROT_CAPS_V1,
-
/* # of blob properties */
PLANE_PROP_BLOBCOUNT,

/* range properties */
PLANE_PROP_ZPOS = PLANE_PROP_BLOBCOUNT,
- PLANE_PROP_ALPHA,
- PLANE_PROP_COLOR_FILL,
- PLANE_PROP_H_DECIMATE,
- PLANE_PROP_V_DECIMATE,
- PLANE_PROP_HUE_ADJUST,
- PLANE_PROP_SATURATION_ADJUST,
- PLANE_PROP_VALUE_ADJUST,
- PLANE_PROP_CONTRAST_ADJUST,
- PLANE_PROP_EXCL_RECT_V1,
- PLANE_PROP_PREFILL_SIZE,
- PLANE_PROP_PREFILL_TIME,
-
- /* enum/bitmask properties */
- PLANE_PROP_BLEND_OP,
- PLANE_PROP_SRC_CONFIG,

/* total # of properties */
PLANE_PROP_COUNT
diff --git a/include/uapi/drm/dpu_drm.h b/include/uapi/drm/dpu_drm.h
index da73279..93af1fb 100644
--- a/include/uapi/drm/dpu_drm.h
+++ b/include/uapi/drm/dpu_drm.h
@@ -66,193 +66,6 @@
/* DRM bitmasks are restricted to 0..63 */
#define DPU_DRM_BITMASK_COUNT 64

-/**
- * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
- * @num_ext_pxls_lr: Number of total horizontal pixels
- * @num_ext_pxls_tb: Number of total vertical lines
- * @left_ftch: Number of extra pixels to overfetch from left
- * @right_ftch: Number of extra pixels to overfetch from right
- * @top_ftch: Number of extra lines to overfetch from top
- * @btm_ftch: Number of extra lines to overfetch from bottom
- * @left_rpt: Number of extra pixels to repeat from left
- * @right_rpt: Number of extra pixels to repeat from right
- * @top_rpt: Number of extra lines to repeat from top
- * @btm_rpt: Number of extra lines to repeat from bottom
- */
-struct dpu_drm_pix_ext_v1 {
- /*
- * Number of pixels ext in left, right, top and bottom direction
- * for all color components.
- */
- int32_t num_ext_pxls_lr[DPU_MAX_PLANES];
- int32_t num_ext_pxls_tb[DPU_MAX_PLANES];
-
- /*
- * Number of pixels needs to be overfetched in left, right, top
- * and bottom directions from source image for scaling.
- */
- int32_t left_ftch[DPU_MAX_PLANES];
- int32_t right_ftch[DPU_MAX_PLANES];
- int32_t top_ftch[DPU_MAX_PLANES];
- int32_t btm_ftch[DPU_MAX_PLANES];
- /*
- * Number of pixels needs to be repeated in left, right, top and
- * bottom directions for scaling.
- */
- int32_t left_rpt[DPU_MAX_PLANES];
- int32_t right_rpt[DPU_MAX_PLANES];
- int32_t top_rpt[DPU_MAX_PLANES];
- int32_t btm_rpt[DPU_MAX_PLANES];
-
-};
-
-/**
- * struct dpu_drm_scaler_v1 - version 1 of struct dpu_drm_scaler
- * @lr: Pixel extension settings for left/right
- * @tb: Pixel extension settings for top/botton
- * @init_phase_x: Initial scaler phase values for x
- * @phase_step_x: Phase step values for x
- * @init_phase_y: Initial scaler phase values for y
- * @phase_step_y: Phase step values for y
- * @horz_filter: Horizontal filter array
- * @vert_filter: Vertical filter array
- */
-struct dpu_drm_scaler_v1 {
- /*
- * Pix ext settings
- */
- struct dpu_drm_pix_ext_v1 pe;
- /*
- * Phase settings
- */
- int32_t init_phase_x[DPU_MAX_PLANES];
- int32_t phase_step_x[DPU_MAX_PLANES];
- int32_t init_phase_y[DPU_MAX_PLANES];
- int32_t phase_step_y[DPU_MAX_PLANES];
-
- /*
- * Filter type to be used for scaling in horizontal and vertical
- * directions
- */
- uint32_t horz_filter[DPU_MAX_PLANES];
- uint32_t vert_filter[DPU_MAX_PLANES];
-};
-
-/**
- * struct dpu_drm_de_v1 - version 1 of detail enhancer structure
- * @enable: Enables/disables detail enhancer
- * @sharpen_level1: Sharpening strength for noise
- * @sharpen_level2: Sharpening strength for context
- * @clip: Clip coefficient
- * @limit: Detail enhancer limit factor
- * @thr_quiet: Quite zone threshold
- * @thr_dieout: Die-out zone threshold
- * @thr_low: Linear zone left threshold
- * @thr_high: Linear zone right threshold
- * @prec_shift: Detail enhancer precision
- * @adjust_a: Mapping curves A coefficients
- * @adjust_b: Mapping curves B coefficients
- * @adjust_c: Mapping curves C coefficients
- */
-struct dpu_drm_de_v1 {
- uint32_t enable;
- int16_t sharpen_level1;
- int16_t sharpen_level2;
- uint16_t clip;
- uint16_t limit;
- uint16_t thr_quiet;
- uint16_t thr_dieout;
- uint16_t thr_low;
- uint16_t thr_high;
- uint16_t prec_shift;
- int16_t adjust_a[DPU_MAX_DE_CURVES];
- int16_t adjust_b[DPU_MAX_DE_CURVES];
- int16_t adjust_c[DPU_MAX_DE_CURVES];
-};
-
-/**
- * struct dpu_drm_scaler_v2 - version 2 of struct dpu_drm_scaler
- * @enable: Scaler enable
- * @dir_en: Detail enhancer enable
- * @pe: Pixel extension settings
- * @horz_decimate: Horizontal decimation factor
- * @vert_decimate: Vertical decimation factor
- * @init_phase_x: Initial scaler phase values for x
- * @phase_step_x: Phase step values for x
- * @init_phase_y: Initial scaler phase values for y
- * @phase_step_y: Phase step values for y
- * @preload_x: Horizontal preload value
- * @preload_y: Vertical preload value
- * @src_width: Source width
- * @src_height: Source height
- * @dst_width: Destination width
- * @dst_height: Destination height
- * @y_rgb_filter_cfg: Y/RGB plane filter configuration
- * @uv_filter_cfg: UV plane filter configuration
- * @alpha_filter_cfg: Alpha filter configuration
- * @blend_cfg: Selection of blend coefficients
- * @lut_flag: LUT configuration flags
- * @dir_lut_idx: 2d 4x4 LUT index
- * @y_rgb_cir_lut_idx: Y/RGB circular LUT index
- * @uv_cir_lut_idx: UV circular LUT index
- * @y_rgb_sep_lut_idx: Y/RGB separable LUT index
- * @uv_sep_lut_idx: UV separable LUT index
- * @de: Detail enhancer settings
- */
-struct dpu_drm_scaler_v2 {
- /*
- * General definitions
- */
- uint32_t enable;
- uint32_t dir_en;
-
- /*
- * Pix ext settings
- */
- struct dpu_drm_pix_ext_v1 pe;
-
- /*
- * Decimation settings
- */
- uint32_t horz_decimate;
- uint32_t vert_decimate;
-
- /*
- * Phase settings
- */
- int32_t init_phase_x[DPU_MAX_PLANES];
- int32_t phase_step_x[DPU_MAX_PLANES];
- int32_t init_phase_y[DPU_MAX_PLANES];
- int32_t phase_step_y[DPU_MAX_PLANES];
-
- uint32_t preload_x[DPU_MAX_PLANES];
- uint32_t preload_y[DPU_MAX_PLANES];
- uint32_t src_width[DPU_MAX_PLANES];
- uint32_t src_height[DPU_MAX_PLANES];
-
- uint32_t dst_width;
- uint32_t dst_height;
-
- uint32_t y_rgb_filter_cfg;
- uint32_t uv_filter_cfg;
- uint32_t alpha_filter_cfg;
- uint32_t blend_cfg;
-
- uint32_t lut_flag;
- uint32_t dir_lut_idx;
-
- /* for Y(RGB) and UV planes*/
- uint32_t y_rgb_cir_lut_idx;
- uint32_t uv_cir_lut_idx;
- uint32_t y_rgb_sep_lut_idx;
- uint32_t uv_sep_lut_idx;
-
- /*
- * Detail enhancer settings
- */
- struct dpu_drm_de_v1 de;
-};
-
/* Number of dest scalers supported */
#define DPU_MAX_DS_COUNT 2

diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index 404f201..60b1a30 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -26,7 +26,6 @@
#define __MSM_DRM_H__

#include "drm.h"
-#include "dpu_drm.h"

#if defined(__cplusplus)
extern "C" {