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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: dcastagna@chromium.org, emil.l.velikov@gmail.com,
	Uma Shankar <uma.shankar@intel.com>,
	seanpaul@chromium.org, ville.syrjala@intel.com,
	maarten.lankhorst@intel.com
Subject: [v2 4/7] drm/i915/icl: Add register definitions for Multi Segmented gamma
Date: Mon,  1 Apr 2019 23:00:08 +0530	[thread overview]
Message-ID: <1554139811-13280-5-git-send-email-uma.shankar@intel.com> (raw)
In-Reply-To: <1554139811-13280-1-git-send-email-uma.shankar@intel.com>

Add macros to define multi segmented gamma registers

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 341f03e..f95f82f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7218,6 +7218,7 @@ enum {
 #define  GAMMA_MODE_MODE_10BIT	(1 << 0)
 #define  GAMMA_MODE_MODE_12BIT	(2 << 0)
 #define  GAMMA_MODE_MODE_SPLIT	(3 << 0)
+#define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED	(3 << 0)
 
 /* DMC/CSR */
 #define CSR_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
@@ -10157,6 +10158,22 @@ enum skl_power_gate {
 #define PRE_CSC_GAMC_INDEX(pipe)	_MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
 #define PRE_CSC_GAMC_DATA(pipe)		_MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
 
+/* Add registers for Gen11 Multi Segmented Gamma Mode */
+#define _PAL_PREC_MULTI_SEG_INDEX_A	0x4A408
+#define _PAL_PREC_MULTI_SEG_INDEX_B	0x4AC08
+#define  PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT		BIT(15)
+#define  PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK	(0x1f << 0)
+
+#define _PAL_PREC_MULTI_SEG_DATA_A	0x4A40C
+#define _PAL_PREC_MULTI_SEG_DATA_B	0x4AC0C
+
+#define PREC_PAL_MULTI_SEG_INDEX(pipe)	_MMIO_PIPE(pipe, \
+					_PAL_PREC_MULTI_SEG_INDEX_A, \
+					_PAL_PREC_MULTI_SEG_INDEX_B)
+#define PREC_PAL_MULTI_SEG_DATA(pipe)	_MMIO_PIPE(pipe, \
+					_PAL_PREC_MULTI_SEG_DATA_A, \
+					_PAL_PREC_MULTI_SEG_DATA_B)
+
 /* pipe CSC & degamma/gamma LUTs on CHV */
 #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)
 #define _CGM_PIPE_A_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x67904)
-- 
1.9.1

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  parent reply	other threads:[~2019-04-01 17:30 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-01 17:30 [v2 0/7] Add Multi Segment Gamma Support Uma Shankar
2019-04-01 17:30 ` [v2 1/7] drm: Add gamma mode caps property Uma Shankar
2019-04-01 18:33   ` Sam Ravnborg
2019-04-08 14:45     ` Shankar, Uma
2019-04-01 17:30 ` [v2 2/7] drm/i915: Define color lut range structure Uma Shankar
2019-04-08 10:09   ` Ville Syrjälä
2019-04-08 12:28     ` Shankar, Uma
2019-04-01 17:30 ` [v2 3/7] drm: Add gamma mode property Uma Shankar
2019-04-01 18:37   ` Sam Ravnborg
2019-04-08 14:49     ` Shankar, Uma
2019-04-01 17:30 ` Uma Shankar [this message]
2019-04-01 17:30 ` [v2 5/7] drm/i915/icl: Add support for multi segmented gamma mode Uma Shankar
2019-04-08 10:19   ` Ville Syrjälä
2019-04-08 12:51     ` Shankar, Uma
2019-04-01 17:30 ` [v2 6/7] drm/i915: Add gamma mode caps property Uma Shankar
2019-04-01 17:30 ` [v2 7/7] drm/i915: Attach gamma mode property Uma Shankar
2019-04-05 16:12 ` [Intel-gfx] [v2 0/7] Add Multi Segment Gamma Support Ville Syrjälä
2019-04-08 12:26   ` Shankar, Uma
2019-04-08 12:31     ` Ville Syrjälä
2019-04-08 14:40       ` Shankar, Uma
2019-04-08 14:57         ` [Intel-gfx] " Ville Syrjälä
2019-04-08 15:40           ` Shankar, Uma
2019-04-08 15:45             ` Ville Syrjälä
2019-04-08 15:59               ` Shankar, Uma
2019-04-08 16:07                 ` [Intel-gfx] " Ville Syrjälä
2019-04-10 13:20                   ` Shankar, Uma
2019-04-10 15:38                     ` Ville Syrjälä
2019-04-11  7:59                       ` [Intel-gfx] " Shankar, Uma

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