From: CK Hu <ck.hu@mediatek.com>
To: wangyan wang <wangyan.wang@mediatek.com>
Cc: Ryder Lee <ryder.lee@mediatek.com>,
srv_heupstream@mediatek.com,
chunhui dai <chunhui.dai@mediatek.com>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Sean Wang <sean.wang@mediatek.com>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
David Airlie <airlied@linux.ie>,
linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
Colin Ian King <colin.king@canonical.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V8 5/5] drm/mediatek: make implementation of recalc_rate() to match the definition
Date: Mon, 8 Apr 2019 12:48:31 +0800 [thread overview]
Message-ID: <1554698911.25248.5.camel@mtksdaap41> (raw)
In-Reply-To: <20190402093605.82004-6-wangyan.wang@mediatek.com>
Hi, Wangyan:
On Tue, 2019-04-02 at 17:36 +0800, wangyan wang wrote:
> From: Wangyan Wang <wangyan.wang@mediatek.com>
>
> Recalculate the rate of this clock, by querying hardware to
> make implementation of recalc_rate() to match the definition.
>
> Signed-off-by: Wangyan Wang <wangyan.wang@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 8 ------
> drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 2 --
> drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 39 +++++++++++++++++++++++---
> drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 8 ++++++
> 4 files changed, 43 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> index fe05aa762107..f753ee72971e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> @@ -15,14 +15,6 @@ static const struct phy_ops mtk_hdmi_phy_dev_ops = {
> .owner = THIS_MODULE,
> };
>
> -unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> - unsigned long parent_rate)
> -{
> - struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
> -
> - return hdmi_phy->pll_rate;
> -}
> -
> void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
> u32 bits)
> {
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
> index 86895be0d192..2d8b3182470d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
> @@ -49,8 +49,6 @@ void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
> void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
> u32 val, u32 mask);
> struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
> -unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> - unsigned long parent_rate);
>
> extern struct platform_driver mtk_hdmi_phy_driver;
> extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> index 5f8c2b044034..3bb72ae6a7b5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> @@ -79,7 +79,6 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
> mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
> usleep_range(80, 100);
> mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
> - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
> mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
> mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
> mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
> @@ -94,7 +93,6 @@ static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
> mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
> mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
> mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
> - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
> mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
> usleep_range(80, 100);
> mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
> @@ -123,6 +121,7 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
>
> mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK);
> mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
> + mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
> mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
> RG_HTPLL_IC_MASK);
> mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
> @@ -160,6 +159,40 @@ static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> return rate;
> }
>
> +static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
Align the first character to the right of '('.
Regards,
CK
> +{
> + struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
> + unsigned long out_rate, val;
> +
> + val = (readl(hdmi_phy->regs + HDMI_CON6)
> + & RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV;
> + switch (val) {
> + case 0x00:
> + out_rate = parent_rate;
> + break;
> + case 0x01:
> + out_rate = parent_rate / 2;
> + break;
> + default:
> + out_rate = parent_rate / 4;
> + break;
> + }
> +
> + val = (readl(hdmi_phy->regs + HDMI_CON6)
> + & RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV;
> + out_rate *= (val + 1) * 2;
> + val = (readl(hdmi_phy->regs + HDMI_CON2)
> + & RG_HDMITX_TX_POSDIV_MASK);
> +
> + out_rate >>= (val >> RG_HDMITX_TX_POSDIV);
> +
> + if (readl(hdmi_phy->regs + HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV)
> + out_rate = out_rate / 5;
> +
> + return out_rate;
> +}
> +
> static const struct clk_ops mtk_hdmi_phy_pll_ops = {
> .prepare = mtk_hdmi_pll_prepare,
> .unprepare = mtk_hdmi_pll_unprepare,
> @@ -180,7 +213,6 @@ static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
> mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
> usleep_range(80, 100);
> mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
> - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
> mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
> mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
> mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
> @@ -192,7 +224,6 @@ static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
> mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
> mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
> mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
> - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
> mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
> usleep_range(80, 100);
> mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> index 472d2fda0a03..3a339f516613 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> @@ -299,6 +299,14 @@ static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> return rate;
> }
>
> +static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
> +
> + return hdmi_phy->pll_rate;
> +}
> +
> static const struct clk_ops mtk_hdmi_phy_pll_ops = {
> .prepare = mtk_hdmi_pll_prepare,
> .unprepare = mtk_hdmi_pll_unprepare,
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prev parent reply other threads:[~2019-04-08 4:48 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-02 9:36 [PATCH V8 0/5] make mt7623 clock of hdmi stable wangyan wang
2019-04-02 9:36 ` [PATCH V8 1/5] drm/mediatek: remove flag CLK_SET_RATE_PARENT for mt2701 hdmi phy to not propagate rate change to parent wangyan wang
2019-04-08 3:53 ` CK Hu
2019-04-02 9:36 ` [PATCH V8 2/5] drm/mediatek: fix the rate and divder of hdmi phy for MT2701 wangyan wang
2019-04-02 9:36 ` [PATCH V8 3/5] drm/mediatek: using new factor for tvdpll in MT2701 wangyan wang
2019-04-08 3:54 ` CK Hu
2019-04-02 9:36 ` [PATCH V8 4/5] drm/mediatek: no change parent rate in round_rate() for mt2701 hdmi phy wangyan wang
2019-04-08 3:57 ` CK Hu
2019-04-02 9:36 ` [PATCH V8 5/5] drm/mediatek: make implementation of recalc_rate() to match the definition wangyan wang
2019-04-08 4:48 ` CK Hu [this message]
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