[v3 4/7] drm/i915/icl: Add support for multi segmented gamma mode

[Uma Shankar <uma.shankar@intel.com>]

Gen11 introduced a new gamma mode i.e, multi segmented
gamma mode. Added support for the same.

v2: Aligned to just 1 property interface as suggested by
Ville. Fixed Ville's review comments.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/intel_color.c | 166 ++++++++++++++++++++++++++++++++++++-
 include/drm/drm_crtc.h             |   3 +
 2 files changed, 165 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index c433215..d4ce1ed 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -58,6 +58,12 @@
 
 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
 
+#define LEGACY_PALETTE_MODE_8BIT               BIT(0)
+#define PRECISION_PALETTE_MODE_10BIT           BIT(1)
+#define INTERPOLATED_GAMMA_MODE_12BIT          BIT(2)
+#define MULTI_SEGMENTED_GAMMA_MODE_12BIT       BIT(3)
+#define SPLIT_GAMMA_MODE_12BIT                 BIT(4)
+
 static const u16 ilk_csc_off_zero[3] = {};
 
 static const u16 ilk_csc_coeff_identity[9] = {
@@ -93,6 +99,22 @@
 	0x0800, 0x0100, 0x0800,
 };
 
+/* ilk+ "12.4" interpolated format (high 10 bits) */
+static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
+{
+	return (color->red >> 6) << 20 |
+		(color->green >> 6) << 10 |
+		(color->blue >> 6);
+}
+
+/* ilk+ "12.4" interpolated format (low 6 bits) */
+static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
+{
+	return (color->red & 0x3f) << 24 |
+		(color->green & 0x3f) << 14 |
+		(color->blue & 0x3f);
+}
+
 static bool lut_is_legacy(const struct drm_property_blob *lut)
 {
 	return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
@@ -781,6 +803,118 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 	}
 }
 
+static void icl_program_coarse_segment_lut(const struct intel_crtc_state
+					   *crtc_state,
+					   struct drm_color_lut *gamma_lut,
+					   u32 offset)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_color_lut *lut = gamma_lut;
+	enum pipe pipe = crtc->pipe;
+	u32 i, lut_size, word;
+
+	WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
+
+	I915_WRITE(PREC_PAL_INDEX(pipe),
+		   (offset ? PAL_PREC_SPLIT_MODE : 0) |
+		   PAL_PREC_AUTO_INCREMENT |
+		   offset);
+
+	if (lut && crtc_state->base.gamma_mode_type ==
+				MULTI_SEGMENTED_GAMMA_MODE_12BIT) {
+		lut_size = 9 + 514;
+		for (i = 9; i < lut_size; i++) {
+			/* For Even Index */
+			word = ilk_lut_12p4_udw(&lut[i]);
+
+			I915_WRITE(PREC_PAL_DATA(pipe), word);
+
+			/* For ODD index */
+			word = ilk_lut_12p4_ldw(&lut[i]);
+
+			I915_WRITE(PREC_PAL_DATA(pipe), word);
+		}
+	}
+
+	/*
+	 * Program the max register to clamp values > 1.0.
+	 * ToDo: Extend the ABI to be able to program values
+	 * from 1.0
+	 */
+	I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16));
+	I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16));
+	I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16));
+
+	/*
+	 * Program the max register to clamp values > 1.0.
+	 * ToDo: Extend the ABI to be able to program values
+	 * from 1.0 to 3.0
+	 */
+	I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16));
+	I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16));
+	I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16));
+
+	/*
+	 * Program the gc max 2 register to clamp values > 1.0.
+	 * ToDo: Extend the ABI to be able to program values
+	 * from 3.0 to 7.0
+	 */
+	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+		I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), (1 << 16));
+		I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), (1 << 16));
+		I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), (1 << 16));
+	}
+}
+
+static void icl_program_fine_segment_lut(const struct intel_crtc_state
+					 *crtc_state,
+					 struct drm_color_lut *gamma_lut,
+					 u32 offset)
+{
+	struct drm_crtc *crtc = crtc_state->base.crtc;
+	struct drm_device *dev = crtc_state->base.crtc->dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	u32 i, word, lut_size = 9;
+
+	WARN_ON(offset & ~PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK);
+
+	I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe),
+		   (PAL_PREC_AUTO_INCREMENT | offset));
+
+	if (gamma_lut) {
+		struct drm_color_lut *lut =
+			(struct drm_color_lut *)gamma_lut;
+
+		for (i = 0; i < lut_size; i++) {
+			/* For Even Index */
+			word = ilk_lut_12p4_udw(&lut[i]);
+
+			I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe), word);
+
+			/* For ODD index */
+			word = ilk_lut_12p4_ldw(&lut[i]);
+
+			I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe), word);
+		}
+	}
+}
+
+static void icl_load_gamma_multi_segmented_lut(const struct intel_crtc_state
+					       *crtc_state, u32 offset)
+{
+	const struct drm_property_blob *gamma_lut_blob =
+					crtc_state->base.gamma_lut;
+	struct drm_color_lut *gamma_lut = NULL;
+
+	if (gamma_lut_blob)
+		gamma_lut = gamma_lut_blob->data;
+
+	icl_program_fine_segment_lut(crtc_state, gamma_lut, 0);
+	icl_program_coarse_segment_lut(crtc_state, gamma_lut, 0);
+}
+
 static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
@@ -792,6 +926,9 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 	if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
 	    GAMMA_MODE_MODE_8BIT) {
 		i9xx_load_luts(crtc_state);
+	} else if (crtc_state->base.gamma_mode_type ==
+		   MULTI_SEGMENTED_GAMMA_MODE_12BIT) {
+		icl_load_gamma_multi_segmented_lut(crtc_state, 0);
 	} else {
 		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_10_max(crtc);
@@ -1186,10 +1323,28 @@ static int glk_color_check(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
-static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
+static u32 icl_gamma_mode(struct intel_crtc_state *crtc_state)
 {
+	struct drm_device *dev = crtc_state->base.crtc->dev;
+	struct drm_mode_config *config = &dev->mode_config;
+	struct drm_property *property = config->gamma_mode_property;
+	struct drm_property_enum *prop_enum;
+	u32 index = 0;
 	u32 gamma_mode = 0;
 
+	list_for_each_entry(prop_enum, &property->enum_list, head) {
+		if (prop_enum->value == crtc_state->base.gamma_mode) {
+			if (!strcmp(prop_enum->name,
+			    "multi-segmented gamma")) {
+				crtc_state->base.gamma_mode_type =
+				MULTI_SEGMENTED_GAMMA_MODE_12BIT;
+				DRM_INFO("multi-segment enabled\n");
+			}
+			break;
+		}
+		index++;
+	}
+
 	if (crtc_state->base.degamma_lut)
 		gamma_mode |= PRE_CSC_GAMMA_ENABLE;
 
@@ -1200,6 +1355,9 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
 	if (!crtc_state->base.gamma_lut ||
 	    crtc_state_is_legacy_gamma(crtc_state))
 		gamma_mode |= GAMMA_MODE_MODE_8BIT;
+	else if (crtc_state->base.gamma_mode_type ==
+		 MULTI_SEGMENTED_GAMMA_MODE_12BIT)
+		gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
 	else
 		gamma_mode |= GAMMA_MODE_MODE_10BIT;
 
@@ -1755,7 +1913,7 @@ void intel_color_init(struct intel_crtc *crtc)
 
 			drm_color_add_gamma_mode_range(&dev_priv->drm,
 						       "8bit gamma",
-						       	i9xx_gamma_8,
+							i9xx_gamma_8,
 							sizeof(i9xx_gamma_8));
 			drm_color_add_gamma_mode_range(&dev_priv->drm,
 						       "10bit gamma",
@@ -1798,8 +1956,8 @@ void intel_color_init(struct intel_crtc *crtc)
 
 			drm_color_add_gamma_mode_range(&dev_priv->drm,
 						       "8bit gamma or degamma",
-						       	ilk_gamma_degamma_8,
-							sizeof(ilk_gamma_degamma_8));
+						       ilk_gamma_degamma_8,
+						       sizeof(ilk_gamma_degamma_8));
 			drm_color_add_gamma_mode_range(&dev_priv->drm,
 						       "10bit gamma or degamma",
 						       ilk_gamma_degamma_10,
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index f2e60bd..f789359 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -255,6 +255,9 @@ struct drm_crtc_state {
 	 */
 	u32 gamma_mode;
 
+	/* Gamma mode type programmed on the pipe */
+	u32 gamma_mode_type;
+
 	/**
 	 * @degamma_lut:
 	 *
-- 
1.9.1

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