From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kalyan Thota Subject: [PATCH v2] msm:disp:dpu1: add support for display for SC7180 target Date: Wed, 20 Nov 2019 16:23:43 +0530 Message-ID: <1574247223-17381-1-git-send-email-kalyan_t@codeaurora.org> Return-path: Sender: linux-kernel-owner@vger.kernel.org To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Kalyan Thota , linux-kernel@vger.kernel.org, robdclark@gmail.com, seanpaul@chromium.org, hoegsberg@chromium.org, dhar@codeaurora.org, jsanka@codeaurora.org, chandanu@codeaurora.org, travitej@codeaurora.org, nganji@codeaurora.org List-Id: dri-devel@lists.freedesktop.org Add display hw catalog changes for SC7180 target. Changes in v1: - Configure register offsets and capabilities for the display hw blocks. Changes in v2: - mdss_irq data type has changed in the dependent patch, accomodate the necessary changes. - Add co-developed-by tags in the commit msg (Stephen Boyd). This patch has dependency on the below series https://patchwork.kernel.org/patch/11251761/ Co-developed-by: Shubhashree Dhar Signed-off-by: Shubhashree Dhar Co-developed-by: Raviteja Tamatam Signed-off-by: Raviteja Tamatam Signed-off-by: Kalyan Thota --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 189 +++++++++++++++++++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_drv.c | 4 +- 5 files changed, 187 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 88f2664..1cf4509 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -11,11 +11,17 @@ #include "dpu_hw_catalog_format.h" #include "dpu_kms.h" -#define VIG_SDM845_MASK \ - (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_SCALER_QSEED3) | BIT(DPU_SSPP_QOS) |\ +#define VIG_MASK \ + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_QOS_8LVL) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) +#define VIG_SDM845_MASK \ + (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3)) + +#define VIG_SC7180_MASK \ + (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED4)) + #define DMA_SDM845_MASK \ (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ @@ -27,6 +33,9 @@ #define MIXER_SDM845_MASK \ (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) +#define MIXER_SC7180_MASK \ + (BIT(DPU_DIM_LAYER)) + #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER) #define PINGPONG_SDM845_SPLIT_MASK \ @@ -60,6 +69,16 @@ .has_idle_pc = true, }; +static const struct dpu_caps sc7180_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0x9, + .qseed_type = DPU_SSPP_SCALER_QSEED4, + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, + .ubwc_version = DPU_HW_UBWC_VER_20, + .has_dim_layer = true, + .has_idle_pc = true, +}; + static struct dpu_mdp_cfg sdm845_mdp[] = { { .name = "top_0", .id = MDP_TOP, @@ -85,6 +104,23 @@ }, }; +static struct dpu_mdp_cfg sc7180_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x494, + .features = 0, + .highest_bank_bit = 0x3, + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { + .reg_off = 0x2AC, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { + .reg_off = 0x2AC, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { + .reg_off = 0x2B4, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { + .reg_off = 0x2BC, .bit_off = 8}, + }, +}; + /************************************************************* * CTL sub blocks config *************************************************************/ @@ -116,6 +152,24 @@ }, }; +static struct dpu_ctl_cfg sc7180_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0xE4, + .features = BIT(DPU_CTL_ACTIVE_CFG) + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0xE4, + .features = BIT(DPU_CTL_ACTIVE_CFG) + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0xE4, + .features = BIT(DPU_CTL_ACTIVE_CFG) + }, +}; + /************************************************************* * SSPP sub blocks config *************************************************************/ @@ -203,9 +257,23 @@ sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), }; +static struct dpu_sspp_cfg sc7180_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, + sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), +}; + /************************************************************* * MIXER sub blocks config *************************************************************/ + +/* SDM845 */ + static const struct dpu_lm_sub_blks sdm845_lm_sblk = { .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .maxblendstages = 11, /* excluding base layer */ @@ -215,23 +283,46 @@ }, }; -#define LM_BLK(_name, _id, _base, _pp, _lmpair) \ +#define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair) \ { \ .name = _name, .id = _id, \ .base = _base, .len = 0x320, \ - .features = MIXER_SDM845_MASK, \ - .sblk = &sdm845_lm_sblk, \ + .features = _fmask, \ + .sblk = _sblk, \ .pingpong = _pp, \ .lm_pair_mask = (1 << _lmpair) \ } static struct dpu_lm_cfg sdm845_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, PINGPONG_0, LM_1), - LM_BLK("lm_1", LM_1, 0x45000, PINGPONG_1, LM_0), - LM_BLK("lm_2", LM_2, 0x46000, PINGPONG_2, LM_5), - LM_BLK("lm_3", LM_3, 0x0, PINGPONG_MAX, 0), - LM_BLK("lm_4", LM_4, 0x0, PINGPONG_MAX, 0), - LM_BLK("lm_5", LM_5, 0x49000, PINGPONG_3, LM_2), + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_0, LM_1), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_1, LM_0), + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_2, LM_5), + LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_MAX, 0), + LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_MAX, 0), + LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_3, LM_2), +}; + +/* SC7180 */ + +static const struct dpu_lm_sub_blks sc7180_lm_sblk = { + .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .maxblendstages = 7, /* excluding base layer */ + .blendstage_base = { /* offsets relative to mixer base */ + 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 + }, +}; + +static struct dpu_lm_cfg sc7180_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK, + &sc7180_lm_sblk, PINGPONG_0, LM_1), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SC7180_MASK, + &sc7180_lm_sblk, PINGPONG_1, LM_0), }; /************************************************************* @@ -271,6 +362,11 @@ PP_BLK("pingpong_3", PINGPONG_3, 0x71800), }; +static struct dpu_pingpong_cfg sc7180_pp[] = { + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800), +}; + /************************************************************* * INTF sub blocks config *************************************************************/ @@ -290,6 +386,11 @@ INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1), }; +static struct dpu_intf_cfg sc7180_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0), + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0), +}; + /************************************************************* * VBIF sub blocks config *************************************************************/ @@ -340,6 +441,10 @@ {.fl = 0, .lut = 0x11222222223357} }; +static struct dpu_qos_lut_entry sc7180_qos_linear[] = { + {.fl = 0, .lut = 0x0011222222335777}, +}; + static struct dpu_qos_lut_entry sdm845_qos_macrotile[] = { {.fl = 10, .lut = 0x344556677}, {.fl = 11, .lut = 0x3344556677}, @@ -349,10 +454,18 @@ {.fl = 0, .lut = 0x112233344556677}, }; +static struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { + {.fl = 0, .lut = 0x0011223344556677}, +}; + static struct dpu_qos_lut_entry sdm845_qos_nrt[] = { {.fl = 0, .lut = 0x0}, }; +static struct dpu_qos_lut_entry sc7180_qos_nrt[] = { + {.fl = 0, .lut = 0x0}, +}; + static struct dpu_perf_cfg sdm845_perf_data = { .max_bw_low = 6800000, .max_bw_high = 6800000, @@ -392,6 +505,30 @@ }, }; +static struct dpu_perf_cfg sc7180_perf_data = { + .max_bw_low = 3900000, + .max_bw_high = 5500000, + .min_core_ib = 2400000, + .min_llcc_ib = 800000, + .min_dram_ib = 800000, + .danger_lut_tbl = {0xff, 0xffff, 0x0}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, +}; + /************************************************************* * Hardware catalog init *************************************************************/ @@ -425,9 +562,39 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg) }; } +/* + * sc7180_cfg_init(): populate sc7180 dpu sub-blocks reg offsets + * and instance counts. + */ +static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg) +{ + *dpu_cfg = (struct dpu_mdss_cfg){ + .caps = &sc7180_dpu_caps, + .mdp_count = ARRAY_SIZE(sc7180_mdp), + .mdp = sc7180_mdp, + .ctl_count = ARRAY_SIZE(sc7180_ctl), + .ctl = sc7180_ctl, + .sspp_count = ARRAY_SIZE(sc7180_sspp), + .sspp = sc7180_sspp, + .mixer_count = ARRAY_SIZE(sc7180_lm), + .mixer = sc7180_lm, + .pingpong_count = ARRAY_SIZE(sc7180_pp), + .pingpong = sc7180_pp, + .intf_count = ARRAY_SIZE(sc7180_intf), + .intf = sc7180_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = sdm845_regdma, + .perf = sc7180_perf_data, + .mdss_irqs = 0x3f, + }; +} + static struct dpu_mdss_hw_cfg_handler cfg_handler[] = { { .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init}, { .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init}, + { .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init}, }; void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 0fd3f50..2607ef3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -38,6 +38,7 @@ #define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */ #define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */ #define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sdm855 v1.0 */ +#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) @@ -45,6 +46,7 @@ #define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400) #define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410) #define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500) +#define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620) #define DPU_HW_BLK_NAME_LEN 16 @@ -110,6 +112,7 @@ enum { DPU_SSPP_SRC = 0x1, DPU_SSPP_SCALER_QSEED2, DPU_SSPP_SCALER_QSEED3, + DPU_SSPP_SCALER_QSEED4, DPU_SSPP_SCALER_RGB, DPU_SSPP_CSC, DPU_SSPP_CSC_10BIT, @@ -166,6 +169,7 @@ enum { */ enum { DPU_CTL_SPLIT_DISPLAY = 0x1, + DPU_CTL_ACTIVE_CFG, DPU_CTL_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 5bc39ba..d0cb1d8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -152,7 +152,7 @@ static void _setup_mixer_ops(struct dpu_mdss_cfg *m, unsigned long features) { ops->setup_mixer_out = dpu_hw_lm_setup_out; - if (IS_SDM845_TARGET(m->hwversion) || IS_SDM670_TARGET(m->hwversion)) + if (IS_SDM845_TARGET(m->hwversion) || IS_SDM670_TARGET(m->hwversion) || IS_SC7180_TARGET(m->hwversion)) ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845; else ops->setup_blend_config = dpu_hw_lm_setup_blend_config; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 58b0485..ee93ba3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1111,6 +1111,7 @@ static int __maybe_unused dpu_runtime_resume(struct device *dev) static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,sdm845-dpu", }, + { .compatible = "qcom,sc7180-dpu", }, {} }; MODULE_DEVICE_TABLE(of, dpu_dt_match); diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index c84f0a8..f50fefb 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -1192,7 +1192,8 @@ static int add_display_components(struct device *dev, * the interfaces to our components list. */ if (of_device_is_compatible(dev->of_node, "qcom,mdss") || - of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) { + of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss") || + of_device_is_compatible(dev->of_node, "qcom,sc7180-mdss")) { ret = of_platform_populate(dev->of_node, NULL, NULL, dev); if (ret) { DRM_DEV_ERROR(dev, "failed to populate children devices\n"); @@ -1317,6 +1318,7 @@ static int msm_pdev_remove(struct platform_device *pdev) { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 }, { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 }, { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU }, + { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU }, {} }; MODULE_DEVICE_TABLE(of, dt_match); -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: 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2019 16:23:47 +0530 Received: by kalyant-linux.qualcomm.com (Postfix, from userid 94428) id A5AF242F7; Wed, 20 Nov 2019 16:23:46 +0530 (IST) From: Kalyan Thota To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2] msm:disp:dpu1: add support for display for SC7180 target Date: Wed, 20 Nov 2019 16:23:43 +0530 Message-Id: <1574247223-17381-1-git-send-email-kalyan_t@codeaurora.org> X-Mailer: git-send-email 1.9.1 X-Mailman-Approved-At: Thu, 21 Nov 2019 07:59:20 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dhar@codeaurora.org, travitej@codeaurora.org, linux-kernel@vger.kernel.org, seanpaul@chromium.org, Kalyan Thota , hoegsberg@chromium.org, chandanu@codeaurora.org MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Message-ID: <20191120105343.14I3MjQ5-u8QUhU77UoNKEYQCBwW6qBwnC0EgX9RFOs@z> QWRkIGRpc3BsYXkgaHcgY2F0YWxvZyBjaGFuZ2VzIGZvciBTQzcxODAgdGFyZ2V0LgoKQ2hhbmdl cyBpbiB2MToKIC0gQ29uZmlndXJlIHJlZ2lzdGVyIG9mZnNldHMgYW5kIGNhcGFiaWxpdGllcyBm b3IgdGhlCiAgIGRpc3BsYXkgaHcgYmxvY2tzLgoKQ2hhbmdlcyBpbiB2MjoKIC0gbWRzc19pcnEg ZGF0YSB0eXBlIGhhcyBjaGFuZ2VkIGluIHRoZSBkZXBlbmRlbnQKICAgcGF0Y2gsIGFjY29tb2Rh dGUgdGhlIG5lY2Vzc2FyeSBjaGFuZ2VzLgogLSBBZGQgY28tZGV2ZWxvcGVkLWJ5IHRhZ3MgaW4g dGhlIGNvbW1pdCBtc2cgKFN0ZXBoZW4gQm95ZCkuCgpUaGlzIHBhdGNoIGhhcyBkZXBlbmRlbmN5 IG9uIHRoZSBiZWxvdyBzZXJpZXMKCmh0dHBzOi8vcGF0Y2h3b3JrLmtlcm5lbC5vcmcvcGF0Y2gv MTEyNTE3NjEvCgpDby1kZXZlbG9wZWQtYnk6IFNodWJoYXNocmVlIERoYXIgPGRoYXJAY29kZWF1 cm9yYS5vcmc+ClNpZ25lZC1vZmYtYnk6IFNodWJoYXNocmVlIERoYXIgPGRoYXJAY29kZWF1cm9y YS5vcmc+CkNvLWRldmVsb3BlZC1ieTogUmF2aXRlamEgVGFtYXRhbSA8dHJhdml0ZWpAY29kZWF1 cm9yYS5vcmc+ClNpZ25lZC1vZmYtYnk6IFJhdml0ZWphIFRhbWF0YW0gPHRyYXZpdGVqQGNvZGVh dXJvcmEub3JnPgpTaWduZWQtb2ZmLWJ5OiBLYWx5YW4gVGhvdGEgPGthbHlhbl90QGNvZGVhdXJv cmEub3JnPgotLS0KIGRyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV9od19jYXRhbG9n LmMgfCAxODkgKysrKysrKysrKysrKysrKysrKysrKystLQogZHJpdmVycy9ncHUvZHJtL21zbS9k aXNwL2RwdTEvZHB1X2h3X2NhdGFsb2cuaCB8ICAgNCArCiBkcml2ZXJzL2dwdS9kcm0vbXNtL2Rp c3AvZHB1MS9kcHVfaHdfbG0uYyAgICAgIHwgICAyICstCiBkcml2ZXJzL2dwdS9kcm0vbXNtL2Rp c3AvZHB1MS9kcHVfa21zLmMgICAgICAgIHwgICAxICsKIGRyaXZlcnMvZ3B1L2RybS9tc20vbXNt X2Rydi5jICAgICAgICAgICAgICAgICAgfCAgIDQgKy0KIDUgZmlsZXMgY2hhbmdlZCwgMTg3IGlu c2VydGlvbnMoKyksIDEzIGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2Ry bS9tc20vZGlzcC9kcHUxL2RwdV9od19jYXRhbG9nLmMgYi9kcml2ZXJzL2dwdS9kcm0vbXNtL2Rp c3AvZHB1MS9kcHVfaHdfY2F0YWxvZy5jCmluZGV4IDg4ZjI2NjQuLjFjZjQ1MDkgMTAwNjQ0Ci0t LSBhL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV9od19jYXRhbG9nLmMKKysrIGIv ZHJpdmVycy9ncHUvZHJtL21zbS9kaXNwL2RwdTEvZHB1X2h3X2NhdGFsb2cuYwpAQCAtMTEsMTEg KzExLDE3IEBACiAjaW5jbHVkZSAiZHB1X2h3X2NhdGFsb2dfZm9ybWF0LmgiCiAjaW5jbHVkZSAi ZHB1X2ttcy5oIgogCi0jZGVmaW5lIFZJR19TRE04NDVfTUFTSyBcCi0JKEJJVChEUFVfU1NQUF9T UkMpIHwgQklUKERQVV9TU1BQX1NDQUxFUl9RU0VFRDMpIHwgQklUKERQVV9TU1BQX1FPUykgfFwK KyNkZWZpbmUgVklHX01BU0sgXAorCShCSVQoRFBVX1NTUFBfU1JDKSB8IEJJVChEUFVfU1NQUF9R T1MpIHxcCiAJQklUKERQVV9TU1BQX0NTQ18xMEJJVCkgfCBCSVQoRFBVX1NTUFBfQ0RQKSB8IEJJ VChEUFVfU1NQUF9RT1NfOExWTCkgfFwKIAlCSVQoRFBVX1NTUFBfVFNfUFJFRklMTCkgfCBCSVQo RFBVX1NTUFBfRVhDTF9SRUNUKSkKIAorI2RlZmluZSBWSUdfU0RNODQ1X01BU0sgXAorCShWSUdf TUFTSyB8IEJJVChEUFVfU1NQUF9TQ0FMRVJfUVNFRUQzKSkKKworI2RlZmluZSBWSUdfU0M3MTgw X01BU0sgXAorCShWSUdfTUFTSyB8IEJJVChEUFVfU1NQUF9TQ0FMRVJfUVNFRUQ0KSkKKwogI2Rl ZmluZSBETUFfU0RNODQ1X01BU0sgXAogCShCSVQoRFBVX1NTUFBfU1JDKSB8IEJJVChEUFVfU1NQ UF9RT1MpIHwgQklUKERQVV9TU1BQX1FPU184TFZMKSB8XAogCUJJVChEUFVfU1NQUF9UU19QUkVG SUxMKSB8IEJJVChEUFVfU1NQUF9UU19QUkVGSUxMX1JFQzEpIHxcCkBAIC0yNyw2ICszMyw5IEBA CiAjZGVmaW5lIE1JWEVSX1NETTg0NV9NQVNLIFwKIAkoQklUKERQVV9NSVhFUl9TT1VSQ0VTUExJ VCkgfCBCSVQoRFBVX0RJTV9MQVlFUikpCiAKKyNkZWZpbmUgTUlYRVJfU0M3MTgwX01BU0sgXAor CShCSVQoRFBVX0RJTV9MQVlFUikpCisKICNkZWZpbmUgUElOR1BPTkdfU0RNODQ1X01BU0sgQklU KERQVV9QSU5HUE9OR19ESVRIRVIpCiAKICNkZWZpbmUgUElOR1BPTkdfU0RNODQ1X1NQTElUX01B U0sgXApAQCAtNjAsNiArNjksMTYgQEAKIAkuaGFzX2lkbGVfcGMgPSB0cnVlLAogfTsKIAorc3Rh dGljIGNvbnN0IHN0cnVjdCBkcHVfY2FwcyBzYzcxODBfZHB1X2NhcHMgPSB7CisJLm1heF9taXhl cl93aWR0aCA9IERFRkFVTFRfRFBVX09VVFBVVF9MSU5FX1dJRFRILAorCS5tYXhfbWl4ZXJfYmxl bmRzdGFnZXMgPSAweDksCisJLnFzZWVkX3R5cGUgPSBEUFVfU1NQUF9TQ0FMRVJfUVNFRUQ0LAor CS5zbWFydF9kbWFfcmV2ID0gRFBVX1NTUFBfU01BUlRfRE1BX1YyLAorCS51YndjX3ZlcnNpb24g PSBEUFVfSFdfVUJXQ19WRVJfMjAsCisJLmhhc19kaW1fbGF5ZXIgPSB0cnVlLAorCS5oYXNfaWRs ZV9wYyA9IHRydWUsCit9OworCiBzdGF0aWMgc3RydWN0IGRwdV9tZHBfY2ZnIHNkbTg0NV9tZHBb XSA9IHsKIAl7CiAJLm5hbWUgPSAidG9wXzAiLCAuaWQgPSBNRFBfVE9QLApAQCAtODUsNiArMTA0 LDIzIEBACiAJfSwKIH07CiAKK3N0YXRpYyBzdHJ1Y3QgZHB1X21kcF9jZmcgc2M3MTgwX21kcFtd ID0geworCXsKKwkubmFtZSA9ICJ0b3BfMCIsIC5pZCA9IE1EUF9UT1AsCisJLmJhc2UgPSAweDAs IC5sZW4gPSAweDQ5NCwKKwkuZmVhdHVyZXMgPSAwLAorCS5oaWdoZXN0X2JhbmtfYml0ID0gMHgz LAorCS5jbGtfY3RybHNbRFBVX0NMS19DVFJMX1ZJRzBdID0geworCQkucmVnX29mZiA9IDB4MkFD LCAuYml0X29mZiA9IDB9LAorCS5jbGtfY3RybHNbRFBVX0NMS19DVFJMX0RNQTBdID0geworCQku cmVnX29mZiA9IDB4MkFDLCAuYml0X29mZiA9IDh9LAorCS5jbGtfY3RybHNbRFBVX0NMS19DVFJM X0RNQTFdID0geworCQkucmVnX29mZiA9IDB4MkI0LCAuYml0X29mZiA9IDh9LAorCS5jbGtfY3Ry bHNbRFBVX0NMS19DVFJMX0NVUlNPUjBdID0geworCQkucmVnX29mZiA9IDB4MkJDLCAuYml0X29m ZiA9IDh9LAorCX0sCit9OworCiAvKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioq KioqKioqKioqKioqKioqKioqKioqKioqKgogICogQ1RMIHN1YiBibG9ja3MgY29uZmlnCiAgKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioq Ki8KQEAgLTExNiw2ICsxNTIsMjQgQEAKIAl9LAogfTsKIAorc3RhdGljIHN0cnVjdCBkcHVfY3Rs X2NmZyBzYzcxODBfY3RsW10gPSB7CisJeworCS5uYW1lID0gImN0bF8wIiwgLmlkID0gQ1RMXzAs CisJLmJhc2UgPSAweDEwMDAsIC5sZW4gPSAweEU0LAorCS5mZWF0dXJlcyA9IEJJVChEUFVfQ1RM X0FDVElWRV9DRkcpCisJfSwKKwl7CisJLm5hbWUgPSAiY3RsXzEiLCAuaWQgPSBDVExfMSwKKwku YmFzZSA9IDB4MTIwMCwgLmxlbiA9IDB4RTQsCisJLmZlYXR1cmVzID0gQklUKERQVV9DVExfQUNU SVZFX0NGRykKKwl9LAorCXsKKwkubmFtZSA9ICJjdGxfMiIsIC5pZCA9IENUTF8yLAorCS5iYXNl ID0gMHgxNDAwLCAubGVuID0gMHhFNCwKKwkuZmVhdHVyZXMgPSBCSVQoRFBVX0NUTF9BQ1RJVkVf Q0ZHKQorCX0sCit9OworCiAvKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioq KioqKioqKioqKioqKioqKioqKioqKgogICogU1NQUCBzdWIgYmxvY2tzIGNvbmZpZwogICoqKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKiov CkBAIC0yMDMsOSArMjU3LDIzIEBACiAJCXNkbTg0NV9kbWFfc2Jsa18zLCAxMywgU1NQUF9UWVBF X0RNQSwgRFBVX0NMS19DVFJMX0NVUlNPUjEpLAogfTsKIAorc3RhdGljIHN0cnVjdCBkcHVfc3Nw cF9jZmcgc2M3MTgwX3NzcHBbXSA9IHsKKwlTU1BQX0JMSygic3NwcF8wIiwgU1NQUF9WSUcwLCAw eDQwMDAsIFZJR19TQzcxODBfTUFTSywKKwkJc2RtODQ1X3ZpZ19zYmxrXzAsIDAsICBTU1BQX1RZ UEVfVklHLCBEUFVfQ0xLX0NUUkxfVklHMCksCisJU1NQUF9CTEsoInNzcHBfOCIsIFNTUFBfRE1B MCwgMHgyNDAwMCwgIERNQV9TRE04NDVfTUFTSywKKwkJc2RtODQ1X2RtYV9zYmxrXzAsIDEsIFNT UFBfVFlQRV9ETUEsIERQVV9DTEtfQ1RSTF9ETUEwKSwKKwlTU1BQX0JMSygic3NwcF85IiwgU1NQ UF9ETUExLCAweDI2MDAwLCAgRE1BX1NETTg0NV9NQVNLLAorCQlzZG04NDVfZG1hX3NibGtfMSwg NSwgU1NQUF9UWVBFX0RNQSwgRFBVX0NMS19DVFJMX0RNQTEpLAorCVNTUFBfQkxLKCJzc3BwXzEw IiwgU1NQUF9ETUEyLCAweDI4MDAwLCAgRE1BX0NVUlNPUl9TRE04NDVfTUFTSywKKwkJc2RtODQ1 X2RtYV9zYmxrXzIsIDksIFNTUFBfVFlQRV9ETUEsIERQVV9DTEtfQ1RSTF9DVVJTT1IwKSwKK307 CisKIC8qKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioq KioqKioqKioqCiAgKiBNSVhFUiBzdWIgYmxvY2tzIGNvbmZpZwogICoqKioqKioqKioqKioqKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKiovCisKKy8qIFNETTg0 NSAqLworCiBzdGF0aWMgY29uc3Qgc3RydWN0IGRwdV9sbV9zdWJfYmxrcyBzZG04NDVfbG1fc2Js ayA9IHsKIAkubWF4d2lkdGggPSBERUZBVUxUX0RQVV9PVVRQVVRfTElORV9XSURUSCwKIAkubWF4 YmxlbmRzdGFnZXMgPSAxMSwgLyogZXhjbHVkaW5nIGJhc2UgbGF5ZXIgKi8KQEAgLTIxNSwyMyAr MjgzLDQ2IEBACiAJfSwKIH07CiAKLSNkZWZpbmUgTE1fQkxLKF9uYW1lLCBfaWQsIF9iYXNlLCBf cHAsIF9sbXBhaXIpIFwKKyNkZWZpbmUgTE1fQkxLKF9uYW1lLCBfaWQsIF9iYXNlLCBfZm1hc2ss IF9zYmxrLCBfcHAsIF9sbXBhaXIpIFwKIAl7IFwKIAkubmFtZSA9IF9uYW1lLCAuaWQgPSBfaWQs IFwKIAkuYmFzZSA9IF9iYXNlLCAubGVuID0gMHgzMjAsIFwKLQkuZmVhdHVyZXMgPSBNSVhFUl9T RE04NDVfTUFTSywgXAotCS5zYmxrID0gJnNkbTg0NV9sbV9zYmxrLCBcCisJLmZlYXR1cmVzID0g X2ZtYXNrLCBcCisJLnNibGsgPSBfc2JsaywgXAogCS5waW5ncG9uZyA9IF9wcCwgXAogCS5sbV9w YWlyX21hc2sgPSAoMSA8PCBfbG1wYWlyKSBcCiAJfQogCiBzdGF0aWMgc3RydWN0IGRwdV9sbV9j Zmcgc2RtODQ1X2xtW10gPSB7Ci0JTE1fQkxLKCJsbV8wIiwgTE1fMCwgMHg0NDAwMCwgUElOR1BP TkdfMCwgTE1fMSksCi0JTE1fQkxLKCJsbV8xIiwgTE1fMSwgMHg0NTAwMCwgUElOR1BPTkdfMSwg TE1fMCksCi0JTE1fQkxLKCJsbV8yIiwgTE1fMiwgMHg0NjAwMCwgUElOR1BPTkdfMiwgTE1fNSks Ci0JTE1fQkxLKCJsbV8zIiwgTE1fMywgMHgwLCBQSU5HUE9OR19NQVgsIDApLAotCUxNX0JMSygi bG1fNCIsIExNXzQsIDB4MCwgUElOR1BPTkdfTUFYLCAwKSwKLQlMTV9CTEsoImxtXzUiLCBMTV81 LCAweDQ5MDAwLCBQSU5HUE9OR18zLCBMTV8yKSwKKwlMTV9CTEsoImxtXzAiLCBMTV8wLCAweDQ0 MDAwLCBNSVhFUl9TRE04NDVfTUFTSywKKwkJJnNkbTg0NV9sbV9zYmxrLCBQSU5HUE9OR18wLCBM TV8xKSwKKwlMTV9CTEsoImxtXzEiLCBMTV8xLCAweDQ1MDAwLCBNSVhFUl9TRE04NDVfTUFTSywK KwkJJnNkbTg0NV9sbV9zYmxrLCBQSU5HUE9OR18xLCBMTV8wKSwKKwlMTV9CTEsoImxtXzIiLCBM TV8yLCAweDQ2MDAwLCBNSVhFUl9TRE04NDVfTUFTSywKKwkJJnNkbTg0NV9sbV9zYmxrLCBQSU5H UE9OR18yLCBMTV81KSwKKwlMTV9CTEsoImxtXzMiLCBMTV8zLCAweDAsIE1JWEVSX1NETTg0NV9N QVNLLAorCQkmc2RtODQ1X2xtX3NibGssIFBJTkdQT05HX01BWCwgMCksCisJTE1fQkxLKCJsbV80 IiwgTE1fNCwgMHgwLCBNSVhFUl9TRE04NDVfTUFTSywKKwkJJnNkbTg0NV9sbV9zYmxrLCBQSU5H UE9OR19NQVgsIDApLAorCUxNX0JMSygibG1fNSIsIExNXzUsIDB4NDkwMDAsIE1JWEVSX1NETTg0 NV9NQVNLLAorCQkmc2RtODQ1X2xtX3NibGssIFBJTkdQT05HXzMsIExNXzIpLAorfTsKKworLyog U0M3MTgwICovCisKK3N0YXRpYyBjb25zdCBzdHJ1Y3QgZHB1X2xtX3N1Yl9ibGtzIHNjNzE4MF9s bV9zYmxrID0geworCS5tYXh3aWR0aCA9IERFRkFVTFRfRFBVX09VVFBVVF9MSU5FX1dJRFRILAor CS5tYXhibGVuZHN0YWdlcyA9IDcsIC8qIGV4Y2x1ZGluZyBiYXNlIGxheWVyICovCisJLmJsZW5k c3RhZ2VfYmFzZSA9IHsgLyogb2Zmc2V0cyByZWxhdGl2ZSB0byBtaXhlciBiYXNlICovCisJCTB4 MjAsIDB4MzgsIDB4NTAsIDB4NjgsIDB4ODAsIDB4OTgsIDB4YjAKKwl9LAorfTsKKworc3RhdGlj IHN0cnVjdCBkcHVfbG1fY2ZnIHNjNzE4MF9sbVtdID0geworCUxNX0JMSygibG1fMCIsIExNXzAs IDB4NDQwMDAsIE1JWEVSX1NDNzE4MF9NQVNLLAorCQkmc2M3MTgwX2xtX3NibGssIFBJTkdQT05H XzAsIExNXzEpLAorCUxNX0JMSygibG1fMSIsIExNXzEsIDB4NDUwMDAsIE1JWEVSX1NDNzE4MF9N QVNLLAorCQkmc2M3MTgwX2xtX3NibGssIFBJTkdQT05HXzEsIExNXzApLAogfTsKIAogLyoqKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioK QEAgLTI3MSw2ICszNjIsMTEgQEAKIAlQUF9CTEsoInBpbmdwb25nXzMiLCBQSU5HUE9OR18zLCAw eDcxODAwKSwKIH07CiAKK3N0YXRpYyBzdHJ1Y3QgZHB1X3Bpbmdwb25nX2NmZyBzYzcxODBfcHBb XSA9IHsKKwlQUF9CTEtfVEUoInBpbmdwb25nXzAiLCBQSU5HUE9OR18wLCAweDcwMDAwKSwKKwlQ UF9CTEtfVEUoInBpbmdwb25nXzEiLCBQSU5HUE9OR18xLCAweDcwODAwKSwKK307CisKIC8qKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioq CiAgKiBJTlRGIHN1YiBibG9ja3MgY29uZmlnCiAgKioqKioqKioqKioqKioqKioqKioqKioqKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKi8KQEAgLTI5MCw2ICszODYsMTEgQEAK IAlJTlRGX0JMSygiaW50Zl8zIiwgSU5URl8zLCAweDZCODAwLCBJTlRGX0RQLCAxKSwKIH07CiAK K3N0YXRpYyBzdHJ1Y3QgZHB1X2ludGZfY2ZnIHNjNzE4MF9pbnRmW10gPSB7CisJSU5URl9CTEso ImludGZfMCIsIElOVEZfMCwgMHg2QTAwMCwgSU5URl9EUCwgMCksCisJSU5URl9CTEsoImludGZf MSIsIElOVEZfMSwgMHg2QTgwMCwgSU5URl9EU0ksIDApLAorfTsKKwogLyoqKioqKioqKioqKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioKICAqIFZCSUYg c3ViIGJsb2NrcyBjb25maWcKICAqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioq KioqKioqKioqKioqKioqKioqKioqKioqLwpAQCAtMzQwLDYgKzQ0MSwxMCBAQAogCXsuZmwgPSAw LCAubHV0ID0gMHgxMTIyMjIyMjIyMzM1N30KIH07CiAKK3N0YXRpYyBzdHJ1Y3QgZHB1X3Fvc19s dXRfZW50cnkgc2M3MTgwX3Fvc19saW5lYXJbXSA9IHsKKwl7LmZsID0gMCwgLmx1dCA9IDB4MDAx MTIyMjIyMjMzNTc3N30sCit9OworCiBzdGF0aWMgc3RydWN0IGRwdV9xb3NfbHV0X2VudHJ5IHNk bTg0NV9xb3NfbWFjcm90aWxlW10gPSB7CiAJey5mbCA9IDEwLCAubHV0ID0gMHgzNDQ1NTY2Nzd9 LAogCXsuZmwgPSAxMSwgLmx1dCA9IDB4MzM0NDU1NjY3N30sCkBAIC0zNDksMTAgKzQ1NCwxOCBA QAogCXsuZmwgPSAwLCAubHV0ID0gMHgxMTIyMzMzNDQ1NTY2Nzd9LAogfTsKIAorc3RhdGljIHN0 cnVjdCBkcHVfcW9zX2x1dF9lbnRyeSBzYzcxODBfcW9zX21hY3JvdGlsZVtdID0geworCXsuZmwg PSAwLCAubHV0ID0gMHgwMDExMjIzMzQ0NTU2Njc3fSwKK307CisKIHN0YXRpYyBzdHJ1Y3QgZHB1 X3Fvc19sdXRfZW50cnkgc2RtODQ1X3Fvc19ucnRbXSA9IHsKIAl7LmZsID0gMCwgLmx1dCA9IDB4 MH0sCiB9OwogCitzdGF0aWMgc3RydWN0IGRwdV9xb3NfbHV0X2VudHJ5IHNjNzE4MF9xb3NfbnJ0 W10gPSB7CisJey5mbCA9IDAsIC5sdXQgPSAweDB9LAorfTsKKwogc3RhdGljIHN0cnVjdCBkcHVf cGVyZl9jZmcgc2RtODQ1X3BlcmZfZGF0YSA9IHsKIAkubWF4X2J3X2xvdyA9IDY4MDAwMDAsCiAJ Lm1heF9id19oaWdoID0gNjgwMDAwMCwKQEAgLTM5Miw2ICs1MDUsMzAgQEAKIAl9LAogfTsKIAor c3RhdGljIHN0cnVjdCBkcHVfcGVyZl9jZmcgc2M3MTgwX3BlcmZfZGF0YSA9IHsKKwkubWF4X2J3 X2xvdyA9IDM5MDAwMDAsCisJLm1heF9id19oaWdoID0gNTUwMDAwMCwKKwkubWluX2NvcmVfaWIg PSAyNDAwMDAwLAorCS5taW5fbGxjY19pYiA9IDgwMDAwMCwKKwkubWluX2RyYW1faWIgPSA4MDAw MDAsCisJLmRhbmdlcl9sdXRfdGJsID0gezB4ZmYsIDB4ZmZmZiwgMHgwfSwKKwkucW9zX2x1dF90 YmwgPSB7CisJCXsubmVudHJ5ID0gQVJSQVlfU0laRShzYzcxODBfcW9zX2xpbmVhciksCisJCS5l bnRyaWVzID0gc2M3MTgwX3Fvc19saW5lYXIKKwkJfSwKKwkJey5uZW50cnkgPSBBUlJBWV9TSVpF KHNjNzE4MF9xb3NfbWFjcm90aWxlKSwKKwkJLmVudHJpZXMgPSBzYzcxODBfcW9zX21hY3JvdGls ZQorCQl9LAorCQl7Lm5lbnRyeSA9IEFSUkFZX1NJWkUoc2M3MTgwX3Fvc19ucnQpLAorCQkuZW50 cmllcyA9IHNjNzE4MF9xb3NfbnJ0CisJCX0sCisJfSwKKwkuY2RwX2NmZyA9IHsKKwkJey5yZF9l bmFibGUgPSAxLCAud3JfZW5hYmxlID0gMX0sCisJCXsucmRfZW5hYmxlID0gMSwgLndyX2VuYWJs ZSA9IDB9CisJfSwKK307CisKIC8qKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioq KioqKioqKioqKioqKioqKioqKioqKioqCiAgKiBIYXJkd2FyZSBjYXRhbG9nIGluaXQKICAqKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioq LwpAQCAtNDI1LDkgKzU2MiwzOSBAQCBzdGF0aWMgdm9pZCBzZG04NDVfY2ZnX2luaXQoc3RydWN0 IGRwdV9tZHNzX2NmZyAqZHB1X2NmZykKIAl9OwogfQogCisvKgorICogc2M3MTgwX2NmZ19pbml0 KCk6IHBvcHVsYXRlIHNjNzE4MCBkcHUgc3ViLWJsb2NrcyByZWcgb2Zmc2V0cworICogYW5kIGlu c3RhbmNlIGNvdW50cy4KKyAqLworc3RhdGljIHZvaWQgc2M3MTgwX2NmZ19pbml0KHN0cnVjdCBk cHVfbWRzc19jZmcgKmRwdV9jZmcpCit7CisJKmRwdV9jZmcgPSAoc3RydWN0IGRwdV9tZHNzX2Nm Zyl7CisJCS5jYXBzID0gJnNjNzE4MF9kcHVfY2FwcywKKwkJLm1kcF9jb3VudCA9IEFSUkFZX1NJ WkUoc2M3MTgwX21kcCksCisJCS5tZHAgPSBzYzcxODBfbWRwLAorCQkuY3RsX2NvdW50ID0gQVJS QVlfU0laRShzYzcxODBfY3RsKSwKKwkJLmN0bCA9IHNjNzE4MF9jdGwsCisJCS5zc3BwX2NvdW50 ID0gQVJSQVlfU0laRShzYzcxODBfc3NwcCksCisJCS5zc3BwID0gc2M3MTgwX3NzcHAsCisJCS5t aXhlcl9jb3VudCA9IEFSUkFZX1NJWkUoc2M3MTgwX2xtKSwKKwkJLm1peGVyID0gc2M3MTgwX2xt LAorCQkucGluZ3BvbmdfY291bnQgPSBBUlJBWV9TSVpFKHNjNzE4MF9wcCksCisJCS5waW5ncG9u ZyA9IHNjNzE4MF9wcCwKKwkJLmludGZfY291bnQgPSBBUlJBWV9TSVpFKHNjNzE4MF9pbnRmKSwK KwkJLmludGYgPSBzYzcxODBfaW50ZiwKKwkJLnZiaWZfY291bnQgPSBBUlJBWV9TSVpFKHNkbTg0 NV92YmlmKSwKKwkJLnZiaWYgPSBzZG04NDVfdmJpZiwKKwkJLnJlZ19kbWFfY291bnQgPSAxLAor CQkuZG1hX2NmZyA9IHNkbTg0NV9yZWdkbWEsCisJCS5wZXJmID0gc2M3MTgwX3BlcmZfZGF0YSwK KwkJLm1kc3NfaXJxcyA9IDB4M2YsCisJfTsKK30KKwogc3RhdGljIHN0cnVjdCBkcHVfbWRzc19o d19jZmdfaGFuZGxlciBjZmdfaGFuZGxlcltdID0gewogCXsgLmh3X3JldiA9IERQVV9IV19WRVJf NDAwLCAuY2ZnX2luaXQgPSBzZG04NDVfY2ZnX2luaXR9LAogCXsgLmh3X3JldiA9IERQVV9IV19W RVJfNDAxLCAuY2ZnX2luaXQgPSBzZG04NDVfY2ZnX2luaXR9LAorCXsgLmh3X3JldiA9IERQVV9I V19WRVJfNjIwLCAuY2ZnX2luaXQgPSBzYzcxODBfY2ZnX2luaXR9LAogfTsKIAogdm9pZCBkcHVf aHdfY2F0YWxvZ19kZWluaXQoc3RydWN0IGRwdV9tZHNzX2NmZyAqZHB1X2NmZykKZGlmZiAtLWdp dCBhL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV9od19jYXRhbG9nLmggYi9kcml2 ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvZHB1MS9kcHVfaHdfY2F0YWxvZy5oCmluZGV4IDBmZDNmNTAu LjI2MDdlZjMgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV9o d19jYXRhbG9nLmgKKysrIGIvZHJpdmVycy9ncHUvZHJtL21zbS9kaXNwL2RwdTEvZHB1X2h3X2Nh dGFsb2cuaApAQCAtMzgsNiArMzgsNyBAQAogI2RlZmluZSBEUFVfSFdfVkVSXzQwMQlEUFVfSFdf VkVSKDQsIDAsIDEpIC8qIHNkbTg0NSB2Mi4wICovCiAjZGVmaW5lIERQVV9IV19WRVJfNDEwCURQ VV9IV19WRVIoNCwgMSwgMCkgLyogc2RtNjcwIHYxLjAgKi8KICNkZWZpbmUgRFBVX0hXX1ZFUl81 MDAJRFBVX0hXX1ZFUig1LCAwLCAwKSAvKiBzZG04NTUgdjEuMCAqLworI2RlZmluZSBEUFVfSFdf VkVSXzYyMAlEUFVfSFdfVkVSKDYsIDIsIDApIC8qIHNjNzE4MCB2MS4wICovCiAKIAogI2RlZmlu ZSBJU19NU004OTk2X1RBUkdFVChyZXYpIElTX0RQVV9NQUpPUl9NSU5PUl9TQU1FKChyZXYpLCBE UFVfSFdfVkVSXzE3MCkKQEAgLTQ1LDYgKzQ2LDcgQEAKICNkZWZpbmUgSVNfU0RNODQ1X1RBUkdF VChyZXYpIElTX0RQVV9NQUpPUl9NSU5PUl9TQU1FKChyZXYpLCBEUFVfSFdfVkVSXzQwMCkKICNk ZWZpbmUgSVNfU0RNNjcwX1RBUkdFVChyZXYpIElTX0RQVV9NQUpPUl9NSU5PUl9TQU1FKChyZXYp LCBEUFVfSFdfVkVSXzQxMCkKICNkZWZpbmUgSVNfU0RNODU1X1RBUkdFVChyZXYpIElTX0RQVV9N QUpPUl9NSU5PUl9TQU1FKChyZXYpLCBEUFVfSFdfVkVSXzUwMCkKKyNkZWZpbmUgSVNfU0M3MTgw X1RBUkdFVChyZXYpIElTX0RQVV9NQUpPUl9NSU5PUl9TQU1FKChyZXYpLCBEUFVfSFdfVkVSXzYy MCkKIAogCiAjZGVmaW5lIERQVV9IV19CTEtfTkFNRV9MRU4JMTYKQEAgLTExMCw2ICsxMTIsNyBA QCBlbnVtIHsKIAlEUFVfU1NQUF9TUkMgPSAweDEsCiAJRFBVX1NTUFBfU0NBTEVSX1FTRUVEMiwK IAlEUFVfU1NQUF9TQ0FMRVJfUVNFRUQzLAorCURQVV9TU1BQX1NDQUxFUl9RU0VFRDQsCiAJRFBV X1NTUFBfU0NBTEVSX1JHQiwKIAlEUFVfU1NQUF9DU0MsCiAJRFBVX1NTUFBfQ1NDXzEwQklULApA QCAtMTY2LDYgKzE2OSw3IEBAIGVudW0gewogICovCiBlbnVtIHsKIAlEUFVfQ1RMX1NQTElUX0RJ U1BMQVkgPSAweDEsCisJRFBVX0NUTF9BQ1RJVkVfQ0ZHLAogCURQVV9DVExfTUFYCiB9OwogCmRp ZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvZHB1MS9kcHVfaHdfbG0uYyBiL2Ry aXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV9od19sbS5jCmluZGV4IDViYzM5YmEuLmQw Y2IxZDggMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV9od19s bS5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV9od19sbS5jCkBAIC0x NTIsNyArMTUyLDcgQEAgc3RhdGljIHZvaWQgX3NldHVwX21peGVyX29wcyhzdHJ1Y3QgZHB1X21k c3NfY2ZnICptLAogCQl1bnNpZ25lZCBsb25nIGZlYXR1cmVzKQogewogCW9wcy0+c2V0dXBfbWl4 ZXJfb3V0ID0gZHB1X2h3X2xtX3NldHVwX291dDsKLQlpZiAoSVNfU0RNODQ1X1RBUkdFVChtLT5o d3ZlcnNpb24pIHx8IElTX1NETTY3MF9UQVJHRVQobS0+aHd2ZXJzaW9uKSkKKwlpZiAoSVNfU0RN ODQ1X1RBUkdFVChtLT5od3ZlcnNpb24pIHx8IElTX1NETTY3MF9UQVJHRVQobS0+aHd2ZXJzaW9u KSB8fCBJU19TQzcxODBfVEFSR0VUKG0tPmh3dmVyc2lvbikpCiAJCW9wcy0+c2V0dXBfYmxlbmRf Y29uZmlnID0gZHB1X2h3X2xtX3NldHVwX2JsZW5kX2NvbmZpZ19zZG04NDU7CiAJZWxzZQogCQlv cHMtPnNldHVwX2JsZW5kX2NvbmZpZyA9IGRwdV9od19sbV9zZXR1cF9ibGVuZF9jb25maWc7CmRp ZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvZHB1MS9kcHVfa21zLmMgYi9kcml2 ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvZHB1MS9kcHVfa21zLmMKaW5kZXggNThiMDQ4NS4uZWU5M2Jh MyAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL21zbS9kaXNwL2RwdTEvZHB1X2ttcy5jCisr KyBiL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV9rbXMuYwpAQCAtMTExMSw2ICsx MTExLDcgQEAgc3RhdGljIGludCBfX21heWJlX3VudXNlZCBkcHVfcnVudGltZV9yZXN1bWUoc3Ry dWN0IGRldmljZSAqZGV2KQogCiBzdGF0aWMgY29uc3Qgc3RydWN0IG9mX2RldmljZV9pZCBkcHVf ZHRfbWF0Y2hbXSA9IHsKIAl7IC5jb21wYXRpYmxlID0gInFjb20sc2RtODQ1LWRwdSIsIH0sCisJ eyAuY29tcGF0aWJsZSA9ICJxY29tLHNjNzE4MC1kcHUiLCB9LAogCXt9CiB9OwogTU9EVUxFX0RF VklDRV9UQUJMRShvZiwgZHB1X2R0X21hdGNoKTsKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2Ry bS9tc20vbXNtX2Rydi5jIGIvZHJpdmVycy9ncHUvZHJtL21zbS9tc21fZHJ2LmMKaW5kZXggYzg0 ZjBhOC4uZjUwZmVmYiAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL21zbS9tc21fZHJ2LmMK KysrIGIvZHJpdmVycy9ncHUvZHJtL21zbS9tc21fZHJ2LmMKQEAgLTExOTIsNyArMTE5Miw4IEBA IHN0YXRpYyBpbnQgYWRkX2Rpc3BsYXlfY29tcG9uZW50cyhzdHJ1Y3QgZGV2aWNlICpkZXYsCiAJ ICogdGhlIGludGVyZmFjZXMgdG8gb3VyIGNvbXBvbmVudHMgbGlzdC4KIAkgKi8KIAlpZiAob2Zf ZGV2aWNlX2lzX2NvbXBhdGlibGUoZGV2LT5vZl9ub2RlLCAicWNvbSxtZHNzIikgfHwKLQkgICAg b2ZfZGV2aWNlX2lzX2NvbXBhdGlibGUoZGV2LT5vZl9ub2RlLCAicWNvbSxzZG04NDUtbWRzcyIp KSB7CisJICAgIG9mX2RldmljZV9pc19jb21wYXRpYmxlKGRldi0+b2Zfbm9kZSwgInFjb20sc2Rt ODQ1LW1kc3MiKSB8fAorCSAgICBvZl9kZXZpY2VfaXNfY29tcGF0aWJsZShkZXYtPm9mX25vZGUs ICJxY29tLHNjNzE4MC1tZHNzIikpIHsKIAkJcmV0ID0gb2ZfcGxhdGZvcm1fcG9wdWxhdGUoZGV2 LT5vZl9ub2RlLCBOVUxMLCBOVUxMLCBkZXYpOwogCQlpZiAocmV0KSB7CiAJCQlEUk1fREVWX0VS Uk9SKGRldiwgImZhaWxlZCB0byBwb3B1bGF0ZSBjaGlsZHJlbiBkZXZpY2VzXG4iKTsKQEAgLTEz MTcsNiArMTMxOCw3IEBAIHN0YXRpYyBpbnQgbXNtX3BkZXZfcmVtb3ZlKHN0cnVjdCBwbGF0Zm9y bV9kZXZpY2UgKnBkZXYpCiAJeyAuY29tcGF0aWJsZSA9ICJxY29tLG1kcDQiLCAuZGF0YSA9ICh2 b2lkICopS01TX01EUDQgfSwKIAl7IC5jb21wYXRpYmxlID0gInFjb20sbWRzcyIsIC5kYXRhID0g KHZvaWQgKilLTVNfTURQNSB9LAogCXsgLmNvbXBhdGlibGUgPSAicWNvbSxzZG04NDUtbWRzcyIs IC5kYXRhID0gKHZvaWQgKilLTVNfRFBVIH0sCisJeyAuY29tcGF0aWJsZSA9ICJxY29tLHNjNzE4 MC1tZHNzIiwgLmRhdGEgPSAodm9pZCAqKUtNU19EUFUgfSwKIAl7fQogfTsKIE1PRFVMRV9ERVZJ Q0VfVEFCTEUob2YsIGR0X21hdGNoKTsKLS0gCjEuOS4xCgpfX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZl bEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFp bG1hbi9saXN0aW5mby9kcmktZGV2ZWw=