From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 5/5] drm/i915: DP_PIPE_ENABLED must check transcoder on CPT Date: Tue, 26 Jul 2011 09:46:48 -0700 Message-ID: <20110726094648.2100f149@jbarnes-desktop> References: <1311662194-4050-1-git-send-email-keithp@keithp.com> <1311662194-4050-6-git-send-email-keithp@keithp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1311662194-4050-6-git-send-email-keithp@keithp.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Keith Packard Cc: Dave Airlie , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org On Mon, 25 Jul 2011 23:36:34 -0700 Keith Packard wrote: > Display port pipe selection on CPT is not done with a bit in the > output register, rather it is controlled by a couple of bits in the > separate transcoder register which indicate which display port output > is connected to the transcoder. > > This patch replaces the simplistic macro DP_PIPE_ENABLED with the > rather more complicated function dp_pipe_enabled which checks the > output register to see if that is enabled, and then goes on to either > check the output register pipe selection bit (on non-CPT) or the > transcoder DP selection bits (on CPT). > > Before this patch, any time the mode of pipe A was changed, any > display port outputs on pipe B would get disabled as > intel_disable_pch_ports would ensure that the mode setting operation > could occur on pipe A without interference from other outputs > connected to that pch port > > Signed-off-by: Keith Packard > --- Ah nice catch. I expect one day we'll have all the chipset and PCH differences coded... Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center