From: Thierry Reding <thierry.reding@gmail.com>
To: "Stéphane Marchesin" <marcheu@chromium.org>
Cc: treding@nvidia.com, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/tegra: Align FB pitch
Date: Thu, 5 Jun 2014 11:40:49 +0200 [thread overview]
Message-ID: <20140605094048.GA23296@ulmo> (raw)
In-Reply-To: <1400896714-7092-1-git-send-email-marcheu@chromium.org>
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On Fri, May 23, 2014 at 06:58:32PM -0700, Stéphane Marchesin wrote:
> The display controller doesn't handle non-256 byte aligned buffer
> pitches. If you give it an unaligned buffer, it will stop after the
> first line and will report underflows in the debug registers
> (DC_WINBUF_UFLOW_STATUS and friends). So let's make sure that all our
> framebuffer pitches are 256-byte aligned.
>
> Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
> ---
> drivers/gpu/drm/tegra/drm.h | 2 ++
> drivers/gpu/drm/tegra/fb.c | 3 ++-
> drivers/gpu/drm/tegra/gem.c | 2 ++
> 3 files changed, 6 insertions(+), 1 deletion(-)
Can you point me to where this requirement is documented? I've gone
through the TRM and all I can find is that the line stride needs to be
64 byte aligned. Also I seem to remember that resolutions such as
1366x768 used to work for HDMI at least on earlier Tegra generations.
Perhaps this is a requirement that's new on Tegra124?
Thierry
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prev parent reply other threads:[~2014-06-05 9:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-24 1:58 [PATCH 1/3] drm/tegra: Align FB pitch Stéphane Marchesin
2014-05-24 1:58 ` [PATCH 2/3] drm/tegra: Support setting the EMC clock Stéphane Marchesin
2014-05-26 9:07 ` Lucas Stach
2014-05-26 9:28 ` Stéphane Marchesin
[not found] ` <CACP_E+J-sCsiiSX-apX3ZqWFHVGxgN5FG9eu9-qTjLQHF22DwA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-05-26 9:35 ` Thierry Reding
2014-05-26 9:52 ` Stéphane Marchesin
2014-05-24 1:58 ` [PATCH 3/3] drm/tegra: Don't hardcode link parameters Stéphane Marchesin
2014-06-05 9:40 ` Thierry Reding [this message]
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