From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [Intel-gfx] [PATCH 2/5] drm/i915: preserve swizzle settings if necessary v3 Date: Mon, 7 Jul 2014 11:03:41 +0200 Message-ID: <20140707090341.GJ5821@phenom.ffwll.local> References: <1401992671-2548-2-git-send-email-jbarnes@virtuousgeek.org> <20140610140251.GP5821@phenom.ffwll.local> <20140610102711.171104dc@jbarnes-desktop> <20140610193326.GB5821@phenom.ffwll.local> <20140610124538.350e86ba@jbarnes-desktop> <20140611081345.2d805e8c@jbarnes-desktop> <20140611084113.4c1089af@jbarnes-desktop> <53AD989D.2020408@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wi0-f175.google.com (mail-wi0-f175.google.com [209.85.212.175]) by gabe.freedesktop.org (Postfix) with ESMTP id 45ABA6E295 for ; Mon, 7 Jul 2014 02:03:33 -0700 (PDT) Received: by mail-wi0-f175.google.com with SMTP id r20so15543599wiv.8 for ; Mon, 07 Jul 2014 02:03:32 -0700 (PDT) Content-Disposition: inline In-Reply-To: <53AD989D.2020408@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Steve Aarnio Cc: dri-devel , intel-gfx , Jesse Barnes List-Id: dri-devel@lists.freedesktop.org On Fri, Jun 27, 2014 at 09:15:25AM -0700, Steve Aarnio wrote: > On 06/11/2014 08:41 AM, Jesse Barnes wrote: > >On Wed, 11 Jun 2014 17:39:29 +0200 > >Daniel Vetter wrote: > > > >>On Wed, Jun 11, 2014 at 5:13 PM, Jesse Barnes wrote: > >>>>- If you have a machine which uses tiled framebuffers and enables > >>>> swizzling in the BIOS your code will a) drop the swizzle setup in > >>>> gem_init_hw, breaking resume b) not set the swizzle settings correctly > >>>> in swizzle_detect, breaking swap in/out and pwrite/pread. Not sure such > >>>> a machine exists, but still. > >>> > >>>This would affect krh's MBA, which is why I wanted testing here... > >>>anyway I'll spin a new one and ask krh to test again. > >> > >>Hm, I've thought the issue with the MBA is that it used tiled fbs, but > >>non-swizzled. And then a mess ensued when we've enabled it. But yeah, > >>unfortunately with the new logic we need to retest :( > > > >Ah yeah I think you're right, either way, need more testing. > > > >Maybe we should have just gone with the first patch to never enable > >swizzling based on Art's assertion that it didn't matter. > > > > I hate to jump into the middle of a conversation that may or may not be > related to a patch I just posted... but... > > There was a very long internal discussion that the Windows guys had with > H/W. For Gen8+ H/W recommends disabling CSX swizzle. Technically, BDW still > supports it, but there is a bug _somewhere_ that makes it problematic. In > any case it goes away for sure with Gen9+, so disabling on Gen8 doesn't > hurt. > > According to the other discussion, the H/W guys say that enabling actually > hurts performance slightly, and the driver should leave the swizzle > decisions to the memory controller. Patch to disable swizzling detection on gen8+ in i915_gem_tiling.c (only there, imo ok to keep the hw paths around for setting up the registers) welcome ;-) -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch