From: Thierry Reding <thierry.reding@gmail.com>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: kernel@pengutronix.de, dri-devel@lists.freedesktop.org,
patchwork-lst@pengutronix.de
Subject: Re: [PATCH 2/2] drm/panel: correct minimum hsync length of the HannStar HSD070PWW1 panel
Date: Fri, 7 Aug 2015 14:43:17 +0200 [thread overview]
Message-ID: <20150807124316.GD25792@ulmo> (raw)
In-Reply-To: <1435314429-10511-2-git-send-email-l.stach@pengutronix.de>
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On Fri, Jun 26, 2015 at 12:27:09PM +0200, Lucas Stach wrote:
> From: Philipp Zabel <p.zabel@pengutronix.de>
>
> According to the data sheet, the minimum horizontal blanking interval
> is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
> minimum working horizontal blanking interval to be 60 clocks.
>
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> drivers/gpu/drm/panel/panel-simple.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> index dc6a923c89d7..7196b940a928 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -713,7 +713,12 @@ static const struct display_timing hannstar_hsd070pww1_timing = {
> .hactive = { 1280, 1280, 1280 },
> .hfront_porch = { 1, 1, 10 },
> .hback_porch = { 1, 1, 10 },
> - .hsync_len = { 52, 158, 661 },
> + /*
> + * According to the data sheet, the minimum horizontal blanking interval
> + * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
> + * minimum working horizontal blanking interval to be 60 clocks.
> + */
> + .hsync_len = { 58, 158, 661 },
58 != 60, so which one is the truth here?
Thierry
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next prev parent reply other threads:[~2015-08-07 12:44 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-26 10:27 [PATCH 1/2] drm/panel: simple: Add bus format for HannStar HSD070PWW1 LVDS panel Lucas Stach
2015-06-26 10:27 ` [PATCH 2/2] drm/panel: correct minimum hsync length of the HannStar HSD070PWW1 panel Lucas Stach
2015-08-07 12:43 ` Thierry Reding [this message]
2015-08-07 12:48 ` Lucas Stach
2015-07-23 14:45 ` [PATCH 1/2] drm/panel: simple: Add bus format for HannStar HSD070PWW1 LVDS panel Lucas Stach
2015-08-07 12:31 ` Lucas Stach
2015-08-07 12:42 ` Thierry Reding
2015-08-07 13:06 ` Philipp Zabel
2015-08-07 13:22 ` Thierry Reding
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