* [PATCH 1/3] drm/fsl-dcu: enable TCON bypass mode by default
@ 2016-10-05 0:58 Stefan Agner
2016-10-05 0:58 ` [PATCH 2/3] drm/fsl-dcu: do not explicitly transfer registers on plane init Stefan Agner
2016-10-05 0:58 ` [PATCH 3/3] drm/fsl-dcu: enable pixel clock when enabling CRTC Stefan Agner
0 siblings, 2 replies; 3+ messages in thread
From: Stefan Agner @ 2016-10-05 0:58 UTC (permalink / raw)
To: meng.yi, dri-devel; +Cc: jianwei.wang.chn, linux-kernel, alison.wang
Do not use encoder disable/enable callbacks to control bypass
mode as this seems to mess with the signals not liked by
displays. This also makes more sense since the encoder is
already defined to be parallel RGB/LVDS at creation time.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
I tested that on Vybrid. Meng, since LS1021a does not use TCON this
should not affect LS1021a, so I think we are fine.
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c | 24 ++++--------------------
1 file changed, 4 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
index 26edcc8..e26c820 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
@@ -28,28 +28,8 @@ fsl_dcu_drm_encoder_atomic_check(struct drm_encoder *encoder,
return 0;
}
-static void fsl_dcu_drm_encoder_disable(struct drm_encoder *encoder)
-{
- struct drm_device *dev = encoder->dev;
- struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
-
- if (fsl_dev->tcon)
- fsl_tcon_bypass_disable(fsl_dev->tcon);
-}
-
-static void fsl_dcu_drm_encoder_enable(struct drm_encoder *encoder)
-{
- struct drm_device *dev = encoder->dev;
- struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
-
- if (fsl_dev->tcon)
- fsl_tcon_bypass_enable(fsl_dev->tcon);
-}
-
static const struct drm_encoder_helper_funcs encoder_helper_funcs = {
.atomic_check = fsl_dcu_drm_encoder_atomic_check,
- .disable = fsl_dcu_drm_encoder_disable,
- .enable = fsl_dcu_drm_encoder_enable,
};
static void fsl_dcu_drm_encoder_destroy(struct drm_encoder *encoder)
@@ -68,6 +48,10 @@ int fsl_dcu_drm_encoder_create(struct fsl_dcu_drm_device *fsl_dev,
int ret;
encoder->possible_crtcs = 1;
+
+ /* Use bypass mode for parallel RGB/LVDS encoder */
+ fsl_tcon_bypass_enable(fsl_dev->tcon);
+
ret = drm_encoder_init(fsl_dev->drm, encoder, &encoder_funcs,
DRM_MODE_ENCODER_LVDS, NULL);
if (ret < 0)
--
2.10.0
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/3] drm/fsl-dcu: do not explicitly transfer registers on plane init
2016-10-05 0:58 [PATCH 1/3] drm/fsl-dcu: enable TCON bypass mode by default Stefan Agner
@ 2016-10-05 0:58 ` Stefan Agner
2016-10-05 0:58 ` [PATCH 3/3] drm/fsl-dcu: enable pixel clock when enabling CRTC Stefan Agner
1 sibling, 0 replies; 3+ messages in thread
From: Stefan Agner @ 2016-10-05 0:58 UTC (permalink / raw)
To: meng.yi, dri-devel; +Cc: jianwei.wang.chn, linux-kernel, alison.wang
There is no need to explicitly initiate a register transfer and
turn off the DCU after initializing the plane registers. In fact,
this is harmful and leads to unnecessary flickers if the DCU has
been left on by the bootloader.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
If you could give this and 3/3 a try on LS1021a I would be glad.
Since those are fixes I would like to send them for v4.9...
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c
index a7e5486..9e6f7d8 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c
@@ -211,11 +211,6 @@ void fsl_dcu_drm_init_planes(struct drm_device *dev)
for (j = 1; j <= fsl_dev->soc->layer_regs; j++)
regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);
}
- regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
- DCU_MODE_DCU_MODE_MASK,
- DCU_MODE_DCU_MODE(DCU_MODE_OFF));
- regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
- DCU_UPDATE_MODE_READREG);
}
struct drm_plane *fsl_dcu_drm_primary_create_plane(struct drm_device *dev)
--
2.10.0
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 3/3] drm/fsl-dcu: enable pixel clock when enabling CRTC
2016-10-05 0:58 [PATCH 1/3] drm/fsl-dcu: enable TCON bypass mode by default Stefan Agner
2016-10-05 0:58 ` [PATCH 2/3] drm/fsl-dcu: do not explicitly transfer registers on plane init Stefan Agner
@ 2016-10-05 0:58 ` Stefan Agner
1 sibling, 0 replies; 3+ messages in thread
From: Stefan Agner @ 2016-10-05 0:58 UTC (permalink / raw)
To: meng.yi, dri-devel; +Cc: jianwei.wang.chn, linux-kernel, alison.wang
The pixel clock should not be on if the CRTC is not in use, hence
move clock enable/disable calls into CRTC callbacks.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 7 +++++++
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 16 +---------------
2 files changed, 8 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index 3371635..4fe0403 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -51,13 +51,20 @@ static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
DCU_MODE_DCU_MODE(DCU_MODE_OFF));
regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
DCU_UPDATE_MODE_READREG);
+ clk_disable_unprepare(fsl_dev->pix_clk);
}
static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
+ int ret;
+ ret = clk_prepare_enable(fsl_dev->pix_clk);
+ if (ret < 0) {
+ dev_err(fsl_dev->dev, "failed to enable pix clk\n");
+ return;
+ }
regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
DCU_MODE_DCU_MODE_MASK,
DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 0884c45..a6863f9 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -267,12 +267,6 @@ static int fsl_dcu_drm_pm_resume(struct device *dev)
return ret;
}
- ret = clk_prepare_enable(fsl_dev->pix_clk);
- if (ret < 0) {
- dev_err(dev, "failed to enable pix clk\n");
- goto disable_dcu_clk;
- }
-
fsl_dcu_drm_init_planes(fsl_dev->drm);
drm_atomic_helper_resume(fsl_dev->drm, fsl_dev->state);
@@ -401,18 +395,12 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
goto disable_clk;
}
- ret = clk_prepare_enable(fsl_dev->pix_clk);
- if (ret < 0) {
- dev_err(dev, "failed to enable pix clk\n");
- goto unregister_pix_clk;
- }
-
fsl_dev->tcon = fsl_tcon_init(dev);
drm = drm_dev_alloc(driver, dev);
if (IS_ERR(drm)) {
ret = PTR_ERR(drm);
- goto disable_pix_clk;
+ goto unregister_pix_clk;
}
fsl_dev->dev = dev;
@@ -433,8 +421,6 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
unref:
drm_dev_unref(drm);
-disable_pix_clk:
- clk_disable_unprepare(fsl_dev->pix_clk);
unregister_pix_clk:
clk_unregister(fsl_dev->pix_clk);
disable_clk:
--
2.10.0
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^ permalink raw reply related [flat|nested] 3+ messages in thread
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2016-10-05 0:58 [PATCH 1/3] drm/fsl-dcu: enable TCON bypass mode by default Stefan Agner
2016-10-05 0:58 ` [PATCH 2/3] drm/fsl-dcu: do not explicitly transfer registers on plane init Stefan Agner
2016-10-05 0:58 ` [PATCH 3/3] drm/fsl-dcu: enable pixel clock when enabling CRTC Stefan Agner
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