From: Stefan Agner <stefan@agner.ch>
To: meng.yi@nxp.com, dri-devel@lists.freedesktop.org
Cc: jianwei.wang.chn@gmail.com, linux-kernel@vger.kernel.org,
alison.wang@freescale.com
Subject: [PATCH v2 3/5] drm/fsl-dcu: do not transfer registers in mode_set_nofb
Date: Wed, 5 Oct 2016 14:47:01 -0700 [thread overview]
Message-ID: <20161005214703.1604-6-stefan@agner.ch> (raw)
In-Reply-To: <20161005214703.1604-1-stefan@agner.ch>
Do not schedule a transfer of mode settings early. Modes should
get applied on on CRTC enable where we also enable the pixel clock.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index 3371635..5ad1d68 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -116,8 +116,6 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
- regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
- DCU_UPDATE_MODE_READREG);
return;
}
--
2.10.0
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next prev parent reply other threads:[~2016-10-05 21:47 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-05 21:46 [PATCH v2 0/5] drm/fsl-dcu: initialization fixes Stefan Agner
2016-10-05 21:46 ` [PATCH v2 1/5] drm/fsl-dcu: enable TCON bypass mode by default Stefan Agner
2016-10-05 21:46 ` [PATCH v2 2/5] drm/fsl-dcu: do not explicitly transfer registers on plane init Stefan Agner
2016-10-05 21:46 ` [PATCH v2 2/5] drm/fsl-dcu: do not " Stefan Agner
2016-10-05 21:47 ` [PATCH v2 3/5] drm/fsl-dcu: do not transfer register in mode_set_nofb Stefan Agner
2016-10-05 21:47 ` Stefan Agner [this message]
2016-10-05 21:47 ` [PATCH v2 4/5] drm/fsl-dcu: enable pixel clock when enabling CRTC Stefan Agner
2016-10-05 21:47 ` [PATCH v2 5/5] drm/fsl-dcu: only init fbdev if required Stefan Agner
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