From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: Jose Abreu <Jose.Abreu@synopsys.com>, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v2 1/3] drm: Add SCDC helpers
Date: Mon, 5 Dec 2016 15:31:36 +0200 [thread overview]
Message-ID: <20161205133136.GD31595@intel.com> (raw)
In-Reply-To: <20161205111652.GE19891@ulmo.ba.sec>
On Mon, Dec 05, 2016 at 12:16:52PM +0100, Thierry Reding wrote:
> On Mon, Dec 05, 2016 at 10:12:39AM +0000, Jose Abreu wrote:
> > On 02-12-2016 19:24, Thierry Reding wrote:
> [...]
> > > +/**
> > > + * drm_scdc_write - write a block of data to SCDC
> > > + * @adapter: I2C controller
> > > + * @offset: start offset of block to write
> > > + * @buffer: block of data to write
> > > + * @size: size of the block to write
> > > + *
> > > + * Writes a block of data to SCDC, starting at a given offset.
> > > + *
> > > + * Returns:
> > > + * The number of bytes written to SCDC or a negative error code on failure.
> > > + */
> > > +ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
> > > + const void *buffer, size_t size)
> > > +{
> > > + struct i2c_msg msg = {
> > > + .addr = SCDC_I2C_SLAVE_ADDRESS,
> > > + .flags = 0,
> > > + .len = 1 + size,
> > > + .buf = NULL,
> > > + };
> > > + void *data;
> > > + int err;
> > > +
> > > + data = kmalloc(1 + size, GFP_TEMPORARY);
> > > + if (!data)
> > > + return -ENOMEM;
> > > +
> > > + msg.buf = data;
> > > +
> > > + memcpy(data, &offset, sizeof(offset));
> > > + memcpy(data + 1, buffer, size);
> >
> > Don't you agree it would be better if you use the same scheme as
> > drm_scdc_read()? Something like:
> >
> > struct i2c_msg msgs[] = {
> > {
> > .addr = SCDC_I2C_SLAVE_ADDRESS,
> > .flags = 0,
> > .len = 1,
> > .buf = &offset,
> > }, {
> > .addr = SCDC_I2C_SLAVE_ADDRESS,
> > .flags = 0,
> > .len = size,
> > .buf = buffer,
> > },
> > };
>
> Ville had a similar comment on a prior iteration. It looks as if the
> above should work, but it's probably best to test it a little more
> widely to make sure we're not running into cases where it breaks.
AFAICS the spec says we shouldn't use a repeated start for writes.
I guess it might work for some devices, but going against the spec
sounds questionable to me.
>
> Have you by any chance verified that it works on your hardware?
>
> Thierry
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2016-12-05 13:31 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-02 19:24 [PATCH v2 1/3] drm: Add SCDC helpers Thierry Reding
2016-12-02 19:24 ` [PATCH v2 2/3] drm/edid: Implement SCDC support detection Thierry Reding
2016-12-03 4:35 ` Sharma, Shashank
2016-12-05 7:57 ` Thierry Reding
2016-12-05 8:16 ` Daniel Vetter
2016-12-05 11:11 ` Thierry Reding
2016-12-05 13:35 ` Ville Syrjälä
2016-12-05 16:21 ` Daniel Vetter
2016-12-05 17:11 ` Thierry Reding
2016-12-06 8:19 ` Daniel Vetter
2016-12-07 19:23 ` Jani Nikula
2016-12-19 8:15 ` Sharma, Shashank
2016-12-02 19:24 ` [PATCH v2 3/3] drm/edid: Implement SCDC Read Request capability detection Thierry Reding
2016-12-05 11:06 ` Jose Abreu
2016-12-05 11:14 ` Thierry Reding
2016-12-05 14:19 ` Jose Abreu
2016-12-05 16:37 ` Thierry Reding
2016-12-06 8:23 ` Daniel Vetter
2016-12-06 10:32 ` Jose Abreu
2016-12-05 10:12 ` [PATCH v2 1/3] drm: Add SCDC helpers Jose Abreu
2016-12-05 11:16 ` Thierry Reding
2016-12-05 13:31 ` Ville Syrjälä [this message]
2016-12-05 14:10 ` Jose Abreu
[not found] <20161202192249.16022-1-thierry.reding@gmail.com>
[not found] ` <e3270a0c-e03e-9314-71e1-92da2e3a54e8@intel.com>
2016-12-19 13:35 ` Sharma, Shashank
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