* [PATCH 0/4] Add Automation Support for DP Compliance Testing (Rev 4)
@ 2017-01-17 22:57 Manasi Navare
2017-01-17 22:57 ` [PATCH 1/4] drm/i915: Add support for DP link training compliance Manasi Navare
` (3 more replies)
0 siblings, 4 replies; 17+ messages in thread
From: Manasi Navare @ 2017-01-17 22:57 UTC (permalink / raw)
To: intel-gfx, dri-devel
This series is a rebased version of the previous series:
https://patchwork.freedesktop.org/series/16643/
DP 1.2 compliance testing can be acheived using DPR-120's CTS suite.
This compliance unit sends a short pulse to initiate link training
and video pattern generation compliance tests and sends a long pulse
to initate EDID compliance tests. It also sets the AUTOMATED TEST REQUEST
bit in Device IRQ to 1. These patches add support in the kernel to respond
to these test requests sent by DPR-120. The test handler has been added for
Link training/EDID and Video pattern compliance tests that gets invoked on
short/long pulse sent by DPR-120. The test handler for each of the tests
reads the corresponding DPCD registers to read the test parameters.
These tests need to be run with the IGT DP compliance automation tool.
Link Training Tests (4.3.1.1 - 4.3.2.3):
It reads the DPCD registers to get the link rate and lane count requested by
test and sends a hotplug uevent for the userspace to redo a modeset in order
to train the link at the requested test parameters.
EDID Tests (4.2.2.3 - 4.2.2.6):
It reads the EDID set by the DPR-120, if EDID read succeeds, it sets the
video mode to PREFERRED and sets the test_active flag. This flag wakes up
the IGT compliance tool that then fills the framebuffers and triggers a
modeset.
Video Pattern Tests (4.3.3.1):
It reads the DPCD registers to set the requested video pattern parameters.
It then sets the test active flag that wakes up the IGT tool, userspace
reads the video pattern values from corresponding debugfs files and fills the
framebuffers and triggers a modeset.
Manasi Navare (4):
drm/i915: Add support for DP link training compliance
drm/i915: Fixes to support DP Compliance EDID tests
drm: Add definitions for DP compliance Video pattern tests
drm/i915: Add support for DP Video pattern compliance tests
drivers/gpu/drm/i915/i915_debugfs.c | 14 ++++-
drivers/gpu/drm/i915/intel_dp.c | 117 ++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_dp_mst.c | 7 ++-
drivers/gpu/drm/i915/intel_drv.h | 5 ++
include/drm/drm_dp_helper.h | 58 ++++++++++++++++++
5 files changed, 193 insertions(+), 8 deletions(-)
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/4] drm/i915: Add support for DP link training compliance
2017-01-17 22:57 [PATCH 0/4] Add Automation Support for DP Compliance Testing (Rev 4) Manasi Navare
@ 2017-01-17 22:57 ` Manasi Navare
2017-01-18 17:29 ` Manasi Navare
2017-01-19 15:51 ` Jani Nikula
2017-01-17 22:57 ` [PATCH 2/4] drm/i915: Fixes to support DP Compliance EDID tests Manasi Navare
` (2 subsequent siblings)
3 siblings, 2 replies; 17+ messages in thread
From: Manasi Navare @ 2017-01-17 22:57 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Daniel Vetter
This patch adds support to handle automated DP compliance
link training test requests. This patch has been tested with
Unigraf DPR-120 DP Compliance device for testing Link
Training Compliance.
After we get a short pulse Compliance test request, test
request values are read and hotplug uevent is sent in order
to trigger another modeset during which the pipe is configured
and link is retrained and enabled for link parameters requested
by the test.
v2:
* Validate the test lane count before using it in
intel_dp_compute_config (Jani Nikula)
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 46 ++++++++++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/intel_drv.h | 2 ++
2 files changed, 44 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e80d620..7a1d3c4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1613,6 +1613,7 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
/* Conveniently, the link BW constants become indices with a shift...*/
int min_clock = 0;
int max_clock;
+ int link_rate_index;
int bpp, mode_rate;
int link_avail, link_clock;
int common_rates[DP_MAX_SUPPORTED_RATES] = {};
@@ -1654,6 +1655,17 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
return false;
+ /* Use values requested by Compliance Test Request */
+ if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
+ link_rate_index = intel_dp_link_rate_index(intel_dp,
+ common_rates,
+ drm_dp_bw_code_to_link_rate(intel_dp->compliance.test_link_rate));
+ if (link_rate_index >= 0)
+ min_clock = max_clock = link_rate_index;
+ if (min_lane_count <= intel_dp->compliance.test_lane_count
+ && intel_dp->compliance.test_lane_count >= max_lane_count)
+ min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
+ }
DRM_DEBUG_KMS("DP link computation with max lane count %i "
"max bw %d pixel clock %iKHz\n",
max_lane_count, common_rates[max_clock],
@@ -3921,6 +3933,27 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
{
uint8_t test_result = DP_TEST_ACK;
+ int status = 0;
+ /* (DP CTS 1.2)
+ * 4.3.1.11
+ */
+ /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
+ status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
+ &intel_dp->compliance.test_lane_count);
+
+ if (status <= 0) {
+ DRM_DEBUG_KMS("Lane count read failed\n");
+ return 0;
+ }
+ intel_dp->compliance.test_lane_count &= DP_MAX_LANE_COUNT_MASK;
+
+ status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
+ &intel_dp->compliance.test_link_rate);
+ if (status <= 0) {
+ DRM_DEBUG_KMS("Link Rate read failed\n");
+ return 0;
+ }
+
return test_result;
}
@@ -4135,9 +4168,8 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
if (!intel_dp->lane_count)
return;
- /* if link training is requested we should perform it always */
- if ((intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) ||
- (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
+ /* Retrain if Channel EQ or CR not ok */
+ if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
intel_encoder->base.name);
@@ -4162,6 +4194,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
intel_dp_short_pulse(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
u8 sink_irq_vector = 0;
u8 old_sink_count = intel_dp->sink_count;
bool ret;
@@ -4195,7 +4228,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
sink_irq_vector);
if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
- DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
+ intel_dp_handle_test_request(intel_dp);
if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
}
@@ -4203,6 +4236,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
intel_dp_check_link_status(intel_dp);
drm_modeset_unlock(&dev->mode_config.connection_mutex);
+ if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
+ DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
+ /* Send a Hotplug Uevent to userspace to start modeset */
+ drm_kms_helper_hotplug_event(intel_encoder->base.dev);
+ }
return true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 84258df..7a2eb76 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -893,6 +893,8 @@ struct intel_dp_compliance {
unsigned long test_type;
struct intel_dp_compliance_data test_data;
bool test_active;
+ u8 test_link_rate;
+ u8 test_lane_count;
};
struct intel_dp {
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/4] drm/i915: Fixes to support DP Compliance EDID tests
2017-01-17 22:57 [PATCH 0/4] Add Automation Support for DP Compliance Testing (Rev 4) Manasi Navare
2017-01-17 22:57 ` [PATCH 1/4] drm/i915: Add support for DP link training compliance Manasi Navare
@ 2017-01-17 22:57 ` Manasi Navare
2017-01-18 17:32 ` Manasi Navare
2017-01-17 22:57 ` [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests Manasi Navare
2017-01-17 22:57 ` [PATCH 4/4] drm/i915: Add support for DP Video pattern compliance tests Manasi Navare
3 siblings, 1 reply; 17+ messages in thread
From: Manasi Navare @ 2017-01-17 22:57 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Manasi Navare, Daniel Vetter
This patch addresses a few issues from the original patch for
DP Compliance EDID test support submitted by
Todd Previte<todd.previte@gmail.com>
Video Mode requested in the EDID test handler for the EDID Read
test (CTS 4.2.2.3) should be set to PREFERRED as per the CTS spec.
v2:
* Added read debugfs data from test_data.edid if its EDID test (Jani NIkula)
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++++-
drivers/gpu/drm/i915/intel_dp.c | 4 ++--
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 01fdbbf..d493978 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3737,7 +3737,10 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data)
if (connector->status == connector_status_connected &&
connector->encoder != NULL) {
intel_dp = enc_to_intel_dp(connector->encoder);
- seq_printf(m, "%lx", intel_dp->compliance.test_data.edid);
+ if (intel_dp->compliance.test_type ==
+ DP_TEST_LINK_EDID_READ)
+ seq_printf(m, "%lx",
+ intel_dp->compliance.test_data.edid);
} else
seq_puts(m, "0");
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7a1d3c4..11c902e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3965,7 +3965,7 @@ static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
{
- uint8_t test_result = DP_TEST_NAK;
+ uint8_t test_result = DP_TEST_ACK;
struct intel_connector *intel_connector = intel_dp->attached_connector;
struct drm_connector *connector = &intel_connector->base;
@@ -4000,7 +4000,7 @@ static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("Failed to write EDID checksum\n");
test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
- intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_STANDARD;
+ intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
}
/* Set test active flag here so userspace doesn't interrupt things */
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests
2017-01-17 22:57 [PATCH 0/4] Add Automation Support for DP Compliance Testing (Rev 4) Manasi Navare
2017-01-17 22:57 ` [PATCH 1/4] drm/i915: Add support for DP link training compliance Manasi Navare
2017-01-17 22:57 ` [PATCH 2/4] drm/i915: Fixes to support DP Compliance EDID tests Manasi Navare
@ 2017-01-17 22:57 ` Manasi Navare
2017-01-18 17:35 ` Manasi Navare
2017-01-19 13:31 ` Jani Nikula
2017-01-17 22:57 ` [PATCH 4/4] drm/i915: Add support for DP Video pattern compliance tests Manasi Navare
3 siblings, 2 replies; 17+ messages in thread
From: Manasi Navare @ 2017-01-17 22:57 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Daniel Vetter
v2:
* Add all the other DP Complianec TEST register defs (Jani Nikula)
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
include/drm/drm_dp_helper.h | 58 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 0468135..ff03f8a 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -417,6 +417,64 @@
#define DP_TEST_LANE_COUNT 0x220
#define DP_TEST_PATTERN 0x221
+# define DP_NO_TEST_PATTERN (0x0)
+# define DP_COLOR_RAMP (0x1)
+# define DP_BLACK_AND_WHITE_VERTICAL_LINES (0x2)
+# define DP_COLOR_SQUARE (0x3)
+
+#define DP_TEST_H_TOTAL_HI 0x222
+#define DP_TEST_H_TOTAl_LO 0x223
+
+#define DP_TEST_V_TOTAL_HI 0x224
+#define DP_TEST_V_TOTAl_LO 0x225
+
+#define DP_TEST_H_START_HI 0x226
+#define DP_TEST_H_START_LO 0x227
+
+#define DP_TEST_V_START_HI 0x228
+#define DP_TEST_V_START_LO 0x229
+
+#define DP_TEST_HSYNC_HI 0x22A
+#define DP_TEST_HSYNC_LO 0x22B
+
+#define DP_TEST_VSYNC_HI 0x22C
+#define DP_TEST_VSYNC_LO 0x22D
+
+#define DP_TEST_H_WIDTH_HI 0x22E
+#define DP_TESt_H_WIDTH_LO 0x22F
+
+#define DP_TEST_V_HEIGHT_HI 0x230
+#define DP_TEST_V_HEIGHT_LO 0x231
+
+#define DP_TEST_MISC_LO 0x232
+# define DP_TEST_SYNC_CLOCK_MASK (1 << 0)
+# define DP_CLOCK_ASYNC (0x0)
+# define DP_CLOCK_SYNC (0x1)
+# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
+# define DP_TEST_COLOR_FORMAT_SHIFT 1
+# define DP_COLOR_FORMAT_RGB (0x0)
+# define DP_COLOR_FORMAT_YCbCr422 (0x1)
+# define DP_COLOR_FORMAT_YCbCr444 (0x2)
+# define DP_TEST_DYNAMIC_RANGE_MASK (1 << 3)
+# define DP_TEST_DYNAMIC_RANGE_SHIFT 3
+# define DP_VESA_RANGE (0x0)
+# define DP_CEA_RANGE (0x1)
+# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
+# define DP_TEST_BIT_DEPTH_SHIFT 5
+# define DP_TEST_BIT_DEPTH_6 (0x0)
+# define DP_TEST_BIT_DEPTH_8 (0x1)
+# define DP_TEST_BIT_DEPTH_10 (0x2)
+# define DP_TEST_BIT_DEPTH_12 (0x3)
+# define DP_TEST_BIT_DEPTH_16 (0x4)
+#define DP_TEST_MISC_HI 0x233
+# define DP_TEST_REFRESH_DENOMINATOR_MASK (1 << 0)
+# define REFRESH_DENOMINATOR_1 (0x0)
+# define REFRESH_DENOMINATOR_1_001 (0x1)
+# define DP_TEST_INTERLACED_MASK (1 << 1)
+# define DP_NON_INTERLACED (0x0)
+# define DP_INTERLACED (0x1)
+
+#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
#define DP_TEST_CRC_R_CR 0x240
#define DP_TEST_CRC_G_Y 0x242
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/4] drm/i915: Add support for DP Video pattern compliance tests
2017-01-17 22:57 [PATCH 0/4] Add Automation Support for DP Compliance Testing (Rev 4) Manasi Navare
` (2 preceding siblings ...)
2017-01-17 22:57 ` [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests Manasi Navare
@ 2017-01-17 22:57 ` Manasi Navare
2017-01-18 17:37 ` Manasi Navare
3 siblings, 1 reply; 17+ messages in thread
From: Manasi Navare @ 2017-01-17 22:57 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Manasi Navare, Daniel Vetter
The intel_dp_autotest_video_pattern() function gets invoked through the
compliance test handler on a HPD short pulse if the test type is
set to DP_TEST_VIDEO_PATTERN. This performs the DPCD registers
reads to read the requested test pattern, video pattern resolution,
frame rate and bits per color value. The results of this analysis
are handed off to userspace so that the userspace app can set the
video pattern mode appropriately for the test result/response.
When the test is requested with specific BPC value, we read the BPC
value from the DPCD register. If this BPC value in intel_dp structure
has a non-zero value and we're on a display port connector, then we use
the value to calculate the bpp for the pipe.
The compliance_test_active flag is set at the end of the individual
test handling functions. This is so that the kernel-side operations
can be completed without the risk of interruption from the userspace
app that is polling on that flag.
v2:
* Updated the DPCD Register reads based on proper defines in header (Jani Nikula)
* Squahsed the patch that forced the pipe bpp to compliance test bpp (Jani Nikula)
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 +++++
drivers/gpu/drm/i915/intel_dp.c | 67 +++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dp_mst.c | 7 +++-
drivers/gpu/drm/i915/intel_drv.h | 3 ++
4 files changed, 85 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d493978..a5959c2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3741,6 +3741,15 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data)
DP_TEST_LINK_EDID_READ)
seq_printf(m, "%lx",
intel_dp->compliance.test_data.edid);
+ else if (intel_dp->compliance.test_type ==
+ DP_TEST_LINK_VIDEO_PATTERN) {
+ seq_printf(m, "hdisplay: %d\n",
+ intel_dp->compliance.test_data.hdisplay);
+ seq_printf(m, "vdisplay: %d\n",
+ intel_dp->compliance.test_data.vdisplay);
+ seq_printf(m, "bpc: %u\n",
+ intel_dp->compliance.test_data.bpc);
+ }
} else
seq_puts(m, "0");
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 11c902e..09fa8cb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -28,8 +28,10 @@
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/export.h>
+#include <linux/types.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
+#include <asm/byteorder.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
@@ -1593,6 +1595,12 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
if (bpc > 0)
bpp = min(bpp, 3*bpc);
+ /* For DP Compliance we override the computed bpp for the pipe */
+ if (intel_dp->compliance.test_data.bpc != 0) {
+ pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
+ DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
+ pipe_config->pipe_bpp);
+ }
return bpp;
}
@@ -3960,6 +3968,65 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
{
uint8_t test_result = DP_TEST_NAK;
+ uint8_t test_pattern;
+ uint16_t test_misc;
+ __be16 h_width, v_height;
+ int status = 0;
+
+ /* Read the TEST_PATTERN (DP CTS 3.1.5) */
+ status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_PATTERN,
+ &test_pattern, 1);
+ if (status <= 0) {
+ DRM_DEBUG_KMS("Test pattern read failed\n");
+ return 0;
+ }
+ if (test_pattern != DP_COLOR_RAMP)
+ return test_result;
+ intel_dp->compliance.test_data.video_pattern = test_pattern;
+
+ status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
+ &h_width, 2);
+ if (status <= 0) {
+ DRM_DEBUG_KMS("H Width read failed\n");
+ return 0;
+ }
+ intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
+
+ status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
+ &v_height, 2);
+ if (status <= 0) {
+ DRM_DEBUG_KMS("V Height read failed\n");
+ return 0;
+ }
+ intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
+
+ status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_MISC_LO,
+ &test_misc, 1);
+ if (status <= 0) {
+ DRM_DEBUG_KMS("TEST MISC read failed\n");
+ return 0;
+ }
+ if (((test_misc & DP_TEST_COLOR_FORMAT_MASK) >> DP_TEST_COLOR_FORMAT_SHIFT) !=
+ DP_COLOR_FORMAT_RGB)
+ return test_result;
+ if (((test_misc & DP_TEST_DYNAMIC_RANGE_MASK) >> DP_TEST_DYNAMIC_RANGE_SHIFT) !=
+ DP_VESA_RANGE)
+ return test_result;
+ switch ((test_misc & DP_TEST_BIT_DEPTH_MASK) >> DP_TEST_BIT_DEPTH_SHIFT) {
+ case DP_TEST_BIT_DEPTH_6:
+ intel_dp->compliance.test_data.bpc = 6;
+ break;
+ case DP_TEST_BIT_DEPTH_8:
+ intel_dp->compliance.test_data.bpc = 8;
+ break;
+ default:
+ return test_result;
+ }
+ /* Set test active flag here so userspace doesn't interrupt things */
+ intel_dp->compliance.test_active = 1;
+
+ test_result = DP_TEST_ACK;
+
return test_result;
}
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 205fe47..29a9af1 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -47,6 +47,11 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
pipe_config->has_pch_encoder = false;
bpp = 24;
+ if (intel_dp->compliance.test_data.bpc) {
+ bpp = intel_dp->compliance.test_data.bpc * 3;
+ DRM_DEBUG_KMS("Setting pipe bpp to %d\n",
+ bpp);
+ }
/*
* for MST we always configure max link bw - the spec doesn't
* seem to suggest we should do otherwise.
@@ -55,7 +60,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
pipe_config->lane_count = lane_count;
- pipe_config->pipe_bpp = 24;
+ pipe_config->pipe_bpp = bpp;
pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);
state = pipe_config->base.state;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7a2eb76..1f94382 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -887,6 +887,9 @@ struct intel_dp_desc {
struct intel_dp_compliance_data {
unsigned long edid;
+ uint8_t video_pattern;
+ uint16_t hdisplay, vdisplay;
+ uint8_t bpc;
};
struct intel_dp_compliance {
--
1.9.1
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^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] drm/i915: Add support for DP link training compliance
2017-01-17 22:57 ` [PATCH 1/4] drm/i915: Add support for DP link training compliance Manasi Navare
@ 2017-01-18 17:29 ` Manasi Navare
2017-01-19 15:51 ` Jani Nikula
1 sibling, 0 replies; 17+ messages in thread
From: Manasi Navare @ 2017-01-18 17:29 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Daniel Vetter
Hi Jani,
Could you please review this patch?
I have added the lane count checking and other review comments you had.
Is there anything else that is blocking from getting this patch merged?
Regards
Manasi
On Tue, Jan 17, 2017 at 02:57:12PM -0800, Manasi Navare wrote:
> This patch adds support to handle automated DP compliance
> link training test requests. This patch has been tested with
> Unigraf DPR-120 DP Compliance device for testing Link
> Training Compliance.
> After we get a short pulse Compliance test request, test
> request values are read and hotplug uevent is sent in order
> to trigger another modeset during which the pipe is configured
> and link is retrained and enabled for link parameters requested
> by the test.
>
> v2:
> * Validate the test lane count before using it in
> intel_dp_compute_config (Jani Nikula)
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 46 ++++++++++++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 2 files changed, 44 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e80d620..7a1d3c4 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1613,6 +1613,7 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
> /* Conveniently, the link BW constants become indices with a shift...*/
> int min_clock = 0;
> int max_clock;
> + int link_rate_index;
> int bpp, mode_rate;
> int link_avail, link_clock;
> int common_rates[DP_MAX_SUPPORTED_RATES] = {};
> @@ -1654,6 +1655,17 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> return false;
>
> + /* Use values requested by Compliance Test Request */
> + if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
> + link_rate_index = intel_dp_link_rate_index(intel_dp,
> + common_rates,
> + drm_dp_bw_code_to_link_rate(intel_dp->compliance.test_link_rate));
> + if (link_rate_index >= 0)
> + min_clock = max_clock = link_rate_index;
> + if (min_lane_count <= intel_dp->compliance.test_lane_count
> + && intel_dp->compliance.test_lane_count >= max_lane_count)
> + min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
> + }
> DRM_DEBUG_KMS("DP link computation with max lane count %i "
> "max bw %d pixel clock %iKHz\n",
> max_lane_count, common_rates[max_clock],
> @@ -3921,6 +3933,27 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
> static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
> {
> uint8_t test_result = DP_TEST_ACK;
> + int status = 0;
> + /* (DP CTS 1.2)
> + * 4.3.1.11
> + */
> + /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
> + status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
> + &intel_dp->compliance.test_lane_count);
> +
> + if (status <= 0) {
> + DRM_DEBUG_KMS("Lane count read failed\n");
> + return 0;
> + }
> + intel_dp->compliance.test_lane_count &= DP_MAX_LANE_COUNT_MASK;
> +
> + status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
> + &intel_dp->compliance.test_link_rate);
> + if (status <= 0) {
> + DRM_DEBUG_KMS("Link Rate read failed\n");
> + return 0;
> + }
> +
> return test_result;
> }
>
> @@ -4135,9 +4168,8 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
> if (!intel_dp->lane_count)
> return;
>
> - /* if link training is requested we should perform it always */
> - if ((intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) ||
> - (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
> + /* Retrain if Channel EQ or CR not ok */
> + if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
> DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
> intel_encoder->base.name);
>
> @@ -4162,6 +4194,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
> intel_dp_short_pulse(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
> u8 sink_irq_vector = 0;
> u8 old_sink_count = intel_dp->sink_count;
> bool ret;
> @@ -4195,7 +4228,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
> sink_irq_vector);
>
> if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
> - DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
> + intel_dp_handle_test_request(intel_dp);
> if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
> DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
> }
> @@ -4203,6 +4236,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
> drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
> intel_dp_check_link_status(intel_dp);
> drm_modeset_unlock(&dev->mode_config.connection_mutex);
> + if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
> + DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
> + /* Send a Hotplug Uevent to userspace to start modeset */
> + drm_kms_helper_hotplug_event(intel_encoder->base.dev);
> + }
>
> return true;
> }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 84258df..7a2eb76 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -893,6 +893,8 @@ struct intel_dp_compliance {
> unsigned long test_type;
> struct intel_dp_compliance_data test_data;
> bool test_active;
> + u8 test_link_rate;
> + u8 test_lane_count;
> };
>
> struct intel_dp {
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/4] drm/i915: Fixes to support DP Compliance EDID tests
2017-01-17 22:57 ` [PATCH 2/4] drm/i915: Fixes to support DP Compliance EDID tests Manasi Navare
@ 2017-01-18 17:32 ` Manasi Navare
0 siblings, 0 replies; 17+ messages in thread
From: Manasi Navare @ 2017-01-18 17:32 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Daniel Vetter
Hi Jani,
This is another simple patch that only changed EDID test to
PREFERRED vs STANDARD as per the CTS spec. Is there anything else
that is blocking this patch getting merged?
Regards
Manasi
On Tue, Jan 17, 2017 at 02:57:13PM -0800, Manasi Navare wrote:
> This patch addresses a few issues from the original patch for
> DP Compliance EDID test support submitted by
> Todd Previte<todd.previte@gmail.com>
>
> Video Mode requested in the EDID test handler for the EDID Read
> test (CTS 4.2.2.3) should be set to PREFERRED as per the CTS spec.
>
> v2:
> * Added read debugfs data from test_data.edid if its EDID test (Jani NIkula)
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 5 ++++-
> drivers/gpu/drm/i915/intel_dp.c | 4 ++--
> 2 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 01fdbbf..d493978 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3737,7 +3737,10 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data)
> if (connector->status == connector_status_connected &&
> connector->encoder != NULL) {
> intel_dp = enc_to_intel_dp(connector->encoder);
> - seq_printf(m, "%lx", intel_dp->compliance.test_data.edid);
> + if (intel_dp->compliance.test_type ==
> + DP_TEST_LINK_EDID_READ)
> + seq_printf(m, "%lx",
> + intel_dp->compliance.test_data.edid);
> } else
> seq_puts(m, "0");
> }
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 7a1d3c4..11c902e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3965,7 +3965,7 @@ static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
>
> static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
> {
> - uint8_t test_result = DP_TEST_NAK;
> + uint8_t test_result = DP_TEST_ACK;
> struct intel_connector *intel_connector = intel_dp->attached_connector;
> struct drm_connector *connector = &intel_connector->base;
>
> @@ -4000,7 +4000,7 @@ static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
> DRM_DEBUG_KMS("Failed to write EDID checksum\n");
>
> test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
> - intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_STANDARD;
> + intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
> }
>
> /* Set test active flag here so userspace doesn't interrupt things */
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests
2017-01-17 22:57 ` [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests Manasi Navare
@ 2017-01-18 17:35 ` Manasi Navare
2017-01-19 13:31 ` Jani Nikula
1 sibling, 0 replies; 17+ messages in thread
From: Manasi Navare @ 2017-01-18 17:35 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Daniel Vetter
Hi Jani,
I have added all the video pattern definitions from CTS
spec following the definition conventions used around this file.
This addresses all the review comments from you, is there anything else
that is blocking this patch from getting merged? Could you please review this patch?
Regards
Manasi
On Tue, Jan 17, 2017 at 02:57:14PM -0800, Manasi Navare wrote:
> v2:
> * Add all the other DP Complianec TEST register defs (Jani Nikula)
> Cc: dri-devel@lists.freedesktop.org
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> include/drm/drm_dp_helper.h | 58 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 0468135..ff03f8a 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -417,6 +417,64 @@
> #define DP_TEST_LANE_COUNT 0x220
>
> #define DP_TEST_PATTERN 0x221
> +# define DP_NO_TEST_PATTERN (0x0)
> +# define DP_COLOR_RAMP (0x1)
> +# define DP_BLACK_AND_WHITE_VERTICAL_LINES (0x2)
> +# define DP_COLOR_SQUARE (0x3)
> +
> +#define DP_TEST_H_TOTAL_HI 0x222
> +#define DP_TEST_H_TOTAl_LO 0x223
> +
> +#define DP_TEST_V_TOTAL_HI 0x224
> +#define DP_TEST_V_TOTAl_LO 0x225
> +
> +#define DP_TEST_H_START_HI 0x226
> +#define DP_TEST_H_START_LO 0x227
> +
> +#define DP_TEST_V_START_HI 0x228
> +#define DP_TEST_V_START_LO 0x229
> +
> +#define DP_TEST_HSYNC_HI 0x22A
> +#define DP_TEST_HSYNC_LO 0x22B
> +
> +#define DP_TEST_VSYNC_HI 0x22C
> +#define DP_TEST_VSYNC_LO 0x22D
> +
> +#define DP_TEST_H_WIDTH_HI 0x22E
> +#define DP_TESt_H_WIDTH_LO 0x22F
> +
> +#define DP_TEST_V_HEIGHT_HI 0x230
> +#define DP_TEST_V_HEIGHT_LO 0x231
> +
> +#define DP_TEST_MISC_LO 0x232
> +# define DP_TEST_SYNC_CLOCK_MASK (1 << 0)
> +# define DP_CLOCK_ASYNC (0x0)
> +# define DP_CLOCK_SYNC (0x1)
> +# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
> +# define DP_TEST_COLOR_FORMAT_SHIFT 1
> +# define DP_COLOR_FORMAT_RGB (0x0)
> +# define DP_COLOR_FORMAT_YCbCr422 (0x1)
> +# define DP_COLOR_FORMAT_YCbCr444 (0x2)
> +# define DP_TEST_DYNAMIC_RANGE_MASK (1 << 3)
> +# define DP_TEST_DYNAMIC_RANGE_SHIFT 3
> +# define DP_VESA_RANGE (0x0)
> +# define DP_CEA_RANGE (0x1)
> +# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
> +# define DP_TEST_BIT_DEPTH_SHIFT 5
> +# define DP_TEST_BIT_DEPTH_6 (0x0)
> +# define DP_TEST_BIT_DEPTH_8 (0x1)
> +# define DP_TEST_BIT_DEPTH_10 (0x2)
> +# define DP_TEST_BIT_DEPTH_12 (0x3)
> +# define DP_TEST_BIT_DEPTH_16 (0x4)
> +#define DP_TEST_MISC_HI 0x233
> +# define DP_TEST_REFRESH_DENOMINATOR_MASK (1 << 0)
> +# define REFRESH_DENOMINATOR_1 (0x0)
> +# define REFRESH_DENOMINATOR_1_001 (0x1)
> +# define DP_TEST_INTERLACED_MASK (1 << 1)
> +# define DP_NON_INTERLACED (0x0)
> +# define DP_INTERLACED (0x1)
> +
> +#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
>
> #define DP_TEST_CRC_R_CR 0x240
> #define DP_TEST_CRC_G_Y 0x242
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/4] drm/i915: Add support for DP Video pattern compliance tests
2017-01-17 22:57 ` [PATCH 4/4] drm/i915: Add support for DP Video pattern compliance tests Manasi Navare
@ 2017-01-18 17:37 ` Manasi Navare
0 siblings, 0 replies; 17+ messages in thread
From: Manasi Navare @ 2017-01-18 17:37 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Daniel Vetter
Hi Jani,
Could you please review this patch? All your previous review comments
are addressed. Is there anything else that is blocking this patch from getting
merged?
Regards
Manasi
On Tue, Jan 17, 2017 at 02:57:15PM -0800, Manasi Navare wrote:
> The intel_dp_autotest_video_pattern() function gets invoked through the
> compliance test handler on a HPD short pulse if the test type is
> set to DP_TEST_VIDEO_PATTERN. This performs the DPCD registers
> reads to read the requested test pattern, video pattern resolution,
> frame rate and bits per color value. The results of this analysis
> are handed off to userspace so that the userspace app can set the
> video pattern mode appropriately for the test result/response.
> When the test is requested with specific BPC value, we read the BPC
> value from the DPCD register. If this BPC value in intel_dp structure
> has a non-zero value and we're on a display port connector, then we use
> the value to calculate the bpp for the pipe.
>
> The compliance_test_active flag is set at the end of the individual
> test handling functions. This is so that the kernel-side operations
> can be completed without the risk of interruption from the userspace
> app that is polling on that flag.
>
> v2:
> * Updated the DPCD Register reads based on proper defines in header (Jani Nikula)
> * Squahsed the patch that forced the pipe bpp to compliance test bpp (Jani Nikula)
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 9 +++++
> drivers/gpu/drm/i915/intel_dp.c | 67 +++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_dp_mst.c | 7 +++-
> drivers/gpu/drm/i915/intel_drv.h | 3 ++
> 4 files changed, 85 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index d493978..a5959c2 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3741,6 +3741,15 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data)
> DP_TEST_LINK_EDID_READ)
> seq_printf(m, "%lx",
> intel_dp->compliance.test_data.edid);
> + else if (intel_dp->compliance.test_type ==
> + DP_TEST_LINK_VIDEO_PATTERN) {
> + seq_printf(m, "hdisplay: %d\n",
> + intel_dp->compliance.test_data.hdisplay);
> + seq_printf(m, "vdisplay: %d\n",
> + intel_dp->compliance.test_data.vdisplay);
> + seq_printf(m, "bpc: %u\n",
> + intel_dp->compliance.test_data.bpc);
> + }
> } else
> seq_puts(m, "0");
> }
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 11c902e..09fa8cb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -28,8 +28,10 @@
> #include <linux/i2c.h>
> #include <linux/slab.h>
> #include <linux/export.h>
> +#include <linux/types.h>
> #include <linux/notifier.h>
> #include <linux/reboot.h>
> +#include <asm/byteorder.h>
> #include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_crtc.h>
> @@ -1593,6 +1595,12 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
> if (bpc > 0)
> bpp = min(bpp, 3*bpc);
>
> + /* For DP Compliance we override the computed bpp for the pipe */
> + if (intel_dp->compliance.test_data.bpc != 0) {
> + pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
> + DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
> + pipe_config->pipe_bpp);
> + }
> return bpp;
> }
>
> @@ -3960,6 +3968,65 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
> static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
> {
> uint8_t test_result = DP_TEST_NAK;
> + uint8_t test_pattern;
> + uint16_t test_misc;
> + __be16 h_width, v_height;
> + int status = 0;
> +
> + /* Read the TEST_PATTERN (DP CTS 3.1.5) */
> + status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_PATTERN,
> + &test_pattern, 1);
> + if (status <= 0) {
> + DRM_DEBUG_KMS("Test pattern read failed\n");
> + return 0;
> + }
> + if (test_pattern != DP_COLOR_RAMP)
> + return test_result;
> + intel_dp->compliance.test_data.video_pattern = test_pattern;
> +
> + status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
> + &h_width, 2);
> + if (status <= 0) {
> + DRM_DEBUG_KMS("H Width read failed\n");
> + return 0;
> + }
> + intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
> +
> + status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
> + &v_height, 2);
> + if (status <= 0) {
> + DRM_DEBUG_KMS("V Height read failed\n");
> + return 0;
> + }
> + intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
> +
> + status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_MISC_LO,
> + &test_misc, 1);
> + if (status <= 0) {
> + DRM_DEBUG_KMS("TEST MISC read failed\n");
> + return 0;
> + }
> + if (((test_misc & DP_TEST_COLOR_FORMAT_MASK) >> DP_TEST_COLOR_FORMAT_SHIFT) !=
> + DP_COLOR_FORMAT_RGB)
> + return test_result;
> + if (((test_misc & DP_TEST_DYNAMIC_RANGE_MASK) >> DP_TEST_DYNAMIC_RANGE_SHIFT) !=
> + DP_VESA_RANGE)
> + return test_result;
> + switch ((test_misc & DP_TEST_BIT_DEPTH_MASK) >> DP_TEST_BIT_DEPTH_SHIFT) {
> + case DP_TEST_BIT_DEPTH_6:
> + intel_dp->compliance.test_data.bpc = 6;
> + break;
> + case DP_TEST_BIT_DEPTH_8:
> + intel_dp->compliance.test_data.bpc = 8;
> + break;
> + default:
> + return test_result;
> + }
> + /* Set test active flag here so userspace doesn't interrupt things */
> + intel_dp->compliance.test_active = 1;
> +
> + test_result = DP_TEST_ACK;
> +
> return test_result;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 205fe47..29a9af1 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -47,6 +47,11 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>
> pipe_config->has_pch_encoder = false;
> bpp = 24;
> + if (intel_dp->compliance.test_data.bpc) {
> + bpp = intel_dp->compliance.test_data.bpc * 3;
> + DRM_DEBUG_KMS("Setting pipe bpp to %d\n",
> + bpp);
> + }
> /*
> * for MST we always configure max link bw - the spec doesn't
> * seem to suggest we should do otherwise.
> @@ -55,7 +60,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>
> pipe_config->lane_count = lane_count;
>
> - pipe_config->pipe_bpp = 24;
> + pipe_config->pipe_bpp = bpp;
> pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);
>
> state = pipe_config->base.state;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 7a2eb76..1f94382 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -887,6 +887,9 @@ struct intel_dp_desc {
>
> struct intel_dp_compliance_data {
> unsigned long edid;
> + uint8_t video_pattern;
> + uint16_t hdisplay, vdisplay;
> + uint8_t bpc;
> };
>
> struct intel_dp_compliance {
> --
> 1.9.1
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests
2017-01-17 22:57 ` [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests Manasi Navare
2017-01-18 17:35 ` Manasi Navare
@ 2017-01-19 13:31 ` Jani Nikula
1 sibling, 0 replies; 17+ messages in thread
From: Jani Nikula @ 2017-01-19 13:31 UTC (permalink / raw)
To: Manasi Navare, intel-gfx, dri-devel; +Cc: Daniel Vetter
On Wed, 18 Jan 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> v2:
> * Add all the other DP Complianec TEST register defs (Jani Nikula)
> Cc: dri-devel@lists.freedesktop.org
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> include/drm/drm_dp_helper.h | 58 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 0468135..ff03f8a 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -417,6 +417,64 @@
> #define DP_TEST_LANE_COUNT 0x220
>
> #define DP_TEST_PATTERN 0x221
> +# define DP_NO_TEST_PATTERN (0x0)
> +# define DP_COLOR_RAMP (0x1)
> +# define DP_BLACK_AND_WHITE_VERTICAL_LINES (0x2)
> +# define DP_COLOR_SQUARE (0x3)
The braces are unnecessary.
> +
> +#define DP_TEST_H_TOTAL_HI 0x222
> +#define DP_TEST_H_TOTAl_LO 0x223
> +
> +#define DP_TEST_V_TOTAL_HI 0x224
> +#define DP_TEST_V_TOTAl_LO 0x225
> +
> +#define DP_TEST_H_START_HI 0x226
> +#define DP_TEST_H_START_LO 0x227
> +
> +#define DP_TEST_V_START_HI 0x228
> +#define DP_TEST_V_START_LO 0x229
> +
> +#define DP_TEST_HSYNC_HI 0x22A
You should add bit definitions for this, as bit 7 is polarity, and only
bits 6:0 are the hsync high order bits.
> +#define DP_TEST_HSYNC_LO 0x22B
> +
> +#define DP_TEST_VSYNC_HI 0x22C
Same as DP_TEST_HSYNC_HI.
> +#define DP_TEST_VSYNC_LO 0x22D
> +
> +#define DP_TEST_H_WIDTH_HI 0x22E
> +#define DP_TESt_H_WIDTH_LO 0x22F
^ should be T
> +
> +#define DP_TEST_V_HEIGHT_HI 0x230
> +#define DP_TEST_V_HEIGHT_LO 0x231
> +
> +#define DP_TEST_MISC_LO 0x232
The other definitions have HI and LO because they contain a 15- or
16-bit value spread across two offsets. This is not the case here. I'd
call these DP_TEST_MISC0 and DP_TEST_MISC1.
> +# define DP_TEST_SYNC_CLOCK_MASK (1 << 0)
> +# define DP_CLOCK_ASYNC (0x0)
> +# define DP_CLOCK_SYNC (0x1)
Single-bit values should just be TEST_SYNCHRONOUS_CLOCK (1 << 0). No
masks, shifts or values.
> +# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
> +# define DP_TEST_COLOR_FORMAT_SHIFT 1
> +# define DP_COLOR_FORMAT_RGB (0x0)
> +# define DP_COLOR_FORMAT_YCbCr422 (0x1)
> +# define DP_COLOR_FORMAT_YCbCr444 (0x2)
The values should be shifted to the right position,
e.g. DP_COLOR_FORMAT_RGB (0 << 1). The usage pattern would be:
if ((x & DP_TEST_COLOR_FORMAT_MASK) == DP_COLOR_FORMAT_RGB)
or
x &= ~DP_TEST_COLOR_FORMAT_MASK;
x |= DP_COLOR_FORMAT_YCbCr422;
> +# define DP_TEST_DYNAMIC_RANGE_MASK (1 << 3)
> +# define DP_TEST_DYNAMIC_RANGE_SHIFT 3
Single-bit values should just be DP_TEST_DYNAMIC_RANGE (1 << 3).
Same for all of the defines below.
BR,
Jani.
> +# define DP_VESA_RANGE (0x0)
> +# define DP_CEA_RANGE (0x1)
> +# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
> +# define DP_TEST_BIT_DEPTH_SHIFT 5
> +# define DP_TEST_BIT_DEPTH_6 (0x0)
> +# define DP_TEST_BIT_DEPTH_8 (0x1)
> +# define DP_TEST_BIT_DEPTH_10 (0x2)
> +# define DP_TEST_BIT_DEPTH_12 (0x3)
> +# define DP_TEST_BIT_DEPTH_16 (0x4)
> +#define DP_TEST_MISC_HI 0x233
> +# define DP_TEST_REFRESH_DENOMINATOR_MASK (1 << 0)
> +# define REFRESH_DENOMINATOR_1 (0x0)
> +# define REFRESH_DENOMINATOR_1_001 (0x1)
> +# define DP_TEST_INTERLACED_MASK (1 << 1)
> +# define DP_NON_INTERLACED (0x0)
> +# define DP_INTERLACED (0x1)
> +
> +#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
>
> #define DP_TEST_CRC_R_CR 0x240
> #define DP_TEST_CRC_G_Y 0x242
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] drm/i915: Add support for DP link training compliance
2017-01-17 22:57 ` [PATCH 1/4] drm/i915: Add support for DP link training compliance Manasi Navare
2017-01-18 17:29 ` Manasi Navare
@ 2017-01-19 15:51 ` Jani Nikula
1 sibling, 0 replies; 17+ messages in thread
From: Jani Nikula @ 2017-01-19 15:51 UTC (permalink / raw)
To: Manasi Navare, intel-gfx, dri-devel; +Cc: Daniel Vetter
On Wed, 18 Jan 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> This patch adds support to handle automated DP compliance
> link training test requests. This patch has been tested with
> Unigraf DPR-120 DP Compliance device for testing Link
> Training Compliance.
> After we get a short pulse Compliance test request, test
> request values are read and hotplug uevent is sent in order
> to trigger another modeset during which the pipe is configured
> and link is retrained and enabled for link parameters requested
> by the test.
>
> v2:
> * Validate the test lane count before using it in
> intel_dp_compute_config (Jani Nikula)
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 46 ++++++++++++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 2 files changed, 44 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e80d620..7a1d3c4 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1613,6 +1613,7 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
> /* Conveniently, the link BW constants become indices with a shift...*/
> int min_clock = 0;
> int max_clock;
> + int link_rate_index;
> int bpp, mode_rate;
> int link_avail, link_clock;
> int common_rates[DP_MAX_SUPPORTED_RATES] = {};
> @@ -1654,6 +1655,17 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> return false;
>
> + /* Use values requested by Compliance Test Request */
> + if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
> + link_rate_index = intel_dp_link_rate_index(intel_dp,
> + common_rates,
> + drm_dp_bw_code_to_link_rate(intel_dp->compliance.test_link_rate));
> + if (link_rate_index >= 0)
> + min_clock = max_clock = link_rate_index;
> + if (min_lane_count <= intel_dp->compliance.test_lane_count
> + && intel_dp->compliance.test_lane_count >= max_lane_count)
> + min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
> + }
Why don't we do these checks and conversions when we get the test
request, so we can NAK the request on errors?
> DRM_DEBUG_KMS("DP link computation with max lane count %i "
> "max bw %d pixel clock %iKHz\n",
> max_lane_count, common_rates[max_clock],
> @@ -3921,6 +3933,27 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
> static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
> {
> uint8_t test_result = DP_TEST_ACK;
> + int status = 0;
> + /* (DP CTS 1.2)
> + * 4.3.1.11
> + */
> + /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
> + status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
> + &intel_dp->compliance.test_lane_count);
> +
> + if (status <= 0) {
> + DRM_DEBUG_KMS("Lane count read failed\n");
> + return 0;
return DP_TEST_NAK;
> + }
> + intel_dp->compliance.test_lane_count &= DP_MAX_LANE_COUNT_MASK;
> +
> + status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
> + &intel_dp->compliance.test_link_rate);
> + if (status <= 0) {
> + DRM_DEBUG_KMS("Link Rate read failed\n");
> + return 0;
return DP_TEST_NAK;
> + }
> +
> return test_result;
Could replace this with a direct return DP_TEST_ACK without the temp
variable.
> }
>
> @@ -4135,9 +4168,8 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
> if (!intel_dp->lane_count)
> return;
>
> - /* if link training is requested we should perform it always */
> - if ((intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) ||
> - (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
> + /* Retrain if Channel EQ or CR not ok */
> + if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
> DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
> intel_encoder->base.name);
>
> @@ -4162,6 +4194,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
> intel_dp_short_pulse(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
> u8 sink_irq_vector = 0;
> u8 old_sink_count = intel_dp->sink_count;
> bool ret;
> @@ -4195,7 +4228,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
> sink_irq_vector);
>
> if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
> - DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
> + intel_dp_handle_test_request(intel_dp);
> if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
> DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
> }
> @@ -4203,6 +4236,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
> drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
> intel_dp_check_link_status(intel_dp);
> drm_modeset_unlock(&dev->mode_config.connection_mutex);
> + if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
> + DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
> + /* Send a Hotplug Uevent to userspace to start modeset */
> + drm_kms_helper_hotplug_event(intel_encoder->base.dev);
> + }
>
> return true;
> }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 84258df..7a2eb76 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -893,6 +893,8 @@ struct intel_dp_compliance {
> unsigned long test_type;
> struct intel_dp_compliance_data test_data;
> bool test_active;
> + u8 test_link_rate;
> + u8 test_lane_count;
> };
>
> struct intel_dp {
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests
2017-01-20 6:23 [PATCH 0/4] Add Automation Support for DP Compliance (Rev 5) Manasi Navare
@ 2017-01-20 6:23 ` Manasi Navare
2017-01-20 15:33 ` Jani Nikula
0 siblings, 1 reply; 17+ messages in thread
From: Manasi Navare @ 2017-01-20 6:23 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Daniel Vetter
v3:
* Fix the conventions in bit definitions (Jani Nikula)
v2:
* Add all the other DP Complianec TEST register defs (Jani Nikula)
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
include/drm/drm_dp_helper.h | 64 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 0468135..7ab4153 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -417,6 +417,70 @@
#define DP_TEST_LANE_COUNT 0x220
#define DP_TEST_PATTERN 0x221
+# define DP_NO_TEST_PATTERN 0x0
+# define DP_COLOR_RAMP 0x1
+# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
+# define DP_COLOR_SQUARE 0x3
+
+#define DP_TEST_H_TOTAL_HI 0x222
+#define DP_TEST_H_TOTAl_LO 0x223
+
+#define DP_TEST_V_TOTAL_HI 0x224
+#define DP_TEST_V_TOTAl_LO 0x225
+
+#define DP_TEST_H_START_HI 0x226
+#define DP_TEST_H_START_LO 0x227
+
+#define DP_TEST_V_START_HI 0x228
+#define DP_TEST_V_START_LO 0x229
+
+#define DP_TEST_HSYNC_HI 0x22A
+# define DP_TEST_HSYNC_POLARITY (1 << 7)
+# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
+#define DP_TEST_HSYNC_WIDTH_LO 0x22B
+
+#define DP_TEST_VSYNC_HI 0x22C
+# define DP_TEST_VSYNC_POLARITY (1 << 7)
+# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
+#define DP_TEST_VSYNC_WIDTH_LO 0x22D
+
+#define DP_TEST_H_WIDTH_HI 0x22E
+#define DP_TEST_H_WIDTH_LO 0x22F
+
+#define DP_TEST_V_HEIGHT_HI 0x230
+#define DP_TEST_V_HEIGHT_LO 0x231
+
+#define DP_TEST_MISC0 0x232
+# define DP_TEST_SYNC_CLOCK (1 << 0)
+# define DP_CLOCK_ASYNC 0x0
+# define DP_CLOCK_SYNC 0x1
+# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
+# define DP_TEST_COLOR_FORMAT_SHIFT 1
+# define DP_COLOR_FORMAT_RGB (0 << 1)
+# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
+# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
+# define DP_TEST_DYNAMIC_RANGE (1 << 3)
+# define DP_VESA_RANGE (0 << 3)
+# define DP_CEA_RANGE (1 << 3)
+# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
+# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
+# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
+# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
+# define DP_TEST_BIT_DEPTH_SHIFT 5
+# define DP_TEST_BIT_DEPTH_6 (0 << 5)
+# define DP_TEST_BIT_DEPTH_8 (1 << 5)
+# define DP_TEST_BIT_DEPTH_10 (2 << 5)
+# define DP_TEST_BIT_DEPTH_12 (3 << 5)
+# define DP_TEST_BIT_DEPTH_16 (4 << 5)
+#define DP_TEST_MISC1 0x233
+# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
+# define REFRESH_DENOMINATOR_1 0x0
+# define REFRESH_DENOMINATOR_1_001 0x1
+# define DP_TEST_INTERLACED (1 << 1)
+# define DP_NON_INTERLACED (0 << 1)
+# define DP_INTERLACED (1 << 1)
+
+#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
#define DP_TEST_CRC_R_CR 0x240
#define DP_TEST_CRC_G_Y 0x242
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests
2017-01-20 6:23 ` [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests Manasi Navare
@ 2017-01-20 15:33 ` Jani Nikula
2017-01-20 16:13 ` Manasi Navare
0 siblings, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2017-01-20 15:33 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Manasi Navare, Daniel Vetter
On Fri, 20 Jan 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> v3:
> * Fix the conventions in bit definitions (Jani Nikula)
> v2:
> * Add all the other DP Complianec TEST register defs (Jani Nikula)
> Cc: dri-devel@lists.freedesktop.org
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> include/drm/drm_dp_helper.h | 64 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 64 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 0468135..7ab4153 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -417,6 +417,70 @@
> #define DP_TEST_LANE_COUNT 0x220
>
> #define DP_TEST_PATTERN 0x221
> +# define DP_NO_TEST_PATTERN 0x0
> +# define DP_COLOR_RAMP 0x1
> +# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
> +# define DP_COLOR_SQUARE 0x3
> +
> +#define DP_TEST_H_TOTAL_HI 0x222
> +#define DP_TEST_H_TOTAl_LO 0x223
^
Sorry, didn't notice it before, but the l in TOTAL is lower case.
> +
> +#define DP_TEST_V_TOTAL_HI 0x224
> +#define DP_TEST_V_TOTAl_LO 0x225
^
Ditto.
> +
> +#define DP_TEST_H_START_HI 0x226
> +#define DP_TEST_H_START_LO 0x227
> +
> +#define DP_TEST_V_START_HI 0x228
> +#define DP_TEST_V_START_LO 0x229
> +
> +#define DP_TEST_HSYNC_HI 0x22A
> +# define DP_TEST_HSYNC_POLARITY (1 << 7)
> +# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
> +#define DP_TEST_HSYNC_WIDTH_LO 0x22B
> +
> +#define DP_TEST_VSYNC_HI 0x22C
> +# define DP_TEST_VSYNC_POLARITY (1 << 7)
> +# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
> +#define DP_TEST_VSYNC_WIDTH_LO 0x22D
> +
> +#define DP_TEST_H_WIDTH_HI 0x22E
> +#define DP_TEST_H_WIDTH_LO 0x22F
> +
> +#define DP_TEST_V_HEIGHT_HI 0x230
> +#define DP_TEST_V_HEIGHT_LO 0x231
> +
> +#define DP_TEST_MISC0 0x232
> +# define DP_TEST_SYNC_CLOCK (1 << 0)
> +# define DP_CLOCK_ASYNC 0x0
> +# define DP_CLOCK_SYNC 0x1
The above two are not necessary.
> +# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
> +# define DP_TEST_COLOR_FORMAT_SHIFT 1
> +# define DP_COLOR_FORMAT_RGB (0 << 1)
> +# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
> +# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
> +# define DP_TEST_DYNAMIC_RANGE (1 << 3)
I'd just name this DP_TEST_DYNAMIC_RANGE_CEA...
> +# define DP_VESA_RANGE (0 << 3)
> +# define DP_CEA_RANGE (1 << 3)
...and drop these two. But whatever.
> +# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
> +# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
> +# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
> +# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
> +# define DP_TEST_BIT_DEPTH_SHIFT 5
> +# define DP_TEST_BIT_DEPTH_6 (0 << 5)
> +# define DP_TEST_BIT_DEPTH_8 (1 << 5)
> +# define DP_TEST_BIT_DEPTH_10 (2 << 5)
> +# define DP_TEST_BIT_DEPTH_12 (3 << 5)
> +# define DP_TEST_BIT_DEPTH_16 (4 << 5)
Blank line here.
> +#define DP_TEST_MISC1 0x233
> +# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
> +# define REFRESH_DENOMINATOR_1 0x0
> +# define REFRESH_DENOMINATOR_1_001 0x1
DP_ prefix.
> +# define DP_TEST_INTERLACED (1 << 1)
> +# define DP_NON_INTERLACED (0 << 1)
> +# define DP_INTERLACED (1 << 1)
No need for these two. DP_TEST_INTERLACED is sufficient.
> +
> +#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
>
> #define DP_TEST_CRC_R_CR 0x240
> #define DP_TEST_CRC_G_Y 0x242
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests
2017-01-20 15:33 ` Jani Nikula
@ 2017-01-20 16:13 ` Manasi Navare
2017-01-20 16:28 ` Jani Nikula
0 siblings, 1 reply; 17+ messages in thread
From: Manasi Navare @ 2017-01-20 16:13 UTC (permalink / raw)
To: Jani Nikula; +Cc: Daniel Vetter, intel-gfx, dri-devel
On Fri, Jan 20, 2017 at 05:33:51PM +0200, Jani Nikula wrote:
> On Fri, 20 Jan 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> > v3:
> > * Fix the conventions in bit definitions (Jani Nikula)
> > v2:
> > * Add all the other DP Complianec TEST register defs (Jani Nikula)
> > Cc: dri-devel@lists.freedesktop.org
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> > include/drm/drm_dp_helper.h | 64 +++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 64 insertions(+)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index 0468135..7ab4153 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -417,6 +417,70 @@
> > #define DP_TEST_LANE_COUNT 0x220
> >
> > #define DP_TEST_PATTERN 0x221
> > +# define DP_NO_TEST_PATTERN 0x0
> > +# define DP_COLOR_RAMP 0x1
> > +# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
> > +# define DP_COLOR_SQUARE 0x3
> > +
> > +#define DP_TEST_H_TOTAL_HI 0x222
> > +#define DP_TEST_H_TOTAl_LO 0x223
> ^
> Sorry, didn't notice it before, but the l in TOTAL is lower case.
>
Oh yes even my eyes didnt catch this.
> > +
> > +#define DP_TEST_V_TOTAL_HI 0x224
> > +#define DP_TEST_V_TOTAl_LO 0x225
> ^
> Ditto.
>
> > +
> > +#define DP_TEST_H_START_HI 0x226
> > +#define DP_TEST_H_START_LO 0x227
> > +
> > +#define DP_TEST_V_START_HI 0x228
> > +#define DP_TEST_V_START_LO 0x229
> > +
> > +#define DP_TEST_HSYNC_HI 0x22A
> > +# define DP_TEST_HSYNC_POLARITY (1 << 7)
> > +# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
> > +#define DP_TEST_HSYNC_WIDTH_LO 0x22B
> > +
> > +#define DP_TEST_VSYNC_HI 0x22C
> > +# define DP_TEST_VSYNC_POLARITY (1 << 7)
> > +# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
> > +#define DP_TEST_VSYNC_WIDTH_LO 0x22D
> > +
> > +#define DP_TEST_H_WIDTH_HI 0x22E
> > +#define DP_TEST_H_WIDTH_LO 0x22F
> > +
> > +#define DP_TEST_V_HEIGHT_HI 0x230
> > +#define DP_TEST_V_HEIGHT_LO 0x231
> > +
> > +#define DP_TEST_MISC0 0x232
> > +# define DP_TEST_SYNC_CLOCK (1 << 0)
> > +# define DP_CLOCK_ASYNC 0x0
> > +# define DP_CLOCK_SYNC 0x1
>
> The above two are not necessary.
>
Wont these above defs be required for checking if it is DP_CLOCK_ASYNC or SYNC?
I can remove the DP_CLOCK_SINK.
> > +# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
> > +# define DP_TEST_COLOR_FORMAT_SHIFT 1
> > +# define DP_COLOR_FORMAT_RGB (0 << 1)
> > +# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
> > +# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
> > +# define DP_TEST_DYNAMIC_RANGE (1 << 3)
>
> I'd just name this DP_TEST_DYNAMIC_RANGE_CEA...
>
> > +# define DP_VESA_RANGE (0 << 3)
> > +# define DP_CEA_RANGE (1 << 3)
>
> ...and drop these two. But whatever.
>
But then how do I check for VESA?
> > +# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
> > +# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
> > +# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
> > +# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
> > +# define DP_TEST_BIT_DEPTH_SHIFT 5
> > +# define DP_TEST_BIT_DEPTH_6 (0 << 5)
> > +# define DP_TEST_BIT_DEPTH_8 (1 << 5)
> > +# define DP_TEST_BIT_DEPTH_10 (2 << 5)
> > +# define DP_TEST_BIT_DEPTH_12 (3 << 5)
> > +# define DP_TEST_BIT_DEPTH_16 (4 << 5)
>
> Blank line here.
>
This blank line is on purpose since I am starting a diff register
Manasi
> > +#define DP_TEST_MISC1 0x233
> > +# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
> > +# define REFRESH_DENOMINATOR_1 0x0
> > +# define REFRESH_DENOMINATOR_1_001 0x1
>
> DP_ prefix.
>
> > +# define DP_TEST_INTERLACED (1 << 1)
> > +# define DP_NON_INTERLACED (0 << 1)
> > +# define DP_INTERLACED (1 << 1)
>
> No need for these two. DP_TEST_INTERLACED is sufficient.
>
> > +
> > +#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
> >
> > #define DP_TEST_CRC_R_CR 0x240
> > #define DP_TEST_CRC_G_Y 0x242
>
> --
> Jani Nikula, Intel Open Source Technology Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests
2017-01-20 16:13 ` Manasi Navare
@ 2017-01-20 16:28 ` Jani Nikula
0 siblings, 0 replies; 17+ messages in thread
From: Jani Nikula @ 2017-01-20 16:28 UTC (permalink / raw)
To: Manasi Navare; +Cc: Daniel Vetter, intel-gfx, dri-devel
On Fri, 20 Jan 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> On Fri, Jan 20, 2017 at 05:33:51PM +0200, Jani Nikula wrote:
>> On Fri, 20 Jan 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
>> > v3:
>> > * Fix the conventions in bit definitions (Jani Nikula)
>> > v2:
>> > * Add all the other DP Complianec TEST register defs (Jani Nikula)
>> > Cc: dri-devel@lists.freedesktop.org
>> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
>> > Cc: Daniel Vetter <daniel.vetter@intel.com>
>> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
>> > ---
>> > include/drm/drm_dp_helper.h | 64 +++++++++++++++++++++++++++++++++++++++++++++
>> > 1 file changed, 64 insertions(+)
>> >
>> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> > index 0468135..7ab4153 100644
>> > --- a/include/drm/drm_dp_helper.h
>> > +++ b/include/drm/drm_dp_helper.h
>> > @@ -417,6 +417,70 @@
>> > #define DP_TEST_LANE_COUNT 0x220
>> >
>> > #define DP_TEST_PATTERN 0x221
>> > +# define DP_NO_TEST_PATTERN 0x0
>> > +# define DP_COLOR_RAMP 0x1
>> > +# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
>> > +# define DP_COLOR_SQUARE 0x3
>> > +
>> > +#define DP_TEST_H_TOTAL_HI 0x222
>> > +#define DP_TEST_H_TOTAl_LO 0x223
>> ^
>> Sorry, didn't notice it before, but the l in TOTAL is lower case.
>>
>
> Oh yes even my eyes didnt catch this.
>
>
>> > +
>> > +#define DP_TEST_V_TOTAL_HI 0x224
>> > +#define DP_TEST_V_TOTAl_LO 0x225
>> ^
>> Ditto.
>>
>> > +
>> > +#define DP_TEST_H_START_HI 0x226
>> > +#define DP_TEST_H_START_LO 0x227
>> > +
>> > +#define DP_TEST_V_START_HI 0x228
>> > +#define DP_TEST_V_START_LO 0x229
>> > +
>> > +#define DP_TEST_HSYNC_HI 0x22A
>> > +# define DP_TEST_HSYNC_POLARITY (1 << 7)
>> > +# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
>> > +#define DP_TEST_HSYNC_WIDTH_LO 0x22B
>> > +
>> > +#define DP_TEST_VSYNC_HI 0x22C
>> > +# define DP_TEST_VSYNC_POLARITY (1 << 7)
>> > +# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
>> > +#define DP_TEST_VSYNC_WIDTH_LO 0x22D
>> > +
>> > +#define DP_TEST_H_WIDTH_HI 0x22E
>> > +#define DP_TEST_H_WIDTH_LO 0x22F
>> > +
>> > +#define DP_TEST_V_HEIGHT_HI 0x230
>> > +#define DP_TEST_V_HEIGHT_LO 0x231
>> > +
>> > +#define DP_TEST_MISC0 0x232
>> > +# define DP_TEST_SYNC_CLOCK (1 << 0)
>> > +# define DP_CLOCK_ASYNC 0x0
>> > +# define DP_CLOCK_SYNC 0x1
>>
>> The above two are not necessary.
>>
>
> Wont these above defs be required for checking if it is DP_CLOCK_ASYNC or SYNC?
> I can remove the DP_CLOCK_SINK.
If the bit is set, it's synchronous, and asynchronous otherwise? You
don't need three macros to check one bit.
>
>> > +# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
>> > +# define DP_TEST_COLOR_FORMAT_SHIFT 1
>> > +# define DP_COLOR_FORMAT_RGB (0 << 1)
>> > +# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
>> > +# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
>> > +# define DP_TEST_DYNAMIC_RANGE (1 << 3)
>>
>> I'd just name this DP_TEST_DYNAMIC_RANGE_CEA...
>>
>> > +# define DP_VESA_RANGE (0 << 3)
>> > +# define DP_CEA_RANGE (1 << 3)
>>
>> ...and drop these two. But whatever.
>>
>
> But then how do I check for VESA?
...if it's not CEA, it's VESA?
>
>> > +# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
>> > +# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
>> > +# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
>> > +# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
>> > +# define DP_TEST_BIT_DEPTH_SHIFT 5
>> > +# define DP_TEST_BIT_DEPTH_6 (0 << 5)
>> > +# define DP_TEST_BIT_DEPTH_8 (1 << 5)
>> > +# define DP_TEST_BIT_DEPTH_10 (2 << 5)
>> > +# define DP_TEST_BIT_DEPTH_12 (3 << 5)
>> > +# define DP_TEST_BIT_DEPTH_16 (4 << 5)
>>
>> Blank line here.
>>
>
> This blank line is on purpose since I am starting a diff register
There was *no* blank line here, I meant you should add a blank line
here.
>
> Manasi
>
>
>> > +#define DP_TEST_MISC1 0x233
>> > +# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
>> > +# define REFRESH_DENOMINATOR_1 0x0
>> > +# define REFRESH_DENOMINATOR_1_001 0x1
>>
>> DP_ prefix.
>>
>> > +# define DP_TEST_INTERLACED (1 << 1)
>> > +# define DP_NON_INTERLACED (0 << 1)
>> > +# define DP_INTERLACED (1 << 1)
>>
>> No need for these two. DP_TEST_INTERLACED is sufficient.
>>
>> > +
>> > +#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
>> >
>> > #define DP_TEST_CRC_R_CR 0x240
>> > #define DP_TEST_CRC_G_Y 0x242
>>
>> --
>> Jani Nikula, Intel Open Source Technology Center
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests
2017-01-21 3:09 [PATCH 0/4] Add automation support for DP Compliance (Rev 6) Manasi Navare
@ 2017-01-21 3:09 ` Manasi Navare
2017-01-24 16:05 ` Jani Nikula
0 siblings, 1 reply; 17+ messages in thread
From: Manasi Navare @ 2017-01-21 3:09 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Daniel Vetter
v4:
* Remove redundant single bit defs (Jani Nikula)
v3:
* Fix the conventions in bit definitions (Jani Nikula)
v2:
* Add all the other DP Complianec TEST register defs (Jani Nikula)
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
include/drm/drm_dp_helper.h | 57 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 0468135..ba89295 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -417,6 +417,63 @@
#define DP_TEST_LANE_COUNT 0x220
#define DP_TEST_PATTERN 0x221
+# define DP_NO_TEST_PATTERN 0x0
+# define DP_COLOR_RAMP 0x1
+# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
+# define DP_COLOR_SQUARE 0x3
+
+#define DP_TEST_H_TOTAL_HI 0x222
+#define DP_TEST_H_TOTAL_LO 0x223
+
+#define DP_TEST_V_TOTAL_HI 0x224
+#define DP_TEST_V_TOTAL_LO 0x225
+
+#define DP_TEST_H_START_HI 0x226
+#define DP_TEST_H_START_LO 0x227
+
+#define DP_TEST_V_START_HI 0x228
+#define DP_TEST_V_START_LO 0x229
+
+#define DP_TEST_HSYNC_HI 0x22A
+# define DP_TEST_HSYNC_POLARITY (1 << 7)
+# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
+#define DP_TEST_HSYNC_WIDTH_LO 0x22B
+
+#define DP_TEST_VSYNC_HI 0x22C
+# define DP_TEST_VSYNC_POLARITY (1 << 7)
+# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
+#define DP_TEST_VSYNC_WIDTH_LO 0x22D
+
+#define DP_TEST_H_WIDTH_HI 0x22E
+#define DP_TEST_H_WIDTH_LO 0x22F
+
+#define DP_TEST_V_HEIGHT_HI 0x230
+#define DP_TEST_V_HEIGHT_LO 0x231
+
+#define DP_TEST_MISC0 0x232
+# define DP_TEST_SYNC_CLOCK (1 << 0)
+# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
+# define DP_TEST_COLOR_FORMAT_SHIFT 1
+# define DP_COLOR_FORMAT_RGB (0 << 1)
+# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
+# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
+# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
+# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
+# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
+# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
+# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
+# define DP_TEST_BIT_DEPTH_SHIFT 5
+# define DP_TEST_BIT_DEPTH_6 (0 << 5)
+# define DP_TEST_BIT_DEPTH_8 (1 << 5)
+# define DP_TEST_BIT_DEPTH_10 (2 << 5)
+# define DP_TEST_BIT_DEPTH_12 (3 << 5)
+# define DP_TEST_BIT_DEPTH_16 (4 << 5)
+
+#define DP_TEST_MISC1 0x233
+# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
+# define DP_TEST_INTERLACED (1 << 1)
+
+#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
#define DP_TEST_CRC_R_CR 0x240
#define DP_TEST_CRC_G_Y 0x242
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests
2017-01-21 3:09 ` [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests Manasi Navare
@ 2017-01-24 16:05 ` Jani Nikula
0 siblings, 0 replies; 17+ messages in thread
From: Jani Nikula @ 2017-01-24 16:05 UTC (permalink / raw)
To: intel-gfx, dri-devel, Dave Airlie; +Cc: Manasi Navare, Daniel Vetter
On Sat, 21 Jan 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> v4:
> * Remove redundant single bit defs (Jani Nikula)
> v3:
> * Fix the conventions in bit definitions (Jani Nikula)
> v2:
> * Add all the other DP Complianec TEST register defs (Jani Nikula)
> Cc: dri-devel@lists.freedesktop.org
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Dave, ack on merging this through drm-intel to not require a backmerge
for the follow-up patches?
> ---
> include/drm/drm_dp_helper.h | 57 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 57 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 0468135..ba89295 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -417,6 +417,63 @@
> #define DP_TEST_LANE_COUNT 0x220
>
> #define DP_TEST_PATTERN 0x221
> +# define DP_NO_TEST_PATTERN 0x0
> +# define DP_COLOR_RAMP 0x1
> +# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
> +# define DP_COLOR_SQUARE 0x3
> +
> +#define DP_TEST_H_TOTAL_HI 0x222
> +#define DP_TEST_H_TOTAL_LO 0x223
> +
> +#define DP_TEST_V_TOTAL_HI 0x224
> +#define DP_TEST_V_TOTAL_LO 0x225
> +
> +#define DP_TEST_H_START_HI 0x226
> +#define DP_TEST_H_START_LO 0x227
> +
> +#define DP_TEST_V_START_HI 0x228
> +#define DP_TEST_V_START_LO 0x229
> +
> +#define DP_TEST_HSYNC_HI 0x22A
> +# define DP_TEST_HSYNC_POLARITY (1 << 7)
> +# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
> +#define DP_TEST_HSYNC_WIDTH_LO 0x22B
> +
> +#define DP_TEST_VSYNC_HI 0x22C
> +# define DP_TEST_VSYNC_POLARITY (1 << 7)
> +# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
> +#define DP_TEST_VSYNC_WIDTH_LO 0x22D
> +
> +#define DP_TEST_H_WIDTH_HI 0x22E
> +#define DP_TEST_H_WIDTH_LO 0x22F
> +
> +#define DP_TEST_V_HEIGHT_HI 0x230
> +#define DP_TEST_V_HEIGHT_LO 0x231
> +
> +#define DP_TEST_MISC0 0x232
> +# define DP_TEST_SYNC_CLOCK (1 << 0)
> +# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
> +# define DP_TEST_COLOR_FORMAT_SHIFT 1
> +# define DP_COLOR_FORMAT_RGB (0 << 1)
> +# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
> +# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
> +# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
> +# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
> +# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
> +# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
> +# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
> +# define DP_TEST_BIT_DEPTH_SHIFT 5
> +# define DP_TEST_BIT_DEPTH_6 (0 << 5)
> +# define DP_TEST_BIT_DEPTH_8 (1 << 5)
> +# define DP_TEST_BIT_DEPTH_10 (2 << 5)
> +# define DP_TEST_BIT_DEPTH_12 (3 << 5)
> +# define DP_TEST_BIT_DEPTH_16 (4 << 5)
> +
> +#define DP_TEST_MISC1 0x233
> +# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
> +# define DP_TEST_INTERLACED (1 << 1)
> +
> +#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
>
> #define DP_TEST_CRC_R_CR 0x240
> #define DP_TEST_CRC_G_Y 0x242
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2017-01-24 16:05 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
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2017-01-17 22:57 [PATCH 0/4] Add Automation Support for DP Compliance Testing (Rev 4) Manasi Navare
2017-01-17 22:57 ` [PATCH 1/4] drm/i915: Add support for DP link training compliance Manasi Navare
2017-01-18 17:29 ` Manasi Navare
2017-01-19 15:51 ` Jani Nikula
2017-01-17 22:57 ` [PATCH 2/4] drm/i915: Fixes to support DP Compliance EDID tests Manasi Navare
2017-01-18 17:32 ` Manasi Navare
2017-01-17 22:57 ` [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests Manasi Navare
2017-01-18 17:35 ` Manasi Navare
2017-01-19 13:31 ` Jani Nikula
2017-01-17 22:57 ` [PATCH 4/4] drm/i915: Add support for DP Video pattern compliance tests Manasi Navare
2017-01-18 17:37 ` Manasi Navare
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2017-01-20 6:23 [PATCH 0/4] Add Automation Support for DP Compliance (Rev 5) Manasi Navare
2017-01-20 6:23 ` [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests Manasi Navare
2017-01-20 15:33 ` Jani Nikula
2017-01-20 16:13 ` Manasi Navare
2017-01-20 16:28 ` Jani Nikula
2017-01-21 3:09 [PATCH 0/4] Add automation support for DP Compliance (Rev 6) Manasi Navare
2017-01-21 3:09 ` [PATCH 3/4] drm: Add definitions for DP compliance Video pattern tests Manasi Navare
2017-01-24 16:05 ` Jani Nikula
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