From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: vathsala nagaraju <vathsala.nagaraju@intel.com>
Cc: Puthikorn Voravootivat <puthik@chromium.org>,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
Date: Thu, 28 Sep 2017 09:54:23 -0700 [thread overview]
Message-ID: <20170928165423.pa6f2pfi726xgyv6@intel.com> (raw)
In-Reply-To: <1506095916-20250-1-git-send-email-vathsala.nagaraju@intel.com>
On Fri, Sep 22, 2017 at 03:58:36PM +0000, vathsala nagaraju wrote:
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
>
> v2 :
> - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
> - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
> - add check ==1 for dpcd_read call (ville)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Merged both patches to dinq. Thanks for the patches.
I'm anxiously waiting the PSR2 related workaroud(s)! ;)
Thanks,
Rodrigo.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> 2 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 82f36dd..89c5249 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -170,6 +170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> (mask) << 16 | (value); })
> #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
> #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
> +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
>
> /* Engine ID */
>
> @@ -4047,7 +4048,6 @@ enum {
> #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
> #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
> #define EDP_PSR2_IDLE_MASK 0xf
> -#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
>
> #define EDP_PSR2_STATUS_CTL _MMIO(0x6f940)
> #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 0a17d1f..e505fa6 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> */
> uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> uint32_t val;
> + uint8_t sink_latency;
>
> val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> * mesh at all with our frontbuffer tracking. And the hw alone isn't
> * good enough. */
> val |= EDP_PSR2_ENABLE |
> - EDP_SU_TRACK_ENABLE |
> - EDP_FRAMES_BEFORE_SU_ENTRY;
> + EDP_SU_TRACK_ENABLE;
> +
> + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> + &sink_latency) == 1) {
> + sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
> + } else {
> + sink_latency = 0;
> + }
> + val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
>
> if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> val |= EDP_PSR2_TP2_TIME_2500;
> --
> 1.9.1
>
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next prev parent reply other threads:[~2017-09-28 16:54 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-20 14:32 [PATCH 1/2] drm/dp: Add defines for latency in sink vathsala nagaraju
2017-09-20 14:32 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
2017-09-20 14:44 ` Ville Syrjälä
2017-09-20 15:19 ` Vivi, Rodrigo
2017-09-22 15:58 ` vathsala nagaraju
2017-09-22 23:54 ` Rodrigo Vivi
2017-09-28 16:54 ` Rodrigo Vivi [this message]
2017-09-29 11:36 ` Jani Nikula
2017-09-20 22:07 ` [PATCH 1/2] drm/dp: Add defines for latency in sink Rodrigo Vivi
2017-09-21 14:42 ` Rodrigo Vivi
2017-09-26 5:11 ` Daniel Vetter
2017-09-26 17:37 ` Puthikorn Voravootivat
2017-09-26 20:37 ` Puthikorn Voravootivat
2017-09-26 20:53 ` [Intel-gfx] " Rodrigo Vivi
-- strict thread matches above, loose matches on Subject: below --
2017-09-23 0:34 vathsala nagaraju
2017-09-23 0:34 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
2017-09-25 8:30 ` [Intel-gfx] " Jani Nikula
2017-09-25 9:10 ` vathsala nagaraju
2017-09-25 16:57 ` Rodrigo Vivi
2017-09-26 9:59 [PATCH 1/2] drm/dp: Add defines for latency in sink vathsala nagaraju
2017-09-26 9:59 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
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