From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Subject: [PATCH v3 09/10] drm/i915/psr: Set DPCD PSR2 enable bit when needed Date: Wed, 28 Mar 2018 15:30:45 -0700 Message-ID: <20180328223046.16125-9-jose.souza@intel.com> References: <20180328223046.16125-1-jose.souza@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180328223046.16125-1-jose.souza@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: intel-gfx@lists.freedesktop.org Cc: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= , dri-devel@lists.freedesktop.org, Dhinakaran Pandiyan List-Id: dri-devel@lists.freedesktop.org SW4gdGhlIDIgZURQMS40YSBwYW5uZWxzIHRlc3RlZCBzZXQgb3Igbm90IHNldCBiaXQgaGF2ZSBu byBlZmZlY3QKYnV0IGlzIGJldHRlciBzZXQgaXQgYW5kIGNvbXBseSB3aXRoIHNwZWNpZmljYXRp b24uCgpTaWduZWQtb2ZmLWJ5OiBKb3PDqSBSb2JlcnRvIGRlIFNvdXphIDxqb3NlLnNvdXphQGlu dGVsLmNvbT4KQ2M6IERoaW5ha2FyYW4gUGFuZGl5YW4gPGRoaW5ha2FyYW4ucGFuZGl5YW5AaW50 ZWwuY29tPgpSZXZpZXdlZC1ieTogUm9kcmlnbyBWaXZpIDxyb2RyaWdvLnZpdmlAaW50ZWwuY29t PgotLS0KCnYzOiByZWJhc2VkCgogZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfcHNyLmMgfCAx MSArKysrKystLS0tLQogMSBmaWxlIGNoYW5nZWQsIDYgaW5zZXJ0aW9ucygrKSwgNSBkZWxldGlv bnMoLSkKCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wc3IuYyBiL2Ry aXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX3Bzci5jCmluZGV4IGQwNzljZjBiMDM0Yy4uMmQ1M2Y3 Mzk4YTZkIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wc3IuYworKysg Yi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wc3IuYwpAQCAtMjc4LDE4ICsyNzgsMTkgQEAg c3RhdGljIHZvaWQgaHN3X3Bzcl9lbmFibGVfc2luayhzdHJ1Y3QgaW50ZWxfZHAgKmludGVsX2Rw KQogCXN0cnVjdCBpbnRlbF9kaWdpdGFsX3BvcnQgKmRpZ19wb3J0ID0gZHBfdG9fZGlnX3BvcnQo aW50ZWxfZHApOwogCXN0cnVjdCBkcm1fZGV2aWNlICpkZXYgPSBkaWdfcG9ydC0+YmFzZS5iYXNl LmRldjsKIAlzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYgPSB0b19pOTE1KGRldik7 CisJdTggZHBjZF92YWwgPSBEUF9QU1JfRU5BQkxFOwogCiAJLyogRW5hYmxlIEFMUE0gYXQgc2lu ayBmb3IgcHNyMiAqLwogCWlmIChkZXZfcHJpdi0+cHNyLnBzcjJfZW5hYmxlZCAmJiBkZXZfcHJp di0+cHNyLmFscG0pCiAJCWRybV9kcF9kcGNkX3dyaXRlYigmaW50ZWxfZHAtPmF1eCwKIAkJCQlE UF9SRUNFSVZFUl9BTFBNX0NPTkZJRywKIAkJCQlEUF9BTFBNX0VOQUJMRSk7CisKKwlpZiAoZGV2 X3ByaXYtPnBzci5wc3IyX2VuYWJsZWQpCisJCWRwY2RfdmFsIHw9IERQX1BTUl9FTkFCTEVfUFNS MjsKIAlpZiAoZGV2X3ByaXYtPnBzci5saW5rX3N0YW5kYnkpCi0JCWRybV9kcF9kcGNkX3dyaXRl YigmaW50ZWxfZHAtPmF1eCwgRFBfUFNSX0VOX0NGRywKLQkJCQkgICBEUF9QU1JfRU5BQkxFIHwg RFBfUFNSX01BSU5fTElOS19BQ1RJVkUpOwotCWVsc2UKLQkJZHJtX2RwX2RwY2Rfd3JpdGViKCZp bnRlbF9kcC0+YXV4LCBEUF9QU1JfRU5fQ0ZHLAotCQkJCSAgIERQX1BTUl9FTkFCTEUpOworCQlk cGNkX3ZhbCB8PSBEUF9QU1JfTUFJTl9MSU5LX0FDVElWRTsKKwlkcm1fZHBfZHBjZF93cml0ZWIo JmludGVsX2RwLT5hdXgsIERQX1BTUl9FTl9DRkcsIGRwY2RfdmFsKTsKIAogCWRybV9kcF9kcGNk X3dyaXRlYigmaW50ZWxfZHAtPmF1eCwgRFBfU0VUX1BPV0VSLCBEUF9TRVRfUE9XRVJfRDApOwog fQotLSAKMi4xNi4zCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5v cmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2 ZWwK