[PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[matthew.s.atwood]

From: Matt Atwood <matthew.s.atwood@intel.com>

According to DP spec (2.9.3.1 of DP 1.4) if
EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
02200h through 0220Fh shall contain the DPRX's true capability. These
values will match 00000h through 0000Fh, except for DPCD_REV,
MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.

Read from DPCD once for all 3 values as this is an expensive operation.
Spec mentions that all of address space 02200h through 0220Fh should
contain the right information however currently only 3 values can
differ.

There is no address space in the intel_dp->dpcd struct for addresses
02200h through 0220Fh, and since so much of the data is a identical,
simply overwrite the values stored in 00000h through 0000Fh with the
values that can be overwritten from addresses 02200h through 0220Fh.

This patch helps with backward compatibility for devices pre DP1.3.

v2: read only dpcd values which can be affected, remove incorrect check,
split into drm include changes into separate patch, commit message,
verbose debugging statements during overwrite.

Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 37 +++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dde92e4af5d3..364cf41a8b89 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3738,6 +3738,43 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
 			     sizeof(intel_dp->dpcd)) < 0)
 		return false; /* aux transfer failed */
 
+	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
+		uint8_t dpcd_ext[6];
+
+		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
+
+		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
+		    &dpcd_ext, sizeof(dpcd_ext)) < 0)
+			return false; /* aux transfer failed */
+
+		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
+			   sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DPCD_REV],
+				      dpcd_ext[DP_DPCD_REV]);
+			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
+			       &dpcd_ext[DP_DPCD_REV],
+			       sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_MAX_LINK_RATE],
+				      dpcd_ext[DP_MAX_LINK_RATE]);
+			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
+			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
+			       sizeof(u8));
+		}
+	}
 	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
 
 	return intel_dp->dpcd[DP_DPCD_REV] != 0;
-- 
2.17.1

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[PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[matthew.s.atwood]

From: Matt Atwood <matthew.s.atwood@intel.com>

According to DP spec (2.9.3.1 of DP 1.4) if
EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
02200h through 0220Fh shall contain the DPRX's true capability. These
values will match 00000h through 0000Fh, except for DPCD_REV,
MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.

Read from DPCD once for all 3 values as this is an expensive operation.
Spec mentions that all of address space 02200h through 0220Fh should
contain the right information however currently only 3 values can
differ.

There is no address space in the intel_dp->dpcd struct for addresses
02200h through 0220Fh, and since so much of the data is a identical,
simply overwrite the values stored in 00000h through 0000Fh with the
values that can be overwritten from addresses 02200h through 0220Fh.

This patch helps with backward compatibility for devices pre DP1.3.

v2: read only dpcd values which can be affected, remove incorrect check,
split into drm include changes into separate patch, commit message,
verbose debugging statements during overwrite.

v3: white space fixes

Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 37 +++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dde92e4af5d3..a31fbbbd7954 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3738,6 +3738,43 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
 			     sizeof(intel_dp->dpcd)) < 0)
 		return false; /* aux transfer failed */
 
+	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
+		uint8_t dpcd_ext[6];
+
+		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
+
+		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
+				     &dpcd_ext, sizeof(dpcd_ext)) < 0)
+			return false; /* aux transfer failed */
+
+		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
+			   sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DPCD_REV],
+				      dpcd_ext[DP_DPCD_REV]);
+			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
+			       &dpcd_ext[DP_DPCD_REV],
+			       sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_MAX_LINK_RATE],
+				      dpcd_ext[DP_MAX_LINK_RATE]);
+			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
+			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
+			       sizeof(u8));
+		}
+	}
 	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
 
 	return intel_dp->dpcd[DP_DPCD_REV] != 0;
-- 
2.17.1

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Re: [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Rodrigo Vivi]

On Thu, Jul 19, 2018 at 01:35:49PM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values will match 00000h through 0000Fh, except for DPCD_REV,
> MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> 
> Read from DPCD once for all 3 values as this is an expensive operation.
> Spec mentions that all of address space 02200h through 0220Fh should
> contain the right information however currently only 3 values can
> differ.
> 
> There is no address space in the intel_dp->dpcd struct for addresses
> 02200h through 0220Fh, and since so much of the data is a identical,
> simply overwrite the values stored in 00000h through 0000Fh with the
> values that can be overwritten from addresses 02200h through 0220Fh.
> 
> This patch helps with backward compatibility for devices pre DP1.3.
> 
> v2: read only dpcd values which can be affected, remove incorrect check,
> split into drm include changes into separate patch, commit message,
> verbose debugging statements during overwrite.
> 
> v3: white space fixes
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 37 +++++++++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dde92e4af5d3..a31fbbbd7954 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3738,6 +3738,43 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
>  			     sizeof(intel_dp->dpcd)) < 0)
>  		return false; /* aux transfer failed */
>  

We never know what vendors can do with reserved bits. We should never assume
they are zero. So we shouldn't do any of below unless it is newer than DP 1.3.

> +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
> +		uint8_t dpcd_ext[6];
> +
> +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
> +
> +		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
> +				     &dpcd_ext, sizeof(dpcd_ext)) < 0)
> +			return false; /* aux transfer failed */
> +
> +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
> +			   sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DPCD_REV],
> +				      dpcd_ext[DP_DPCD_REV]);
> +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> +			       &dpcd_ext[DP_DPCD_REV],
> +			       sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_MAX_LINK_RATE],
> +				      dpcd_ext[DP_MAX_LINK_RATE]);
> +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
> +			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> +			       sizeof(u8));
> +		}
> +	}
>  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
>  
>  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
> -- 
> 2.17.1
> 
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Re: [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Atwood, Matthew S]

On Thu, 2018-07-19 at 14:07 -0700, Rodrigo Vivi wrote:
> On Thu, Jul 19, 2018 at 01:35:49PM -0700, matthew.s.atwood@intel.com
> wrote:
> > From: Matt Atwood <matthew.s.atwood@intel.com>
> > 
> > According to DP spec (2.9.3.1 of DP 1.4) if
> > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in
> > DPCD
> > 02200h through 0220Fh shall contain the DPRX's true capability.
> > These
> > values will match 00000h through 0000Fh, except for DPCD_REV,
> > MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> > 
> > Read from DPCD once for all 3 values as this is an expensive
> > operation.
> > Spec mentions that all of address space 02200h through 0220Fh
> > should
> > contain the right information however currently only 3 values can
> > differ.
> > 
> > There is no address space in the intel_dp->dpcd struct for
> > addresses
> > 02200h through 0220Fh, and since so much of the data is a
> > identical,
> > simply overwrite the values stored in 00000h through 0000Fh with
> > the
> > values that can be overwritten from addresses 02200h through
> > 0220Fh.
> > 
> > This patch helps with backward compatibility for devices pre DP1.3.
> > 
> > v2: read only dpcd values which can be affected, remove incorrect
> > check,
> > split into drm include changes into separate patch, commit message,
> > verbose debugging statements during overwrite.
> > 
> > v3: white space fixes
> > 
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 37
> > +++++++++++++++++++++++++++++++++
> >  1 file changed, 37 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index dde92e4af5d3..a31fbbbd7954 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3738,6 +3738,43 @@ intel_dp_read_dpcd(struct intel_dp
> > *intel_dp)
> >  			     sizeof(intel_dp->dpcd)) < 0)
> >  		return false; /* aux transfer failed */
> >  
> 
> We never know what vendors can do with reserved bits. We should never
> assume
> they are zero. So we shouldn't do any of below unless it is newer
> than DP 1.3.
I think you mean newer than DP1.2?
> 
> > +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> > +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
> > +		uint8_t dpcd_ext[6];
> > +
> > +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability
> > Field Present, accessing 02200h through 022FFh\n");
> > +
> > +		if (drm_dp_dpcd_read(&intel_dp->aux,
> > DP_DP13_DPCD_REV,
> > +				     &dpcd_ext, sizeof(dpcd_ext))
> > < 0)
> > +			return false; /* aux transfer failed */
> > +
> > +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV],
> > &dpcd_ext[DP_DPCD_REV],
> > +			   sizeof(u8))) {
> > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > Revision previous value %2x new value %2x\n",
> > +				      intel_dp->dpcd[DP_DPCD_REV],
> > +				      dpcd_ext[DP_DPCD_REV]);
> > +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> > +			       &dpcd_ext[DP_DPCD_REV],
> > +			       sizeof(u8));
> > +		}
> > +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> > +			   &dpcd_ext[DP_MAX_LINK_RATE],
> > sizeof(u8))) {
> > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > Max Link Rate previous value %2x new value %2x\n",
> > +				      intel_dp-
> > >dpcd[DP_MAX_LINK_RATE],
> > +				      dpcd_ext[DP_MAX_LINK_RATE]);
> > +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> > +			       &dpcd_ext[DP_MAX_LINK_RATE],
> > sizeof(u8));
> > +		}
> > +		if (memcmp(&intel_dp-
> > >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> > sizeof(u8))) {
> > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > Downstream Port Present  previous value %2x new value %2x\n",
> > +				      intel_dp-
> > >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > +				      dpcd_ext[DP_DOWNSTREAMPORT_P
> > RESENT]);
> > +			memcpy(&intel_dp-
> > >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT
> > ],
> > +			       sizeof(u8));
> > +		}
> > +	}
> >  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp-
> > >dpcd), intel_dp->dpcd);
> >  
> >  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
> > -- 
> > 2.17.1
> > 
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Re: [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Rodrigo Vivi]

On Thu, Jul 19, 2018 at 02:47:59PM -0700, Atwood, Matthew S wrote:
> On Thu, 2018-07-19 at 14:07 -0700, Rodrigo Vivi wrote:
> > On Thu, Jul 19, 2018 at 01:35:49PM -0700, matthew.s.atwood@intel.com
> > wrote:
> > > From: Matt Atwood <matthew.s.atwood@intel.com>
> > > 
> > > According to DP spec (2.9.3.1 of DP 1.4) if
> > > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in
> > > DPCD
> > > 02200h through 0220Fh shall contain the DPRX's true capability.
> > > These
> > > values will match 00000h through 0000Fh, except for DPCD_REV,
> > > MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> > > 
> > > Read from DPCD once for all 3 values as this is an expensive
> > > operation.
> > > Spec mentions that all of address space 02200h through 0220Fh
> > > should
> > > contain the right information however currently only 3 values can
> > > differ.
> > > 
> > > There is no address space in the intel_dp->dpcd struct for
> > > addresses
> > > 02200h through 0220Fh, and since so much of the data is a
> > > identical,
> > > simply overwrite the values stored in 00000h through 0000Fh with
> > > the
> > > values that can be overwritten from addresses 02200h through
> > > 0220Fh.
> > > 
> > > This patch helps with backward compatibility for devices pre DP1.3.
> > > 
> > > v2: read only dpcd values which can be affected, remove incorrect
> > > check,
> > > split into drm include changes into separate patch, commit message,
> > > verbose debugging statements during overwrite.
> > > 
> > > v3: white space fixes
> > > 
> > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c | 37
> > > +++++++++++++++++++++++++++++++++
> > >  1 file changed, 37 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index dde92e4af5d3..a31fbbbd7954 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -3738,6 +3738,43 @@ intel_dp_read_dpcd(struct intel_dp
> > > *intel_dp)
> > >  			     sizeof(intel_dp->dpcd)) < 0)
> > >  		return false; /* aux transfer failed */
> > >  
> > 
> > We never know what vendors can do with reserved bits. We should never
> > assume
> > they are zero. So we shouldn't do any of below unless it is newer
> > than DP 1.3.
> I think you mean newer than DP1.2?

yeap, sorry..

>= DP1.3

> > 
> > > +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> > > +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
> > > +		uint8_t dpcd_ext[6];
> > > +
> > > +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability
> > > Field Present, accessing 02200h through 022FFh\n");
> > > +
> > > +		if (drm_dp_dpcd_read(&intel_dp->aux,
> > > DP_DP13_DPCD_REV,
> > > +				     &dpcd_ext, sizeof(dpcd_ext))
> > > < 0)
> > > +			return false; /* aux transfer failed */
> > > +
> > > +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV],
> > > &dpcd_ext[DP_DPCD_REV],
> > > +			   sizeof(u8))) {
> > > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > > Revision previous value %2x new value %2x\n",
> > > +				      intel_dp->dpcd[DP_DPCD_REV],
> > > +				      dpcd_ext[DP_DPCD_REV]);
> > > +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> > > +			       &dpcd_ext[DP_DPCD_REV],
> > > +			       sizeof(u8));
> > > +		}
> > > +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> > > +			   &dpcd_ext[DP_MAX_LINK_RATE],
> > > sizeof(u8))) {
> > > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > > Max Link Rate previous value %2x new value %2x\n",
> > > +				      intel_dp-
> > > >dpcd[DP_MAX_LINK_RATE],
> > > +				      dpcd_ext[DP_MAX_LINK_RATE]);
> > > +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> > > +			       &dpcd_ext[DP_MAX_LINK_RATE],
> > > sizeof(u8));
> > > +		}
> > > +		if (memcmp(&intel_dp-
> > > >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > > +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> > > sizeof(u8))) {
> > > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > > Downstream Port Present  previous value %2x new value %2x\n",
> > > +				      intel_dp-
> > > >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > > +				      dpcd_ext[DP_DOWNSTREAMPORT_P
> > > RESENT]);
> > > +			memcpy(&intel_dp-
> > > >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > > +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT
> > > ],
> > > +			       sizeof(u8));
> > > +		}
> > > +	}
> > >  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp-
> > > >dpcd), intel_dp->dpcd);
> > >  
> > >  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
> > > -- 
> > > 2.17.1
> > > 
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[PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[matthew.s.atwood]

From: Matt Atwood <matthew.s.atwood@intel.com>

According to DP spec (2.9.3.1 of DP 1.4) if
EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
02200h through 0220Fh shall contain the DPRX's true capability. These
values will match 00000h through 0000Fh, except for DPCD_REV,
MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.

Read from DPCD once for all 3 values as this is an expensive operation.
Spec mentions that all of address space 02200h through 0220Fh should
contain the right information however currently only 3 values can
differ.

There is no address space in the intel_dp->dpcd struct for addresses
02200h through 0220Fh, and since so much of the data is a identical,
simply overwrite the values stored in 00000h through 0000Fh with the
values that can be overwritten from addresses 02200h through 0220Fh.

This patch helps with backward compatibility for devices pre DP1.3.

v2: read only dpcd values which can be affected, remove incorrect check,
split into drm include changes into separate patch, commit message,
verbose debugging statements during overwrite.
v3: white space fixes
v4: make path dependent on DPCD revision > 1.2

Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 38 +++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dde92e4af5d3..9d7e1d0b1487 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3738,6 +3738,44 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
 			     sizeof(intel_dp->dpcd)) < 0)
 		return false; /* aux transfer failed */
 
+	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT &&
+	    intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_13) {
+		uint8_t dpcd_ext[6];
+
+		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
+
+		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
+				     &dpcd_ext, sizeof(dpcd_ext)) < 0)
+			return false; /* aux transfer failed */
+
+		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
+			   sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DPCD_REV],
+				      dpcd_ext[DP_DPCD_REV]);
+			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
+			       &dpcd_ext[DP_DPCD_REV],
+			       sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_MAX_LINK_RATE],
+				      dpcd_ext[DP_MAX_LINK_RATE]);
+			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
+			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
+			       sizeof(u8));
+		}
+	}
 	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
 
 	return intel_dp->dpcd[DP_DPCD_REV] != 0;
-- 
2.17.1

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Re: [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Rodrigo Vivi]

On Fri, Jul 20, 2018 at 09:18:12AM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values will match 00000h through 0000Fh, except for DPCD_REV,
> MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> 
> Read from DPCD once for all 3 values as this is an expensive operation.
> Spec mentions that all of address space 02200h through 0220Fh should
> contain the right information however currently only 3 values can
> differ.
> 
> There is no address space in the intel_dp->dpcd struct for addresses
> 02200h through 0220Fh, and since so much of the data is a identical,
> simply overwrite the values stored in 00000h through 0000Fh with the
> values that can be overwritten from addresses 02200h through 0220Fh.
> 
> This patch helps with backward compatibility for devices pre DP1.3.
> 
> v2: read only dpcd values which can be affected, remove incorrect check,
> split into drm include changes into separate patch, commit message,
> verbose debugging statements during overwrite.
> v3: white space fixes
> v4: make path dependent on DPCD revision > 1.2
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 38 +++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dde92e4af5d3..9d7e1d0b1487 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3738,6 +3738,44 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
>  			     sizeof(intel_dp->dpcd)) < 0)
>  		return false; /* aux transfer failed */
>  
> +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT &&
> +	    intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_13) {

wrong order... you don't need to read those bits if ! rev >= 1.3

> +		uint8_t dpcd_ext[6];
> +
> +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
> +
> +		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
> +				     &dpcd_ext, sizeof(dpcd_ext)) < 0)
> +			return false; /* aux transfer failed */
> +
> +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
> +			   sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DPCD_REV],
> +				      dpcd_ext[DP_DPCD_REV]);
> +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> +			       &dpcd_ext[DP_DPCD_REV],
> +			       sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_MAX_LINK_RATE],
> +				      dpcd_ext[DP_MAX_LINK_RATE]);
> +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
> +			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> +			       sizeof(u8));
> +		}
> +	}
>  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
>  
>  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
> -- 
> 2.17.1
> 
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Re: [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Manasi Navare]

On Fri, Jul 20, 2018 at 09:18:12AM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values will match 00000h through 0000Fh, except for DPCD_REV,
> MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> 
> Read from DPCD once for all 3 values as this is an expensive operation.
> Spec mentions that all of address space 02200h through 0220Fh should
> contain the right information however currently only 3 values can
> differ.
> 
> There is no address space in the intel_dp->dpcd struct for addresses
> 02200h through 0220Fh, and since so much of the data is a identical,
> simply overwrite the values stored in 00000h through 0000Fh with the
> values that can be overwritten from addresses 02200h through 0220Fh.
> 
> This patch helps with backward compatibility for devices pre DP1.3.
> 
> v2: read only dpcd values which can be affected, remove incorrect check,
> split into drm include changes into separate patch, commit message,
> verbose debugging statements during overwrite.
> v3: white space fixes
> v4: make path dependent on DPCD revision > 1.2
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 38 +++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dde92e4af5d3..9d7e1d0b1487 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3738,6 +3738,44 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
>  			     sizeof(intel_dp->dpcd)) < 0)
>  		return false; /* aux transfer failed */
>  
> +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT &&
> +	    intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_13) {

Like I had mentioned earlier, this check for DP_DPCD_REV is not required infact
if the extended reciever cap field is present its likely that the correct REV is present in the different offset
and the original DP_DPCD_REV indicates the legacy or older REV number. This is waht i observed when I tested this earlier
on DP 1.4 sink and had to remove this REV check since the original REV register was advertising it as DP 1.1 sink.

Manasi

> +		uint8_t dpcd_ext[6];
> +
> +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
> +
> +		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
> +				     &dpcd_ext, sizeof(dpcd_ext)) < 0)
> +			return false; /* aux transfer failed */
> +
> +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
> +			   sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DPCD_REV],
> +				      dpcd_ext[DP_DPCD_REV]);
> +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> +			       &dpcd_ext[DP_DPCD_REV],
> +			       sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_MAX_LINK_RATE],
> +				      dpcd_ext[DP_MAX_LINK_RATE]);
> +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
> +			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> +			       sizeof(u8));
> +		}
> +	}
>  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
>  
>  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
> -- 
> 2.17.1
> 
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[PATCH 1/2] drm/dp: add extended receiver capability field present bit

[matthew.s.atwood]

From: Matt Atwood <matthew.s.atwood@intel.com>

This bit was added to DP Training Aux RD interval with DP 1.3. Via
descriptiion of the spec this field indicates the panels true
capabilities are described in DPCD address space 02200h through 022FFh.

v2: version comment update
v3: version comment correction, commit message update
v4: white space correction

Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 include/drm/drm_dp_helper.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c01564991a9f..44aaefdc8448 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -123,8 +123,9 @@
 # define DP_FRAMING_CHANGE_CAP		    (1 << 1)
 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */
 
-#define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
-# define DP_TRAINING_AUX_RD_MASK            0x7F    /* XXX 1.2? */
+#define DP_TRAINING_AUX_RD_INTERVAL             0x00e   /* XXX 1.2? */
+# define DP_TRAINING_AUX_RD_MASK                0x7F    /* DP 1.3 */
+# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT	(1 << 7)/* DP 1.3 */
 
 #define DP_ADAPTER_CAP			    0x00f   /* 1.2 */
 # define DP_FORCE_LOAD_SENSE_CAP	    (1 << 0)
-- 
2.17.1

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[PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[matthew.s.atwood]

From: Matt Atwood <matthew.s.atwood@intel.com>

According to DP spec (2.9.3.1 of DP 1.4) if
EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
02200h through 0220Fh shall contain the DPRX's true capability. These
values will match 00000h through 0000Fh, except for DPCD_REV,
MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.

Read from DPCD once for all 3 values as this is an expensive operation.
Spec mentions that all of address space 02200h through 0220Fh should
contain the right information however currently only 3 values can
differ.

There is no address space in the intel_dp->dpcd struct for addresses
02200h through 0220Fh, and since so much of the data is a identical,
simply overwrite the values stored in 00000h through 0000Fh with the
values that can be overwritten from addresses 02200h through 0220Fh.

This patch helps with backward compatibility for devices pre DP1.3.

v2: read only dpcd values which can be affected, remove incorrect check,
split into drm include changes into separate patch, commit message,
verbose debugging statements during overwrite.
v3: white space fixes
v4: make path dependent on DPCD revision > 1.2
v5: split into function, removed DPCD rev check

Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 54 +++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dde92e4af5d3..ed16b93bfe40 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3731,6 +3731,58 @@ intel_dp_link_down(struct intel_encoder *encoder,
 	}
 }
 
+static void
+intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
+{
+	/*
+	 * Prior to DP1.3 the bit represented by
+	 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
+	 * if it is set DP_DPCD_REV at 0000h could be at a value less than
+	 * the true capability of the panel. The only way to check is to
+	 * then compare 0000h and 2200h.
+	 */
+	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
+		uint8_t dpcd_ext[6];
+
+		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
+
+		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
+				     &dpcd_ext, sizeof(dpcd_ext)) < 0)
+			return;
+
+		if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV])
+			return;
+
+		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
+			   sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DPCD_REV],
+				      dpcd_ext[DP_DPCD_REV]);
+			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
+			       &dpcd_ext[DP_DPCD_REV], sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_MAX_LINK_RATE],
+				      dpcd_ext[DP_MAX_LINK_RATE]);
+			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
+			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
+			       sizeof(u8));
+		}
+	}
+}
+
+
 bool
 intel_dp_read_dpcd(struct intel_dp *intel_dp)
 {
@@ -3738,6 +3790,8 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
 			     sizeof(intel_dp->dpcd)) < 0)
 		return false; /* aux transfer failed */
 
+	intel_dp_extended_receiver_capabilities(intel_dp);
+
 	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
 
 	return intel_dp->dpcd[DP_DPCD_REV] != 0;
-- 
2.17.1

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Re: [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Rodrigo Vivi]

On Mon, Jul 23, 2018 at 02:27:35PM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values will match 00000h through 0000Fh, except for DPCD_REV,
> MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> 
> Read from DPCD once for all 3 values as this is an expensive operation.
> Spec mentions that all of address space 02200h through 0220Fh should
> contain the right information however currently only 3 values can
> differ.
> 
> There is no address space in the intel_dp->dpcd struct for addresses
> 02200h through 0220Fh, and since so much of the data is a identical,
> simply overwrite the values stored in 00000h through 0000Fh with the
> values that can be overwritten from addresses 02200h through 0220Fh.
> 
> This patch helps with backward compatibility for devices pre DP1.3.
> 
> v2: read only dpcd values which can be affected, remove incorrect check,
> split into drm include changes into separate patch, commit message,
> verbose debugging statements during overwrite.
> v3: white space fixes
> v4: make path dependent on DPCD revision > 1.2
> v5: split into function, removed DPCD rev check
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 54 +++++++++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dde92e4af5d3..ed16b93bfe40 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3731,6 +3731,58 @@ intel_dp_link_down(struct intel_encoder *encoder,
>  	}
>  }
>  
> +static void
> +intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
> +{
> +	/*
> +	 * Prior to DP1.3 the bit represented by
> +	 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
> +	 * if it is set DP_DPCD_REV at 0000h could be at a value less than
> +	 * the true capability of the panel. The only way to check is to
> +	 * then compare 0000h and 2200h.
> +	 */
> +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
> +		uint8_t dpcd_ext[6];
> +
> +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
> +
> +		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
> +				     &dpcd_ext, sizeof(dpcd_ext)) < 0)

DRM_ERROR

> +			return;
> +
> +		if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV])

DRM_DEBUG_KMS
> +			return;

The silent skip will be hard to debug and we will never know where it went
wrong.

> +
> +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
> +			   sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DPCD_REV],
> +				      dpcd_ext[DP_DPCD_REV]);
> +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> +			       &dpcd_ext[DP_DPCD_REV], sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_MAX_LINK_RATE],
> +				      dpcd_ext[DP_MAX_LINK_RATE]);
> +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
> +			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> +			       sizeof(u8));
> +		}
> +	}
> +}
> +
> +
>  bool
>  intel_dp_read_dpcd(struct intel_dp *intel_dp)
>  {
> @@ -3738,6 +3790,8 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
>  			     sizeof(intel_dp->dpcd)) < 0)
>  		return false; /* aux transfer failed */
>  
> +	intel_dp_extended_receiver_capabilities(intel_dp);
> +
>  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
>  
>  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
> -- 
> 2.17.1
> 
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> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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Re: [PATCH 1/2] drm/dp: add extended receiver capability field present bit

[Rodrigo Vivi]

On Mon, Jul 23, 2018 at 02:27:34PM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> This bit was added to DP Training Aux RD interval with DP 1.3. Via
> descriptiion of the spec this field indicates the panels true
> capabilities are described in DPCD address space 02200h through 022FFh.
> 
> v2: version comment update
> v3: version comment correction, commit message update
> v4: white space correction

I'm afraid the wrong space that I had mentioned it is still there
s/"(1 << 7)/* DP 1.3 */"/"(1 << 7) /* DP 1.3 *"/g

> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  include/drm/drm_dp_helper.h | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index c01564991a9f..44aaefdc8448 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -123,8 +123,9 @@
>  # define DP_FRAMING_CHANGE_CAP		    (1 << 1)
>  # define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */
>  
> -#define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
> -# define DP_TRAINING_AUX_RD_MASK            0x7F    /* XXX 1.2? */
> +#define DP_TRAINING_AUX_RD_INTERVAL             0x00e   /* XXX 1.2? */
> +# define DP_TRAINING_AUX_RD_MASK                0x7F    /* DP 1.3 */
> +# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT	(1 << 7)/* DP 1.3 */
                                                                ^ here

>  
>  #define DP_ADAPTER_CAP			    0x00f   /* 1.2 */
>  # define DP_FORCE_LOAD_SENSE_CAP	    (1 << 0)
> -- 
> 2.17.1
> 
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Re: [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Rodrigo Vivi]

On Mon, Jul 23, 2018 at 02:27:35PM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values will match 00000h through 0000Fh, except for DPCD_REV,
> MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> 
> Read from DPCD once for all 3 values as this is an expensive operation.
> Spec mentions that all of address space 02200h through 0220Fh should
> contain the right information however currently only 3 values can
> differ.
> 
> There is no address space in the intel_dp->dpcd struct for addresses
> 02200h through 0220Fh, and since so much of the data is a identical,
> simply overwrite the values stored in 00000h through 0000Fh with the
> values that can be overwritten from addresses 02200h through 0220Fh.
> 
> This patch helps with backward compatibility for devices pre DP1.3.
> 
> v2: read only dpcd values which can be affected, remove incorrect check,
> split into drm include changes into separate patch, commit message,
> verbose debugging statements during overwrite.
> v3: white space fixes
> v4: make path dependent on DPCD revision > 1.2
> v5: split into function, removed DPCD rev check
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 54 +++++++++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dde92e4af5d3..ed16b93bfe40 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3731,6 +3731,58 @@ intel_dp_link_down(struct intel_encoder *encoder,
>  	}
>  }
>  
> +static void
> +intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
> +{
> +	/*
> +	 * Prior to DP1.3 the bit represented by
> +	 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
> +	 * if it is set DP_DPCD_REV at 0000h could be at a value less than
> +	 * the true capability of the panel. The only way to check is to
> +	 * then compare 0000h and 2200h.
> +	 */
> +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
> +		uint8_t dpcd_ext[6];
> +
> +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
> +
> +		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
> +				     &dpcd_ext, sizeof(dpcd_ext)) < 0)
> +			return;
> +
> +		if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV])
> +			return;

I'm still missing the debug messages here and above... 

> +
> +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
> +			   sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DPCD_REV],
> +				      dpcd_ext[DP_DPCD_REV]);
> +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> +			       &dpcd_ext[DP_DPCD_REV], sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_MAX_LINK_RATE],
> +				      dpcd_ext[DP_MAX_LINK_RATE]);
> +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
> +			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> +			       sizeof(u8));
> +		}
> +	}
> +}
> +
> +
>  bool
>  intel_dp_read_dpcd(struct intel_dp *intel_dp)
>  {
> @@ -3738,6 +3790,8 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
>  			     sizeof(intel_dp->dpcd)) < 0)
>  		return false; /* aux transfer failed */
>  
> +	intel_dp_extended_receiver_capabilities(intel_dp);
> +
>  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
>  
>  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
> -- 
> 2.17.1
> 
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Re: [PATCH 1/2] drm/dp: add extended receiver capability field present bit

[Manasi Navare]

On Mon, Jul 23, 2018 at 02:27:34PM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> This bit was added to DP Training Aux RD interval with DP 1.3. Via
> descriptiion of the spec this field indicates the panels true
> capabilities are described in DPCD address space 02200h through 022FFh.
> 
> v2: version comment update
> v3: version comment correction, commit message update
> v4: white space correction
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  include/drm/drm_dp_helper.h | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index c01564991a9f..44aaefdc8448 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -123,8 +123,9 @@
>  # define DP_FRAMING_CHANGE_CAP		    (1 << 1)
>  # define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */
>  
> -#define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
> -# define DP_TRAINING_AUX_RD_MASK            0x7F    /* XXX 1.2? */
> +#define DP_TRAINING_AUX_RD_INTERVAL             0x00e   /* XXX 1.2? */
> +# define DP_TRAINING_AUX_RD_MASK                0x7F    /* DP 1.3 */
> +# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT	(1 << 7)/* DP 1.3 */

With the fix mentioned by Rodrigo about having a space as below:
# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT      (1 << 7) /* DP 1.3 */

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

>  
>  #define DP_ADAPTER_CAP			    0x00f   /* 1.2 */
>  # define DP_FORCE_LOAD_SENSE_CAP	    (1 << 0)
> -- 
> 2.17.1
> 
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Re: [PATCH 1/2] drm/dp: add extended receiver capability field present bit

[Manasi Navare]

Pushed to drm-misc-next with the whitespace fix.
Thanks for the patch.

Regards
Manasi

On Mon, Jul 23, 2018 at 02:27:34PM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> This bit was added to DP Training Aux RD interval with DP 1.3. Via
> descriptiion of the spec this field indicates the panels true
> capabilities are described in DPCD address space 02200h through 022FFh.
> 
> v2: version comment update
> v3: version comment correction, commit message update
> v4: white space correction
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  include/drm/drm_dp_helper.h | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index c01564991a9f..44aaefdc8448 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -123,8 +123,9 @@
>  # define DP_FRAMING_CHANGE_CAP		    (1 << 1)
>  # define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */
>  
> -#define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
> -# define DP_TRAINING_AUX_RD_MASK            0x7F    /* XXX 1.2? */
> +#define DP_TRAINING_AUX_RD_INTERVAL             0x00e   /* XXX 1.2? */
> +# define DP_TRAINING_AUX_RD_MASK                0x7F    /* DP 1.3 */
> +# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT	(1 << 7)/* DP 1.3 */
>  
>  #define DP_ADAPTER_CAP			    0x00f   /* 1.2 */
>  # define DP_FORCE_LOAD_SENSE_CAP	    (1 << 0)
> -- 
> 2.17.1
> 
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