* [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT
2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare
@ 2018-07-31 21:06 ` Manasi Navare
2018-07-31 22:17 ` Srivatsa, Anusha
2018-07-31 21:06 ` [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
` (6 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Manasi Navare @ 2018-07-31 21:06 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
This patch defines the DP DSC receiver capability size that gives
total number of DP DSC DPCD registers.
This also adds a missing #defines for DP DSC support missed in the
commit id (ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature")
v3:
* MIN_SLICE_WIDTH = 2560 (Anusha)
* Define DP_DSC_SLICE_WIDTH_MULTIPLIER = 320
v2:
* Add SHIFT define and DECOMPRESSION_EN define misse din prev patch
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
include/drm/drm_dp_helper.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 05cc31b..eb0d86c 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -230,6 +230,8 @@
#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
+# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
+# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
# define DP_DSC_RGB (1 << 0)
@@ -278,6 +280,8 @@
# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
#define DP_DSC_MAX_SLICE_WIDTH 0x06C
+#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
+#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320
#define DP_DSC_SLICE_CAP_2 0x06D
# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
@@ -476,6 +480,7 @@
# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
+# define DP_DECOMPRESSION_EN (1 << 0)
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
# define DP_PSR_ENABLE (1 << 0)
@@ -962,6 +967,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
+#define DP_DSC_RECEIVER_CAP_SIZE 0xf
#define EDP_PSR_RECEIVER_CAP_SIZE 2
#define EDP_DISPLAY_CTL_CAP_SIZE 3
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* RE: [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT
2018-07-31 21:06 ` [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
@ 2018-07-31 22:17 ` Srivatsa, Anusha
0 siblings, 0 replies; 23+ messages in thread
From: Srivatsa, Anusha @ 2018-07-31 22:17 UTC (permalink / raw)
To: Navare, Manasi D, intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org, Singh, Gaurav K
>-----Original Message-----
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D <manasi.d.navare@intel.com>; dri-
>devel@lists.freedesktop.org; Jani Nikula <jani.nikula@linux.intel.com>; Ville
>Syrjala <ville.syrjala@linux.intel.com>; Srivatsa, Anusha
><anusha.srivatsa@intel.com>; Singh, Gaurav K <gaurav.k.singh@intel.com>
>Subject: [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size
>define and missing SHIFT
>
>This patch defines the DP DSC receiver capability size that gives total number of
>DP DSC DPCD registers.
>This also adds a missing #defines for DP DSC support missed in the commit id
>(ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature")
>
>v3:
>* MIN_SLICE_WIDTH = 2560 (Anusha)
>* Define DP_DSC_SLICE_WIDTH_MULTIPLIER = 320
>v2:
>* Add SHIFT define and DECOMPRESSION_EN define misse din prev patch
^^^ "missed in previous"
>Cc: dri-devel@lists.freedesktop.org
>Cc: Jani Nikula <jani.nikula@linux.intel.com>
>Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
>Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Other than the typo, the patch looks good.
Checked with Spec.
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> include/drm/drm_dp_helper.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
>diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
>05cc31b..eb0d86c 100644
>--- a/include/drm/drm_dp_helper.h
>+++ b/include/drm/drm_dp_helper.h
>@@ -230,6 +230,8 @@
> #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
>
> #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
>+# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define
>+DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
>
> #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
> # define DP_DSC_RGB (1 << 0)
>@@ -278,6 +280,8 @@
> # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
>
> #define DP_DSC_MAX_SLICE_WIDTH 0x06C
>+#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
>+#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320
>
> #define DP_DSC_SLICE_CAP_2 0x06D
> # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
>@@ -476,6 +480,7 @@
> # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
>
> #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
>+# define DP_DECOMPRESSION_EN (1 << 0)
>
> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
> # define DP_PSR_ENABLE (1 << 0)
>@@ -962,6 +967,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8
>link_status[DP_LINK_STATUS_SI
>
> #define DP_BRANCH_OUI_HEADER_SIZE 0xc
> #define DP_RECEIVER_CAP_SIZE 0xf
>+#define DP_DSC_RECEIVER_CAP_SIZE 0xf
> #define EDP_PSR_RECEIVER_CAP_SIZE 2
> #define EDP_DISPLAY_CTL_CAP_SIZE 3
>
>--
>2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters
2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare
2018-07-31 21:06 ` [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
@ 2018-07-31 21:06 ` Manasi Navare
2018-07-31 23:33 ` Srivatsa, Anusha
2018-07-31 21:07 ` [PATCH v2 06/23] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare
` (5 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Manasi Navare @ 2018-07-31 21:06 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
This patch adds inline functions and helpers for obtaining
DP sink's supported DSC parameters like DSC sink support,
eDP compressed BPP supported, maximum slice count supported
by the sink devices, DSC line buffer bit depth supported on DP sink,
DSC sink maximum color depth by parsing corresponding DPCD registers.
v4:
* Add helper to give line buf bit depth (Manasi)
v3:
* Use SLICE_CAP_2 for DP (Anusha)
v2:
* Add DSC sink support macro (Jani N)
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 89 +++++++++++++++++++++++++++++++++++++++++
include/drm/drm_dp_helper.h | 30 ++++++++++++++
2 files changed, 119 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 0cccbcb..7dc61d1 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1336,3 +1336,92 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
return 0;
}
EXPORT_SYMBOL(drm_dp_read_desc);
+
+/**
+ * DRM DP Helpers for DSC
+ */
+u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ bool is_edp)
+{
+ u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
+
+ if (is_edp) {
+ /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
+ return 4;
+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
+ return 2;
+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
+ return 1;
+ } else {
+ /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
+ u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
+
+ if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
+ return 24;
+ if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
+ return 20;
+ if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
+ return 16;
+ if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
+ return 12;
+ if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
+ return 10;
+ if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
+ return 8;
+ if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
+ return 6;
+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
+ return 4;
+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
+ return 2;
+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
+
+u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
+
+ switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
+ case DP_DSC_LINE_BUF_BIT_DEPTH_9:
+ return 9;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_10:
+ return 10;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_11:
+ return 11;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_12:
+ return 12;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_13:
+ return 13;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_14:
+ return 14;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_15:
+ return 15;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_16:
+ return 16;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_8:
+ return 8;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
+
+u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ switch (dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]) {
+ case DP_DSC_12_BPC:
+ return 12;
+ case DP_DSC_10_BPC:
+ return 10;
+ case DP_DSC_8_BPC:
+ return 8;
+ }
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index eb0d86c..8c1dbca 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1064,6 +1064,36 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
}
+/* DP/eDP DSC support */
+u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ bool is_edp);
+u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
+u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE]);
+
+static inline bool
+drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
+ DP_DSC_DECOMPRESSION_IS_SUPPORTED;
+}
+
+static inline u16
+drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
+ (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
+ DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
+ DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
+}
+
+static inline u32
+drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ /* Max Slicewidth = Number of Pixels * 320 */
+ return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
+ DP_DSC_SLICE_WIDTH_MULTIPLIER;
+}
+
/*
* DisplayPort AUX channel
*/
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters
2018-07-31 21:06 ` [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
@ 2018-07-31 23:33 ` Srivatsa, Anusha
0 siblings, 0 replies; 23+ messages in thread
From: Srivatsa, Anusha @ 2018-07-31 23:33 UTC (permalink / raw)
To: Navare, Manasi D, intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
>-----Original Message-----
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Singh, Gaurav K
><gaurav.k.singh@intel.com>; dri-devel@lists.freedesktop.org; Jani Nikula
><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>;
>Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Subject: [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC
>parameters
>
>This patch adds inline functions and helpers for obtaining DP sink's supported DSC
>parameters like DSC sink support, eDP compressed BPP supported, maximum slice
>count supported by the sink devices, DSC line buffer bit depth supported on DP
>sink, DSC sink maximum color depth by parsing corresponding DPCD registers.
>
>v4:
>* Add helper to give line buf bit depth (Manasi)
>v3:
>* Use SLICE_CAP_2 for DP (Anusha)
>v2:
>* Add DSC sink support macro (Jani N)
>
>Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
>Cc: dri-devel@lists.freedesktop.org
>Cc: Jani Nikula <jani.nikula@linux.intel.com>
>Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/drm_dp_helper.c | 89
>+++++++++++++++++++++++++++++++++++++++++
> include/drm/drm_dp_helper.h | 30 ++++++++++++++
> 2 files changed, 119 insertions(+)
>
>diff --git a/drivers/gpu/drm/drm_dp_helper.c
>b/drivers/gpu/drm/drm_dp_helper.c index 0cccbcb..7dc61d1 100644
>--- a/drivers/gpu/drm/drm_dp_helper.c
>+++ b/drivers/gpu/drm/drm_dp_helper.c
>@@ -1336,3 +1336,92 @@ int drm_dp_read_desc(struct drm_dp_aux *aux,
>struct drm_dp_desc *desc,
> return 0;
> }
> EXPORT_SYMBOL(drm_dp_read_desc);
>+
>+/**
>+ * DRM DP Helpers for DSC
>+ */
>+u8 drm_dp_dsc_sink_max_slice_count(const u8
>dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
>+ bool is_edp)
>+{
>+ u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
>+
>+ if (is_edp) {
>+ /* For eDP, register DSC_SLICE_CAPABILITIES_1
NIT : the actual register is DSC_SLICE_CAP_1
gives slice count
>*/
>+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
>+ return 4;
>+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
>+ return 2;
>+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
>+ return 1;
>+ } else {
>+ /* For DP, use values from DSC_SLICE_CAP_1 and
>DSC_SLICE_CAP2 */
^^^ DSC_SLICE_CAP_2
>+ u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 -
>DP_DSC_SUPPORT];
>+
>+ if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
>+ return 24;
>+ if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
>+ return 20;
>+ if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
>+ return 16;
>+ if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
>+ return 12;
>+ if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
>+ return 10;
>+ if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
>+ return 8;
>+ if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
>+ return 6;
>+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
>+ return 4;
>+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
>+ return 2;
>+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
>+ return 1;
>+ }
>+
>+ return 0;
>+}
>+EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
>+
>+u8 drm_dp_dsc_sink_line_buf_depth(const u8
>+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
>+{
>+ u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH -
>+DP_DSC_SUPPORT];
>+
>+ switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_9:
>+ return 9;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_10:
>+ return 10;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_11:
>+ return 11;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_12:
>+ return 12;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_13:
>+ return 13;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_14:
>+ return 14;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_15:
>+ return 15;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_16:
>+ return 16;
>+ case DP_DSC_LINE_BUF_BIT_DEPTH_8:
>+ return 8;
>+ }
>+
>+ return 0;
>+}
>+EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
>+
>+u8 drm_dp_dsc_sink_max_color_depth(const u8
>+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
>+{
>+ switch (dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP -
>DP_DSC_SUPPORT]) {
>+ case DP_DSC_12_BPC:
>+ return 12;
>+ case DP_DSC_10_BPC:
>+ return 10;
>+ case DP_DSC_8_BPC:
>+ return 8;
>+ }
>+ return 0;
>+}
>+EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth);
>diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
>eb0d86c..8c1dbca 100644
>--- a/include/drm/drm_dp_helper.h
>+++ b/include/drm/drm_dp_helper.h
>@@ -1064,6 +1064,36 @@ drm_dp_is_branch(const u8
>dpcd[DP_RECEIVER_CAP_SIZE])
> return dpcd[DP_DOWNSTREAMPORT_PRESENT] &
>DP_DWN_STRM_PORT_PRESENT; }
>
>+/* DP/eDP DSC support */
>+u8 drm_dp_dsc_sink_max_slice_count(const u8
>dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
>+ bool is_edp);
>+u8 drm_dp_dsc_sink_line_buf_depth(const u8
>+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
>+u8 drm_dp_dsc_sink_max_color_depth(const u8
>+dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE]);
>+
>+static inline bool
>+drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
>+{
>+ return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
>+ DP_DSC_DECOMPRESSION_IS_SUPPORTED;
>+}
>+
>+static inline u16
>+drm_edp_dsc_sink_output_bpp(const u8
>+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
>+{
>+ return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW -
>DP_DSC_SUPPORT] |
>+ (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI -
>DP_DSC_SUPPORT] &
>+ DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
>+ DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
>+}
>+
>+static inline u32
>+drm_dp_dsc_sink_max_slice_width(const u8
>+dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
>+{
>+ /* Max Slicewidth = Number of Pixels * 320 */
>+ return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
>+ DP_DSC_SLICE_WIDTH_MULTIPLIER;
>+}
>+
> /*
> * DisplayPort AUX channel
> */
>--
>2.7.4
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 06/23] drm/dp: Define payload size for DP SDP PPS packet
2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare
2018-07-31 21:06 ` [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
2018-07-31 21:06 ` [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
@ 2018-07-31 21:07 ` Manasi Navare
2018-07-31 21:07 ` [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
` (4 subsequent siblings)
7 siblings, 0 replies; 23+ messages in thread
From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Anusha Srivatsa, Manasi Navare, dri-devel, Gaurav K Singh
DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
include/drm/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 8c1dbca..0cf2407 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -998,6 +998,7 @@ struct dp_sdp_header {
#define EDP_SDP_HEADER_REVISION_MASK 0x1F
#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
+#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
struct edp_vsc_psr {
struct dp_sdp_header sdp_header;
--
2.7.4
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe
2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare
` (2 preceding siblings ...)
2018-07-31 21:07 ` [PATCH v2 06/23] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare
@ 2018-07-31 21:07 ` Manasi Navare
2018-08-17 19:31 ` Srivatsa, Anusha
2018-08-23 19:40 ` Harry Wentland
2018-07-31 21:07 ` [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
` (3 subsequent siblings)
7 siblings, 2 replies; 23+ messages in thread
From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Anusha Srivatsa, Manasi Navare, dri-devel, Gaurav K Singh
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
include/drm/drm_dsc.h | 365 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 365 insertions(+)
create mode 100644 include/drm/drm_dsc.h
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
new file mode 100644
index 0000000..678e8e6
--- /dev/null
+++ b/include/drm/drm_dsc.h
@@ -0,0 +1,365 @@
+/*
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Manasi Navare <manasi.d.navare@intel.com>
+ */
+
+#ifndef DRM_DSC_H_
+#define DRM_DSC_H_
+
+#include <drm/drm_dp_helper.h>
+
+/* VESA Display Stream Compression DSC 1.2 constants */
+#define DSC_NUM_BUF_RANGES 15
+
+/**
+ * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
+ *
+ * The VESA DSC standard defines picture parameter set (PPS) which display
+ * stream compression encoders must communicate to decoders.
+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
+ * The PPS fields that span over more than a byte should be stored in Big Endian
+ * format.
+ */
+struct picture_parameter_set {
+ /**
+ * @dsc_version:
+ * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
+ * PPS0[7:4] - dsc_version_major: Contains major version of DSC
+ */
+ u8 dsc_version;
+ /**
+ * @pps_identifier:
+ * PPS1[7:0] - Application specific identifier that can be
+ * used to differentiate between different PPS tables.
+ */
+ u8 pps_identifier;
+ /**
+ * @pps_reserved:
+ * PPS2[7:0]- RESERVED Byte
+ */
+ u8 pps_reserved;
+ /**
+ * @pps_3:
+ * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
+ * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
+ * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
+ * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
+ * PPS3[7:4] - bits_per_component: Bits per component for the original
+ * pixels of the encoded picture.
+ * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
+ * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
+ * allowed only when dsc_minor_version = 0x2)
+ */
+ u8 pps_3;
+ /**
+ * @pps_4:
+ * PPS4[1:0] -These are the most significant 2 bits of
+ * compressed BPP bits_per_pixel[9:0] syntax element.
+ * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
+ * PPS4[3] - simple_422: Indicates if decoder drops samples to
+ * reconstruct the 4:2:2 picture.
+ * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
+ * active.
+ * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
+ * groups in picture
+ * PPS4[7:6] - Reseved bits
+ */
+ u8 pps_4;
+ /**
+ * @bits_per_pixel_low:
+ * PPS5[7:0] - This indicates the lower significant 8 bits of
+ * the compressed BPP bits_per_pixel[9:0] element.
+ */
+ u8 bits_per_pixel_low;
+ /**
+ * @pic_height:
+ * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
+ * within the raster.
+ */
+ __be16 pic_height;
+ /**
+ * @pic_width:
+ * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
+ * the raster.
+ */
+ __be16 pic_width;
+ /**
+ * @slice_height:
+ * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
+ */
+ __be16 slice_height;
+ /**
+ * @slice_width:
+ * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
+ */
+ __be16 slice_width;
+ /**
+ * @chunk_size:
+ * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
+ * that are used for slice multiplexing.
+ */
+ __be16 chunk_size;
+ /**
+ * @initial_xmit_delay_high:
+ * PPS16[1:0] - Most Significant two bits of initial transmission delay.
+ * It specifies the number of pixel times that the encoder waits before
+ * transmitting data from its rate buffer.
+ * PPS16[7:2] - Reserved
+ */
+ u8 initial_xmit_delay_high;
+ /**
+ * @initial_xmit_delay_low:
+ * PPS17[7:0] - Least significant 8 bits of initial transmission delay.
+ */
+ u8 initial_xmit_delay_low;
+ /**
+ * @initial_dec_delay:
+ *
+ * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
+ * of pixel times that the decoder accumulates data in its rate buffer
+ * before starting to decode and output pixels.
+ */
+ __be16 initial_dec_delay;
+ /**
+ * @pps20_reserved:
+ *
+ * PPS20[7:0] - Reserved
+ */
+ u8 pps20_reserved;
+ /**
+ * @initial_scale_value:
+ * PPS21[5:0] - Initial rcXformScale factor used at beginning
+ * of a slice.
+ * PPS21[7:6] - Reserved
+ */
+ u8 initial_scale_value;
+ /**
+ * @scale_increment_interval:
+ * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
+ * the rcXformScale factor at end of a slice.
+ */
+ __be16 scale_increment_interval;
+ /**
+ * @scale_decrement_interval_high:
+ * PPS24[3:0] - Higher 4 bits indicating number of group times between
+ * decrementing the rcXformScale factor at beginning of a slice.
+ * PPS24[7:4] - Reserved
+ */
+ u8 scale_decrement_interval_high;
+ /**
+ * @scale_decrement_interval_low:
+ * PPS25[7:0] - Lower 8 bits of scale decrement interval
+ */
+ u8 scale_decrement_interval_low;
+ /**
+ * @pps26_reserved:
+ * PPS26[7:0]
+ */
+ u8 pps26_reserved;
+ /**
+ * @first_line_bpg_offset:
+ * PPS27[4:0] - Number of additional bits that are allocated
+ * for each group on first line of a slice.
+ * PPS27[7:5] - Reserved
+ */
+ u8 first_line_bpg_offset;
+ /**
+ * @nfl_bpg_offset:
+ * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
+ * deallocated for each group for groups after the first line of slice.
+ */
+ __be16 nfl_bpg_offset;
+ /**
+ * @slice_bpg_offset:
+ * PPS30, PPS31[7:0] - Number of bits that are deallocated for each
+ * group to enforce the slice constraint.
+ */
+ __be16 slice_bpg_offset;
+ /**
+ * @initial_offset:
+ * PPS32,33[7:0] - Initial value for rcXformOffset
+ */
+ __be16 initial_offset;
+ /**
+ * @final_offset:
+ * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
+ */
+ __be16 final_offset;
+ /**
+ * @flatness_min_qp:
+ * PPS36[4:0] - Minimum QP at which flatness is signaled and
+ * flatness QP adjustment is made.
+ * PPS36[7:5] - Reserved
+ */
+ u8 flatness_min_qp;
+ /**
+ * @flatness_max_qp:
+ * PPS37[4:0] - Max QP at which flatness is signalled and
+ * the flatness adjustment is made.
+ * PPS37[7:5] - Reserved
+ */
+ u8 flatness_max_qp;
+ /**
+ * @rc_model_size:
+ * PPS38,39[7:0] - Number of bits within RC Model.
+ */
+ __be16 rc_model_size;
+ /**
+ * @rc_edge_factor:
+ * PPS40[3:0] - Ratio of current activity vs, previous
+ * activity to determine presence of edge.
+ * PPS40[7:4] - Reserved
+ */
+ u8 rc_edge_factor;
+ /**
+ * @rc_quant_incr_limit0:
+ * PPS41[4:0] - QP threshold used in short term RC
+ * PPS41[7:5] - Reserved
+ */
+ u8 rc_quant_incr_limit0;
+ /**
+ * @rc_quant_incr_limit1:
+ * PPS42[4:0] - QP threshold used in short term RC
+ * PPS42[7:5] - Reserved
+ */
+ u8 rc_quant_incr_limit1;
+ /**
+ * @rc_tgt_offset:
+ * PPS43[3:0] - Lower end of the variability range around the target
+ * bits per group that is allowed by short term RC.
+ * PPS43[7:4]- Upper end of the variability range around the target
+ * bits per group that i allowed by short term rc.
+ */
+ u8 rc_tgt_offset;
+ /**
+ * @rc_buf_thresh:
+ * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
+ * the 15 ranges defined by 14 thresholds.
+ */
+ u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+ /**
+ * @rc_range_parameters:
+ * PPS58[7:0] - PPS87[7:0]
+ * Parameters that correspond to each of the 15 ranges.
+ */
+ __be16 rc_range_parameters[DSC_NUM_BUF_RANGES];
+ /**
+ * @native_422_420:
+ * PPS88[0] - 0 = Native 4:2:2 not used
+ * 1 = Native 4:2:2 used
+ * PPS88[1] - 0 = Native 4:2:0 not use
+ * 1 = Native 4:2:0 used
+ * PPS88[7:2] - Reserved 6 bits
+ */
+ u8 native_422_420;
+ /**
+ * @second_line_bpg_offset:
+ * PPS89[4:0] - Additional bits/group budget for the
+ * second line of a slice in Native 4:2:0 mode.
+ * Set to 0 if DSC minor version is 1 or native420 is 0.
+ * PPS89[7:5] - Reserved
+ */
+ u8 second_line_bpg_offset;
+ /**
+ * @nsl_bpg_offset:
+ * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
+ * for each group that is not in the second line of a slice.
+ */
+ __be16 nsl_bpg_offset;
+ /**
+ * @second_line_offset_adj:
+ * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
+ * line in Native 4:2:0 mode.
+ */
+ __be16 second_line_offset_adj;
+ /**
+ * @pps_long_94_reserved:
+ * PPS 94, 95, 96, 97 - Reserved
+ */
+ u32 pps_long_94_reserved;
+ /**
+ * @pps_long_98_reserved:
+ * PPS 98, 99, 100, 101 - Reserved
+ */
+ u32 pps_long_98_reserved;
+ /**
+ * @pps_long_102_reserved:
+ * PPS 102, 103, 104, 105 - Reserved
+ */
+ u32 pps_long_102_reserved;
+ /**
+ * @pps_long_106_reserved:
+ * PPS 106, 107, 108, 109 - reserved
+ */
+ u32 pps_long_106_reserved;
+ /**
+ * @pps_long_110_reserved:
+ * PPS 110, 111, 112, 113 - reserved
+ */
+ u32 pps_long_110_reserved;
+ /**
+ * @pps_long_114_reserved:
+ * PPS 114 - 117 - reserved
+ */
+ u32 pps_long_114_reserved;
+ /**
+ * @pps_long_118_reserved:
+ * PPS 118 - 121 - reserved
+ */
+ u32 pps_long_118_reserved;
+ /**
+ * @pps_long_122_reserved:
+ * PPS 122- 125 - reserved
+ */
+ u32 pps_long_122_reserved;
+ /**
+ * @pps_short_126_reserved:
+ * PPS 126, 127 - reserved
+ */
+ __be16 pps_short_126_reserved;
+};
+
+/**
+ * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter
+ * Set Metadata
+ *
+ * This structure represents the DSC PPS infoframe required to send the Picture
+ * Parameter Set metadata required before enabling VESA Display Stream
+ * Compression. This is based on the DP Secondary Data Packet structure and
+ * comprises of SDP Header as defined in drm_dp_helper.h and PPS payload.
+ *
+ * @pps_header:
+ *
+ * Header for PPS as per DP SDP header format
+ *
+ * @pps_payload:
+ *
+ * PPS payload fields as per DSC specification Table 4-1
+ */
+struct drm_dsc_pps_infoframe {
+ struct dp_sdp_header pps_header;
+ struct picture_parameter_set pps_payload;
+} __packed;
+
+#endif /* _DRM_DSC_H_ */
--
2.7.4
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^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe
2018-07-31 21:07 ` [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
@ 2018-08-17 19:31 ` Srivatsa, Anusha
2018-08-23 20:08 ` Manasi Navare
2018-08-23 19:40 ` Harry Wentland
1 sibling, 1 reply; 23+ messages in thread
From: Srivatsa, Anusha @ 2018-08-17 19:31 UTC (permalink / raw)
To: Navare, Manasi D, intel-gfx@lists.freedesktop.org
Cc: Harry Wentland, dri-devel@lists.freedesktop.org
This patch needs to now incorporate the newly added slice_row_per_frame parameter in PPS_16.
Anusha
>-----Original Message-----
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Singh, Gaurav K
><gaurav.k.singh@intel.com>; dri-devel@lists.freedesktop.org; Jani Nikula
><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>;
>Srivatsa, Anusha <anusha.srivatsa@intel.com>; Harry Wentland
><harry.wentland@amd.com>
>Subject: [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS
>infoframe
>
>This patch defines a new header file for all the DSC 1.2 structures and creates a
>structure for PPS infoframe which will be used to send picture parameter set
>secondary data packet for display stream compression.
>All the PPS infoframe syntax elements are taken from DSC 1.2 specification from
>VESA.
>
>Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
>Cc: dri-devel@lists.freedesktop.org
>Cc: Jani Nikula <jani.nikula@linux.intel.com>
>Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Cc: Harry Wentland <harry.wentland@amd.com>
>Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
>---
> include/drm/drm_dsc.h | 365
>++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 365 insertions(+)
> create mode 100644 include/drm/drm_dsc.h
>
>diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h new file mode
>100644 index 0000000..678e8e6
>--- /dev/null
>+++ b/include/drm/drm_dsc.h
>@@ -0,0 +1,365 @@
>+/*
>+ * Copyright (C) 2018 Intel Corp.
>+ *
>+ * Permission is hereby granted, free of charge, to any person
>+obtaining a
>+ * copy of this software and associated documentation files (the
>+"Software"),
>+ * to deal in the Software without restriction, including without
>+limitation
>+ * the rights to use, copy, modify, merge, publish, distribute,
>+sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom
>+the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be
>+included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>+EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>+MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
>EVENT
>+SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
>+DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
>+OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
>USE
>+OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors:
>+ * Manasi Navare <manasi.d.navare@intel.com> */
>+
>+#ifndef DRM_DSC_H_
>+#define DRM_DSC_H_
>+
>+#include <drm/drm_dp_helper.h>
>+
>+/* VESA Display Stream Compression DSC 1.2 constants */
>+#define DSC_NUM_BUF_RANGES 15
>+
>+/**
>+ * struct picture_parameter_set - Represents 128 bytes of Picture
>+Parameter Set
>+ *
>+ * The VESA DSC standard defines picture parameter set (PPS) which
>+display
>+ * stream compression encoders must communicate to decoders.
>+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The
>+fields in
>+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
>+ * The PPS fields that span over more than a byte should be stored in
>+Big Endian
>+ * format.
>+ */
>+struct picture_parameter_set {
>+ /**
>+ * @dsc_version:
>+ * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
>+ * PPS0[7:4] - dsc_version_major: Contains major version of DSC
>+ */
>+ u8 dsc_version;
>+ /**
>+ * @pps_identifier:
>+ * PPS1[7:0] - Application specific identifier that can be
>+ * used to differentiate between different PPS tables.
>+ */
>+ u8 pps_identifier;
>+ /**
>+ * @pps_reserved:
>+ * PPS2[7:0]- RESERVED Byte
>+ */
>+ u8 pps_reserved;
>+ /**
>+ * @pps_3:
>+ * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
>+ * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
>+ * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
>+ * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
>+ * PPS3[7:4] - bits_per_component: Bits per component for the original
>+ * pixels of the encoded picture.
>+ * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
>+ * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
>+ * allowed only when dsc_minor_version = 0x2)
>+ */
>+ u8 pps_3;
>+ /**
>+ * @pps_4:
>+ * PPS4[1:0] -These are the most significant 2 bits of
>+ * compressed BPP bits_per_pixel[9:0] syntax element.
>+ * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
>+ * PPS4[3] - simple_422: Indicates if decoder drops samples to
>+ * reconstruct the 4:2:2 picture.
>+ * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
>+ * active.
>+ * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
>+ * groups in picture
>+ * PPS4[7:6] - Reseved bits
>+ */
>+ u8 pps_4;
>+ /**
>+ * @bits_per_pixel_low:
>+ * PPS5[7:0] - This indicates the lower significant 8 bits of
>+ * the compressed BPP bits_per_pixel[9:0] element.
>+ */
>+ u8 bits_per_pixel_low;
>+ /**
>+ * @pic_height:
>+ * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
>+ * within the raster.
>+ */
>+ __be16 pic_height;
>+ /**
>+ * @pic_width:
>+ * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
>+ * the raster.
>+ */
>+ __be16 pic_width;
>+ /**
>+ * @slice_height:
>+ * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
>+ */
>+ __be16 slice_height;
>+ /**
>+ * @slice_width:
>+ * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
>+ */
>+ __be16 slice_width;
>+ /**
>+ * @chunk_size:
>+ * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
>+ * that are used for slice multiplexing.
>+ */
>+ __be16 chunk_size;
>+ /**
>+ * @initial_xmit_delay_high:
>+ * PPS16[1:0] - Most Significant two bits of initial transmission delay.
>+ * It specifies the number of pixel times that the encoder waits before
>+ * transmitting data from its rate buffer.
>+ * PPS16[7:2] - Reserved
>+ */
>+ u8 initial_xmit_delay_high;
>+ /**
>+ * @initial_xmit_delay_low:
>+ * PPS17[7:0] - Least significant 8 bits of initial transmission delay.
>+ */
>+ u8 initial_xmit_delay_low;
>+ /**
>+ * @initial_dec_delay:
>+ *
>+ * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
>+ * of pixel times that the decoder accumulates data in its rate buffer
>+ * before starting to decode and output pixels.
>+ */
>+ __be16 initial_dec_delay;
>+ /**
>+ * @pps20_reserved:
>+ *
>+ * PPS20[7:0] - Reserved
>+ */
>+ u8 pps20_reserved;
>+ /**
>+ * @initial_scale_value:
>+ * PPS21[5:0] - Initial rcXformScale factor used at beginning
>+ * of a slice.
>+ * PPS21[7:6] - Reserved
>+ */
>+ u8 initial_scale_value;
>+ /**
>+ * @scale_increment_interval:
>+ * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
>+ * the rcXformScale factor at end of a slice.
>+ */
>+ __be16 scale_increment_interval;
>+ /**
>+ * @scale_decrement_interval_high:
>+ * PPS24[3:0] - Higher 4 bits indicating number of group times between
>+ * decrementing the rcXformScale factor at beginning of a slice.
>+ * PPS24[7:4] - Reserved
>+ */
>+ u8 scale_decrement_interval_high;
>+ /**
>+ * @scale_decrement_interval_low:
>+ * PPS25[7:0] - Lower 8 bits of scale decrement interval
>+ */
>+ u8 scale_decrement_interval_low;
>+ /**
>+ * @pps26_reserved:
>+ * PPS26[7:0]
>+ */
>+ u8 pps26_reserved;
>+ /**
>+ * @first_line_bpg_offset:
>+ * PPS27[4:0] - Number of additional bits that are allocated
>+ * for each group on first line of a slice.
>+ * PPS27[7:5] - Reserved
>+ */
>+ u8 first_line_bpg_offset;
>+ /**
>+ * @nfl_bpg_offset:
>+ * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
>+ * deallocated for each group for groups after the first line of slice.
>+ */
>+ __be16 nfl_bpg_offset;
>+ /**
>+ * @slice_bpg_offset:
>+ * PPS30, PPS31[7:0] - Number of bits that are deallocated for each
>+ * group to enforce the slice constraint.
>+ */
>+ __be16 slice_bpg_offset;
>+ /**
>+ * @initial_offset:
>+ * PPS32,33[7:0] - Initial value for rcXformOffset
>+ */
>+ __be16 initial_offset;
>+ /**
>+ * @final_offset:
>+ * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
>+ */
>+ __be16 final_offset;
>+ /**
>+ * @flatness_min_qp:
>+ * PPS36[4:0] - Minimum QP at which flatness is signaled and
>+ * flatness QP adjustment is made.
>+ * PPS36[7:5] - Reserved
>+ */
>+ u8 flatness_min_qp;
>+ /**
>+ * @flatness_max_qp:
>+ * PPS37[4:0] - Max QP at which flatness is signalled and
>+ * the flatness adjustment is made.
>+ * PPS37[7:5] - Reserved
>+ */
>+ u8 flatness_max_qp;
>+ /**
>+ * @rc_model_size:
>+ * PPS38,39[7:0] - Number of bits within RC Model.
>+ */
>+ __be16 rc_model_size;
>+ /**
>+ * @rc_edge_factor:
>+ * PPS40[3:0] - Ratio of current activity vs, previous
>+ * activity to determine presence of edge.
>+ * PPS40[7:4] - Reserved
>+ */
>+ u8 rc_edge_factor;
>+ /**
>+ * @rc_quant_incr_limit0:
>+ * PPS41[4:0] - QP threshold used in short term RC
>+ * PPS41[7:5] - Reserved
>+ */
>+ u8 rc_quant_incr_limit0;
>+ /**
>+ * @rc_quant_incr_limit1:
>+ * PPS42[4:0] - QP threshold used in short term RC
>+ * PPS42[7:5] - Reserved
>+ */
>+ u8 rc_quant_incr_limit1;
>+ /**
>+ * @rc_tgt_offset:
>+ * PPS43[3:0] - Lower end of the variability range around the target
>+ * bits per group that is allowed by short term RC.
>+ * PPS43[7:4]- Upper end of the variability range around the target
>+ * bits per group that i allowed by short term rc.
>+ */
>+ u8 rc_tgt_offset;
>+ /**
>+ * @rc_buf_thresh:
>+ * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
>+ * the 15 ranges defined by 14 thresholds.
>+ */
>+ u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
>+ /**
>+ * @rc_range_parameters:
>+ * PPS58[7:0] - PPS87[7:0]
>+ * Parameters that correspond to each of the 15 ranges.
>+ */
>+ __be16 rc_range_parameters[DSC_NUM_BUF_RANGES];
>+ /**
>+ * @native_422_420:
>+ * PPS88[0] - 0 = Native 4:2:2 not used
>+ * 1 = Native 4:2:2 used
>+ * PPS88[1] - 0 = Native 4:2:0 not use
>+ * 1 = Native 4:2:0 used
>+ * PPS88[7:2] - Reserved 6 bits
>+ */
>+ u8 native_422_420;
>+ /**
>+ * @second_line_bpg_offset:
>+ * PPS89[4:0] - Additional bits/group budget for the
>+ * second line of a slice in Native 4:2:0 mode.
>+ * Set to 0 if DSC minor version is 1 or native420 is 0.
>+ * PPS89[7:5] - Reserved
>+ */
>+ u8 second_line_bpg_offset;
>+ /**
>+ * @nsl_bpg_offset:
>+ * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
>+ * for each group that is not in the second line of a slice.
>+ */
>+ __be16 nsl_bpg_offset;
>+ /**
>+ * @second_line_offset_adj:
>+ * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
>+ * line in Native 4:2:0 mode.
>+ */
>+ __be16 second_line_offset_adj;
>+ /**
>+ * @pps_long_94_reserved:
>+ * PPS 94, 95, 96, 97 - Reserved
>+ */
>+ u32 pps_long_94_reserved;
>+ /**
>+ * @pps_long_98_reserved:
>+ * PPS 98, 99, 100, 101 - Reserved
>+ */
>+ u32 pps_long_98_reserved;
>+ /**
>+ * @pps_long_102_reserved:
>+ * PPS 102, 103, 104, 105 - Reserved
>+ */
>+ u32 pps_long_102_reserved;
>+ /**
>+ * @pps_long_106_reserved:
>+ * PPS 106, 107, 108, 109 - reserved
>+ */
>+ u32 pps_long_106_reserved;
>+ /**
>+ * @pps_long_110_reserved:
>+ * PPS 110, 111, 112, 113 - reserved
>+ */
>+ u32 pps_long_110_reserved;
>+ /**
>+ * @pps_long_114_reserved:
>+ * PPS 114 - 117 - reserved
>+ */
>+ u32 pps_long_114_reserved;
>+ /**
>+ * @pps_long_118_reserved:
>+ * PPS 118 - 121 - reserved
>+ */
>+ u32 pps_long_118_reserved;
>+ /**
>+ * @pps_long_122_reserved:
>+ * PPS 122- 125 - reserved
>+ */
>+ u32 pps_long_122_reserved;
>+ /**
>+ * @pps_short_126_reserved:
>+ * PPS 126, 127 - reserved
>+ */
>+ __be16 pps_short_126_reserved;
>+};
>+
>+/**
>+ * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture
>+Parameter
>+ * Set Metadata
>+ *
>+ * This structure represents the DSC PPS infoframe required to send the
>+Picture
>+ * Parameter Set metadata required before enabling VESA Display Stream
>+ * Compression. This is based on the DP Secondary Data Packet structure
>+and
>+ * comprises of SDP Header as defined in drm_dp_helper.h and PPS payload.
>+ *
>+ * @pps_header:
>+ *
>+ * Header for PPS as per DP SDP header format
>+ *
>+ * @pps_payload:
>+ *
>+ * PPS payload fields as per DSC specification Table 4-1 */ struct
>+drm_dsc_pps_infoframe {
>+ struct dp_sdp_header pps_header;
>+ struct picture_parameter_set pps_payload; } __packed;
>+
>+#endif /* _DRM_DSC_H_ */
>--
>2.7.4
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^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe
2018-08-17 19:31 ` Srivatsa, Anusha
@ 2018-08-23 20:08 ` Manasi Navare
0 siblings, 0 replies; 23+ messages in thread
From: Manasi Navare @ 2018-08-23 20:08 UTC (permalink / raw)
To: Srivatsa, Anusha
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
Singh, Gaurav K
On Fri, Aug 17, 2018 at 12:31:51PM -0700, Srivatsa, Anusha wrote:
> This patch needs to now incorporate the newly added slice_row_per_frame parameter in PPS_16.
Nope, the slice_row_per_frame and slice_per_line are only required to configure PPS
on the source side. They are not DSC spec related PPS parameters.
Manasi
>
> Anusha
>
> >-----Original Message-----
> >From: Navare, Manasi D
> >Sent: Tuesday, July 31, 2018 2:07 PM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Singh, Gaurav K
> ><gaurav.k.singh@intel.com>; dri-devel@lists.freedesktop.org; Jani Nikula
> ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>;
> >Srivatsa, Anusha <anusha.srivatsa@intel.com>; Harry Wentland
> ><harry.wentland@amd.com>
> >Subject: [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS
> >infoframe
> >
> >This patch defines a new header file for all the DSC 1.2 structures and creates a
> >structure for PPS infoframe which will be used to send picture parameter set
> >secondary data packet for display stream compression.
> >All the PPS infoframe syntax elements are taken from DSC 1.2 specification from
> >VESA.
> >
> >Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
> >Cc: dri-devel@lists.freedesktop.org
> >Cc: Jani Nikula <jani.nikula@linux.intel.com>
> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >Cc: Harry Wentland <harry.wentland@amd.com>
> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> >---
> > include/drm/drm_dsc.h | 365
> >++++++++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 365 insertions(+)
> > create mode 100644 include/drm/drm_dsc.h
> >
> >diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h new file mode
> >100644 index 0000000..678e8e6
> >--- /dev/null
> >+++ b/include/drm/drm_dsc.h
> >@@ -0,0 +1,365 @@
> >+/*
> >+ * Copyright (C) 2018 Intel Corp.
> >+ *
> >+ * Permission is hereby granted, free of charge, to any person
> >+obtaining a
> >+ * copy of this software and associated documentation files (the
> >+"Software"),
> >+ * to deal in the Software without restriction, including without
> >+limitation
> >+ * the rights to use, copy, modify, merge, publish, distribute,
> >+sublicense,
> >+ * and/or sell copies of the Software, and to permit persons to whom
> >+the
> >+ * Software is furnished to do so, subject to the following conditions:
> >+ *
> >+ * The above copyright notice and this permission notice shall be
> >+included in
> >+ * all copies or substantial portions of the Software.
> >+ *
> >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >+EXPRESS OR
> >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> >+MERCHANTABILITY,
> >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> >EVENT
> >+SHALL
> >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> >+DAMAGES OR
> >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> >+OTHERWISE,
> >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
> >USE
> >+OR
> >+ * OTHER DEALINGS IN THE SOFTWARE.
> >+ *
> >+ * Authors:
> >+ * Manasi Navare <manasi.d.navare@intel.com> */
> >+
> >+#ifndef DRM_DSC_H_
> >+#define DRM_DSC_H_
> >+
> >+#include <drm/drm_dp_helper.h>
> >+
> >+/* VESA Display Stream Compression DSC 1.2 constants */
> >+#define DSC_NUM_BUF_RANGES 15
> >+
> >+/**
> >+ * struct picture_parameter_set - Represents 128 bytes of Picture
> >+Parameter Set
> >+ *
> >+ * The VESA DSC standard defines picture parameter set (PPS) which
> >+display
> >+ * stream compression encoders must communicate to decoders.
> >+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The
> >+fields in
> >+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
> >+ * The PPS fields that span over more than a byte should be stored in
> >+Big Endian
> >+ * format.
> >+ */
> >+struct picture_parameter_set {
> >+ /**
> >+ * @dsc_version:
> >+ * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
> >+ * PPS0[7:4] - dsc_version_major: Contains major version of DSC
> >+ */
> >+ u8 dsc_version;
> >+ /**
> >+ * @pps_identifier:
> >+ * PPS1[7:0] - Application specific identifier that can be
> >+ * used to differentiate between different PPS tables.
> >+ */
> >+ u8 pps_identifier;
> >+ /**
> >+ * @pps_reserved:
> >+ * PPS2[7:0]- RESERVED Byte
> >+ */
> >+ u8 pps_reserved;
> >+ /**
> >+ * @pps_3:
> >+ * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
> >+ * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
> >+ * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
> >+ * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
> >+ * PPS3[7:4] - bits_per_component: Bits per component for the original
> >+ * pixels of the encoded picture.
> >+ * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
> >+ * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
> >+ * allowed only when dsc_minor_version = 0x2)
> >+ */
> >+ u8 pps_3;
> >+ /**
> >+ * @pps_4:
> >+ * PPS4[1:0] -These are the most significant 2 bits of
> >+ * compressed BPP bits_per_pixel[9:0] syntax element.
> >+ * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
> >+ * PPS4[3] - simple_422: Indicates if decoder drops samples to
> >+ * reconstruct the 4:2:2 picture.
> >+ * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
> >+ * active.
> >+ * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
> >+ * groups in picture
> >+ * PPS4[7:6] - Reseved bits
> >+ */
> >+ u8 pps_4;
> >+ /**
> >+ * @bits_per_pixel_low:
> >+ * PPS5[7:0] - This indicates the lower significant 8 bits of
> >+ * the compressed BPP bits_per_pixel[9:0] element.
> >+ */
> >+ u8 bits_per_pixel_low;
> >+ /**
> >+ * @pic_height:
> >+ * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
> >+ * within the raster.
> >+ */
> >+ __be16 pic_height;
> >+ /**
> >+ * @pic_width:
> >+ * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
> >+ * the raster.
> >+ */
> >+ __be16 pic_width;
> >+ /**
> >+ * @slice_height:
> >+ * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
> >+ */
> >+ __be16 slice_height;
> >+ /**
> >+ * @slice_width:
> >+ * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
> >+ */
> >+ __be16 slice_width;
> >+ /**
> >+ * @chunk_size:
> >+ * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
> >+ * that are used for slice multiplexing.
> >+ */
> >+ __be16 chunk_size;
> >+ /**
> >+ * @initial_xmit_delay_high:
> >+ * PPS16[1:0] - Most Significant two bits of initial transmission delay.
> >+ * It specifies the number of pixel times that the encoder waits before
> >+ * transmitting data from its rate buffer.
> >+ * PPS16[7:2] - Reserved
> >+ */
> >+ u8 initial_xmit_delay_high;
> >+ /**
> >+ * @initial_xmit_delay_low:
> >+ * PPS17[7:0] - Least significant 8 bits of initial transmission delay.
> >+ */
> >+ u8 initial_xmit_delay_low;
> >+ /**
> >+ * @initial_dec_delay:
> >+ *
> >+ * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
> >+ * of pixel times that the decoder accumulates data in its rate buffer
> >+ * before starting to decode and output pixels.
> >+ */
> >+ __be16 initial_dec_delay;
> >+ /**
> >+ * @pps20_reserved:
> >+ *
> >+ * PPS20[7:0] - Reserved
> >+ */
> >+ u8 pps20_reserved;
> >+ /**
> >+ * @initial_scale_value:
> >+ * PPS21[5:0] - Initial rcXformScale factor used at beginning
> >+ * of a slice.
> >+ * PPS21[7:6] - Reserved
> >+ */
> >+ u8 initial_scale_value;
> >+ /**
> >+ * @scale_increment_interval:
> >+ * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
> >+ * the rcXformScale factor at end of a slice.
> >+ */
> >+ __be16 scale_increment_interval;
> >+ /**
> >+ * @scale_decrement_interval_high:
> >+ * PPS24[3:0] - Higher 4 bits indicating number of group times between
> >+ * decrementing the rcXformScale factor at beginning of a slice.
> >+ * PPS24[7:4] - Reserved
> >+ */
> >+ u8 scale_decrement_interval_high;
> >+ /**
> >+ * @scale_decrement_interval_low:
> >+ * PPS25[7:0] - Lower 8 bits of scale decrement interval
> >+ */
> >+ u8 scale_decrement_interval_low;
> >+ /**
> >+ * @pps26_reserved:
> >+ * PPS26[7:0]
> >+ */
> >+ u8 pps26_reserved;
> >+ /**
> >+ * @first_line_bpg_offset:
> >+ * PPS27[4:0] - Number of additional bits that are allocated
> >+ * for each group on first line of a slice.
> >+ * PPS27[7:5] - Reserved
> >+ */
> >+ u8 first_line_bpg_offset;
> >+ /**
> >+ * @nfl_bpg_offset:
> >+ * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
> >+ * deallocated for each group for groups after the first line of slice.
> >+ */
> >+ __be16 nfl_bpg_offset;
> >+ /**
> >+ * @slice_bpg_offset:
> >+ * PPS30, PPS31[7:0] - Number of bits that are deallocated for each
> >+ * group to enforce the slice constraint.
> >+ */
> >+ __be16 slice_bpg_offset;
> >+ /**
> >+ * @initial_offset:
> >+ * PPS32,33[7:0] - Initial value for rcXformOffset
> >+ */
> >+ __be16 initial_offset;
> >+ /**
> >+ * @final_offset:
> >+ * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
> >+ */
> >+ __be16 final_offset;
> >+ /**
> >+ * @flatness_min_qp:
> >+ * PPS36[4:0] - Minimum QP at which flatness is signaled and
> >+ * flatness QP adjustment is made.
> >+ * PPS36[7:5] - Reserved
> >+ */
> >+ u8 flatness_min_qp;
> >+ /**
> >+ * @flatness_max_qp:
> >+ * PPS37[4:0] - Max QP at which flatness is signalled and
> >+ * the flatness adjustment is made.
> >+ * PPS37[7:5] - Reserved
> >+ */
> >+ u8 flatness_max_qp;
> >+ /**
> >+ * @rc_model_size:
> >+ * PPS38,39[7:0] - Number of bits within RC Model.
> >+ */
> >+ __be16 rc_model_size;
> >+ /**
> >+ * @rc_edge_factor:
> >+ * PPS40[3:0] - Ratio of current activity vs, previous
> >+ * activity to determine presence of edge.
> >+ * PPS40[7:4] - Reserved
> >+ */
> >+ u8 rc_edge_factor;
> >+ /**
> >+ * @rc_quant_incr_limit0:
> >+ * PPS41[4:0] - QP threshold used in short term RC
> >+ * PPS41[7:5] - Reserved
> >+ */
> >+ u8 rc_quant_incr_limit0;
> >+ /**
> >+ * @rc_quant_incr_limit1:
> >+ * PPS42[4:0] - QP threshold used in short term RC
> >+ * PPS42[7:5] - Reserved
> >+ */
> >+ u8 rc_quant_incr_limit1;
> >+ /**
> >+ * @rc_tgt_offset:
> >+ * PPS43[3:0] - Lower end of the variability range around the target
> >+ * bits per group that is allowed by short term RC.
> >+ * PPS43[7:4]- Upper end of the variability range around the target
> >+ * bits per group that i allowed by short term rc.
> >+ */
> >+ u8 rc_tgt_offset;
> >+ /**
> >+ * @rc_buf_thresh:
> >+ * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
> >+ * the 15 ranges defined by 14 thresholds.
> >+ */
> >+ u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
> >+ /**
> >+ * @rc_range_parameters:
> >+ * PPS58[7:0] - PPS87[7:0]
> >+ * Parameters that correspond to each of the 15 ranges.
> >+ */
> >+ __be16 rc_range_parameters[DSC_NUM_BUF_RANGES];
> >+ /**
> >+ * @native_422_420:
> >+ * PPS88[0] - 0 = Native 4:2:2 not used
> >+ * 1 = Native 4:2:2 used
> >+ * PPS88[1] - 0 = Native 4:2:0 not use
> >+ * 1 = Native 4:2:0 used
> >+ * PPS88[7:2] - Reserved 6 bits
> >+ */
> >+ u8 native_422_420;
> >+ /**
> >+ * @second_line_bpg_offset:
> >+ * PPS89[4:0] - Additional bits/group budget for the
> >+ * second line of a slice in Native 4:2:0 mode.
> >+ * Set to 0 if DSC minor version is 1 or native420 is 0.
> >+ * PPS89[7:5] - Reserved
> >+ */
> >+ u8 second_line_bpg_offset;
> >+ /**
> >+ * @nsl_bpg_offset:
> >+ * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
> >+ * for each group that is not in the second line of a slice.
> >+ */
> >+ __be16 nsl_bpg_offset;
> >+ /**
> >+ * @second_line_offset_adj:
> >+ * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
> >+ * line in Native 4:2:0 mode.
> >+ */
> >+ __be16 second_line_offset_adj;
> >+ /**
> >+ * @pps_long_94_reserved:
> >+ * PPS 94, 95, 96, 97 - Reserved
> >+ */
> >+ u32 pps_long_94_reserved;
> >+ /**
> >+ * @pps_long_98_reserved:
> >+ * PPS 98, 99, 100, 101 - Reserved
> >+ */
> >+ u32 pps_long_98_reserved;
> >+ /**
> >+ * @pps_long_102_reserved:
> >+ * PPS 102, 103, 104, 105 - Reserved
> >+ */
> >+ u32 pps_long_102_reserved;
> >+ /**
> >+ * @pps_long_106_reserved:
> >+ * PPS 106, 107, 108, 109 - reserved
> >+ */
> >+ u32 pps_long_106_reserved;
> >+ /**
> >+ * @pps_long_110_reserved:
> >+ * PPS 110, 111, 112, 113 - reserved
> >+ */
> >+ u32 pps_long_110_reserved;
> >+ /**
> >+ * @pps_long_114_reserved:
> >+ * PPS 114 - 117 - reserved
> >+ */
> >+ u32 pps_long_114_reserved;
> >+ /**
> >+ * @pps_long_118_reserved:
> >+ * PPS 118 - 121 - reserved
> >+ */
> >+ u32 pps_long_118_reserved;
> >+ /**
> >+ * @pps_long_122_reserved:
> >+ * PPS 122- 125 - reserved
> >+ */
> >+ u32 pps_long_122_reserved;
> >+ /**
> >+ * @pps_short_126_reserved:
> >+ * PPS 126, 127 - reserved
> >+ */
> >+ __be16 pps_short_126_reserved;
> >+};
> >+
> >+/**
> >+ * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture
> >+Parameter
> >+ * Set Metadata
> >+ *
> >+ * This structure represents the DSC PPS infoframe required to send the
> >+Picture
> >+ * Parameter Set metadata required before enabling VESA Display Stream
> >+ * Compression. This is based on the DP Secondary Data Packet structure
> >+and
> >+ * comprises of SDP Header as defined in drm_dp_helper.h and PPS payload.
> >+ *
> >+ * @pps_header:
> >+ *
> >+ * Header for PPS as per DP SDP header format
> >+ *
> >+ * @pps_payload:
> >+ *
> >+ * PPS payload fields as per DSC specification Table 4-1 */ struct
> >+drm_dsc_pps_infoframe {
> >+ struct dp_sdp_header pps_header;
> >+ struct picture_parameter_set pps_payload; } __packed;
> >+
> >+#endif /* _DRM_DSC_H_ */
> >--
> >2.7.4
>
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe
2018-07-31 21:07 ` [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-08-17 19:31 ` Srivatsa, Anusha
@ 2018-08-23 19:40 ` Harry Wentland
2018-08-23 20:12 ` Manasi Navare
1 sibling, 1 reply; 23+ messages in thread
From: Harry Wentland @ 2018-08-23 19:40 UTC (permalink / raw)
To: Manasi Navare, intel-gfx; +Cc: dri-devel
On 2018-07-31 05:07 PM, Manasi Navare wrote:
> This patch defines a new header file for all the DSC 1.2 structures
> and creates a structure for PPS infoframe which will be used to send
> picture parameter set secondary data packet for display stream compression.
> All the PPS infoframe syntax elements are taken from DSC 1.2 specification
> from VESA.
>
> Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Looks like this version basically removes the bitfield definitions and adds those
in the comments, compared to the review in May.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> include/drm/drm_dsc.h | 365 ++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 365 insertions(+)
> create mode 100644 include/drm/drm_dsc.h
>
> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> new file mode 100644
> index 0000000..678e8e6
> --- /dev/null
> +++ b/include/drm/drm_dsc.h
> @@ -0,0 +1,365 @@
> +/*
> + * Copyright (C) 2018 Intel Corp.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors:
> + * Manasi Navare <manasi.d.navare@intel.com>
> + */
> +
> +#ifndef DRM_DSC_H_
> +#define DRM_DSC_H_
> +
> +#include <drm/drm_dp_helper.h>
> +
> +/* VESA Display Stream Compression DSC 1.2 constants */
> +#define DSC_NUM_BUF_RANGES 15
> +
> +/**
> + * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
> + *
> + * The VESA DSC standard defines picture parameter set (PPS) which display
> + * stream compression encoders must communicate to decoders.
> + * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
> + * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
> + * The PPS fields that span over more than a byte should be stored in Big Endian
> + * format.
> + */
> +struct picture_parameter_set {
> + /**
> + * @dsc_version:
> + * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
> + * PPS0[7:4] - dsc_version_major: Contains major version of DSC
> + */
> + u8 dsc_version;
> + /**
> + * @pps_identifier:
> + * PPS1[7:0] - Application specific identifier that can be
> + * used to differentiate between different PPS tables.
> + */
> + u8 pps_identifier;
> + /**
> + * @pps_reserved:
> + * PPS2[7:0]- RESERVED Byte
> + */
> + u8 pps_reserved;
> + /**
> + * @pps_3:
> + * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
> + * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
> + * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
> + * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
> + * PPS3[7:4] - bits_per_component: Bits per component for the original
> + * pixels of the encoded picture.
> + * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
> + * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
> + * allowed only when dsc_minor_version = 0x2)
> + */
> + u8 pps_3;
> + /**
> + * @pps_4:
> + * PPS4[1:0] -These are the most significant 2 bits of
> + * compressed BPP bits_per_pixel[9:0] syntax element.
> + * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
> + * PPS4[3] - simple_422: Indicates if decoder drops samples to
> + * reconstruct the 4:2:2 picture.
> + * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
> + * active.
> + * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
> + * groups in picture
> + * PPS4[7:6] - Reseved bits
> + */
> + u8 pps_4;
> + /**
> + * @bits_per_pixel_low:
> + * PPS5[7:0] - This indicates the lower significant 8 bits of
> + * the compressed BPP bits_per_pixel[9:0] element.
> + */
> + u8 bits_per_pixel_low;
> + /**
> + * @pic_height:
> + * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
> + * within the raster.
> + */
> + __be16 pic_height;
> + /**
> + * @pic_width:
> + * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
> + * the raster.
> + */
> + __be16 pic_width;
> + /**
> + * @slice_height:
> + * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
> + */
> + __be16 slice_height;
> + /**
> + * @slice_width:
> + * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
> + */
> + __be16 slice_width;
> + /**
> + * @chunk_size:
> + * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
> + * that are used for slice multiplexing.
> + */
> + __be16 chunk_size;
> + /**
> + * @initial_xmit_delay_high:
> + * PPS16[1:0] - Most Significant two bits of initial transmission delay.
> + * It specifies the number of pixel times that the encoder waits before
> + * transmitting data from its rate buffer.
> + * PPS16[7:2] - Reserved
> + */
> + u8 initial_xmit_delay_high;
> + /**
> + * @initial_xmit_delay_low:
> + * PPS17[7:0] - Least significant 8 bits of initial transmission delay.
> + */
> + u8 initial_xmit_delay_low;
> + /**
> + * @initial_dec_delay:
> + *
> + * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
> + * of pixel times that the decoder accumulates data in its rate buffer
> + * before starting to decode and output pixels.
> + */
> + __be16 initial_dec_delay;
> + /**
> + * @pps20_reserved:
> + *
> + * PPS20[7:0] - Reserved
> + */
> + u8 pps20_reserved;
> + /**
> + * @initial_scale_value:
> + * PPS21[5:0] - Initial rcXformScale factor used at beginning
> + * of a slice.
> + * PPS21[7:6] - Reserved
> + */
> + u8 initial_scale_value;
> + /**
> + * @scale_increment_interval:
> + * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
> + * the rcXformScale factor at end of a slice.
> + */
> + __be16 scale_increment_interval;
> + /**
> + * @scale_decrement_interval_high:
> + * PPS24[3:0] - Higher 4 bits indicating number of group times between
> + * decrementing the rcXformScale factor at beginning of a slice.
> + * PPS24[7:4] - Reserved
> + */
> + u8 scale_decrement_interval_high;
> + /**
> + * @scale_decrement_interval_low:
> + * PPS25[7:0] - Lower 8 bits of scale decrement interval
> + */
> + u8 scale_decrement_interval_low;
> + /**
> + * @pps26_reserved:
> + * PPS26[7:0]
> + */
> + u8 pps26_reserved;
> + /**
> + * @first_line_bpg_offset:
> + * PPS27[4:0] - Number of additional bits that are allocated
> + * for each group on first line of a slice.
> + * PPS27[7:5] - Reserved
> + */
> + u8 first_line_bpg_offset;
> + /**
> + * @nfl_bpg_offset:
> + * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
> + * deallocated for each group for groups after the first line of slice.
> + */
> + __be16 nfl_bpg_offset;
> + /**
> + * @slice_bpg_offset:
> + * PPS30, PPS31[7:0] - Number of bits that are deallocated for each
> + * group to enforce the slice constraint.
> + */
> + __be16 slice_bpg_offset;
> + /**
> + * @initial_offset:
> + * PPS32,33[7:0] - Initial value for rcXformOffset
> + */
> + __be16 initial_offset;
> + /**
> + * @final_offset:
> + * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
> + */
> + __be16 final_offset;
> + /**
> + * @flatness_min_qp:
> + * PPS36[4:0] - Minimum QP at which flatness is signaled and
> + * flatness QP adjustment is made.
> + * PPS36[7:5] - Reserved
> + */
> + u8 flatness_min_qp;
> + /**
> + * @flatness_max_qp:
> + * PPS37[4:0] - Max QP at which flatness is signalled and
> + * the flatness adjustment is made.
> + * PPS37[7:5] - Reserved
> + */
> + u8 flatness_max_qp;
> + /**
> + * @rc_model_size:
> + * PPS38,39[7:0] - Number of bits within RC Model.
> + */
> + __be16 rc_model_size;
> + /**
> + * @rc_edge_factor:
> + * PPS40[3:0] - Ratio of current activity vs, previous
> + * activity to determine presence of edge.
> + * PPS40[7:4] - Reserved
> + */
> + u8 rc_edge_factor;
> + /**
> + * @rc_quant_incr_limit0:
> + * PPS41[4:0] - QP threshold used in short term RC
> + * PPS41[7:5] - Reserved
> + */
> + u8 rc_quant_incr_limit0;
> + /**
> + * @rc_quant_incr_limit1:
> + * PPS42[4:0] - QP threshold used in short term RC
> + * PPS42[7:5] - Reserved
> + */
> + u8 rc_quant_incr_limit1;
> + /**
> + * @rc_tgt_offset:
> + * PPS43[3:0] - Lower end of the variability range around the target
> + * bits per group that is allowed by short term RC.
> + * PPS43[7:4]- Upper end of the variability range around the target
> + * bits per group that i allowed by short term rc.
> + */
> + u8 rc_tgt_offset;
> + /**
> + * @rc_buf_thresh:
> + * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
> + * the 15 ranges defined by 14 thresholds.
> + */
> + u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
> + /**
> + * @rc_range_parameters:
> + * PPS58[7:0] - PPS87[7:0]
> + * Parameters that correspond to each of the 15 ranges.
> + */
> + __be16 rc_range_parameters[DSC_NUM_BUF_RANGES];
> + /**
> + * @native_422_420:
> + * PPS88[0] - 0 = Native 4:2:2 not used
> + * 1 = Native 4:2:2 used
> + * PPS88[1] - 0 = Native 4:2:0 not use
> + * 1 = Native 4:2:0 used
> + * PPS88[7:2] - Reserved 6 bits
> + */
> + u8 native_422_420;
> + /**
> + * @second_line_bpg_offset:
> + * PPS89[4:0] - Additional bits/group budget for the
> + * second line of a slice in Native 4:2:0 mode.
> + * Set to 0 if DSC minor version is 1 or native420 is 0.
> + * PPS89[7:5] - Reserved
> + */
> + u8 second_line_bpg_offset;
> + /**
> + * @nsl_bpg_offset:
> + * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
> + * for each group that is not in the second line of a slice.
> + */
> + __be16 nsl_bpg_offset;
> + /**
> + * @second_line_offset_adj:
> + * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
> + * line in Native 4:2:0 mode.
> + */
> + __be16 second_line_offset_adj;
> + /**
> + * @pps_long_94_reserved:
> + * PPS 94, 95, 96, 97 - Reserved
> + */
> + u32 pps_long_94_reserved;
> + /**
> + * @pps_long_98_reserved:
> + * PPS 98, 99, 100, 101 - Reserved
> + */
> + u32 pps_long_98_reserved;
> + /**
> + * @pps_long_102_reserved:
> + * PPS 102, 103, 104, 105 - Reserved
> + */
> + u32 pps_long_102_reserved;
> + /**
> + * @pps_long_106_reserved:
> + * PPS 106, 107, 108, 109 - reserved
> + */
> + u32 pps_long_106_reserved;
> + /**
> + * @pps_long_110_reserved:
> + * PPS 110, 111, 112, 113 - reserved
> + */
> + u32 pps_long_110_reserved;
> + /**
> + * @pps_long_114_reserved:
> + * PPS 114 - 117 - reserved
> + */
> + u32 pps_long_114_reserved;
> + /**
> + * @pps_long_118_reserved:
> + * PPS 118 - 121 - reserved
> + */
> + u32 pps_long_118_reserved;
> + /**
> + * @pps_long_122_reserved:
> + * PPS 122- 125 - reserved
> + */
> + u32 pps_long_122_reserved;
> + /**
> + * @pps_short_126_reserved:
> + * PPS 126, 127 - reserved
> + */
> + __be16 pps_short_126_reserved;
> +};
> +
> +/**
> + * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter
> + * Set Metadata
> + *
> + * This structure represents the DSC PPS infoframe required to send the Picture
> + * Parameter Set metadata required before enabling VESA Display Stream
> + * Compression. This is based on the DP Secondary Data Packet structure and
> + * comprises of SDP Header as defined in drm_dp_helper.h and PPS payload.
> + *
> + * @pps_header:
> + *
> + * Header for PPS as per DP SDP header format
> + *
> + * @pps_payload:
> + *
> + * PPS payload fields as per DSC specification Table 4-1
> + */
> +struct drm_dsc_pps_infoframe {
> + struct dp_sdp_header pps_header;
> + struct picture_parameter_set pps_payload;
> +} __packed;
> +
> +#endif /* _DRM_DSC_H_ */
>
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^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe
2018-08-23 19:40 ` Harry Wentland
@ 2018-08-23 20:12 ` Manasi Navare
0 siblings, 0 replies; 23+ messages in thread
From: Manasi Navare @ 2018-08-23 20:12 UTC (permalink / raw)
To: Harry Wentland; +Cc: Anusha Srivatsa, intel-gfx, dri-devel, Gaurav K Singh
Thanks for the review.
And yes it just removes the bitfields in PPS since the packing of the
bitfields and memory allocations are heavily dependent on HW.
So we cant have them in DRM level.
I will make sure to add this in version history and also add
Suggested-by: jani.nikula@linux.intel.com
Manasi
On Thu, Aug 23, 2018 at 03:40:12PM -0400, Harry Wentland wrote:
> On 2018-07-31 05:07 PM, Manasi Navare wrote:
> > This patch defines a new header file for all the DSC 1.2 structures
> > and creates a structure for PPS infoframe which will be used to send
> > picture parameter set secondary data packet for display stream compression.
> > All the PPS infoframe syntax elements are taken from DSC 1.2 specification
> > from VESA.
> >
> > Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
> > Cc: dri-devel@lists.freedesktop.org
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Cc: Harry Wentland <harry.wentland@amd.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
>
> Looks like this version basically removes the bitfield definitions and adds those
> in the comments, compared to the review in May.
>
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
>
> Harry
>
> > ---
> > include/drm/drm_dsc.h | 365 ++++++++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 365 insertions(+)
> > create mode 100644 include/drm/drm_dsc.h
> >
> > diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> > new file mode 100644
> > index 0000000..678e8e6
> > --- /dev/null
> > +++ b/include/drm/drm_dsc.h
> > @@ -0,0 +1,365 @@
> > +/*
> > + * Copyright (C) 2018 Intel Corp.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors:
> > + * Manasi Navare <manasi.d.navare@intel.com>
> > + */
> > +
> > +#ifndef DRM_DSC_H_
> > +#define DRM_DSC_H_
> > +
> > +#include <drm/drm_dp_helper.h>
> > +
> > +/* VESA Display Stream Compression DSC 1.2 constants */
> > +#define DSC_NUM_BUF_RANGES 15
> > +
> > +/**
> > + * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
> > + *
> > + * The VESA DSC standard defines picture parameter set (PPS) which display
> > + * stream compression encoders must communicate to decoders.
> > + * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
> > + * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
> > + * The PPS fields that span over more than a byte should be stored in Big Endian
> > + * format.
> > + */
> > +struct picture_parameter_set {
> > + /**
> > + * @dsc_version:
> > + * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
> > + * PPS0[7:4] - dsc_version_major: Contains major version of DSC
> > + */
> > + u8 dsc_version;
> > + /**
> > + * @pps_identifier:
> > + * PPS1[7:0] - Application specific identifier that can be
> > + * used to differentiate between different PPS tables.
> > + */
> > + u8 pps_identifier;
> > + /**
> > + * @pps_reserved:
> > + * PPS2[7:0]- RESERVED Byte
> > + */
> > + u8 pps_reserved;
> > + /**
> > + * @pps_3:
> > + * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
> > + * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
> > + * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
> > + * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
> > + * PPS3[7:4] - bits_per_component: Bits per component for the original
> > + * pixels of the encoded picture.
> > + * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
> > + * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
> > + * allowed only when dsc_minor_version = 0x2)
> > + */
> > + u8 pps_3;
> > + /**
> > + * @pps_4:
> > + * PPS4[1:0] -These are the most significant 2 bits of
> > + * compressed BPP bits_per_pixel[9:0] syntax element.
> > + * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
> > + * PPS4[3] - simple_422: Indicates if decoder drops samples to
> > + * reconstruct the 4:2:2 picture.
> > + * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
> > + * active.
> > + * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
> > + * groups in picture
> > + * PPS4[7:6] - Reseved bits
> > + */
> > + u8 pps_4;
> > + /**
> > + * @bits_per_pixel_low:
> > + * PPS5[7:0] - This indicates the lower significant 8 bits of
> > + * the compressed BPP bits_per_pixel[9:0] element.
> > + */
> > + u8 bits_per_pixel_low;
> > + /**
> > + * @pic_height:
> > + * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
> > + * within the raster.
> > + */
> > + __be16 pic_height;
> > + /**
> > + * @pic_width:
> > + * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
> > + * the raster.
> > + */
> > + __be16 pic_width;
> > + /**
> > + * @slice_height:
> > + * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
> > + */
> > + __be16 slice_height;
> > + /**
> > + * @slice_width:
> > + * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
> > + */
> > + __be16 slice_width;
> > + /**
> > + * @chunk_size:
> > + * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
> > + * that are used for slice multiplexing.
> > + */
> > + __be16 chunk_size;
> > + /**
> > + * @initial_xmit_delay_high:
> > + * PPS16[1:0] - Most Significant two bits of initial transmission delay.
> > + * It specifies the number of pixel times that the encoder waits before
> > + * transmitting data from its rate buffer.
> > + * PPS16[7:2] - Reserved
> > + */
> > + u8 initial_xmit_delay_high;
> > + /**
> > + * @initial_xmit_delay_low:
> > + * PPS17[7:0] - Least significant 8 bits of initial transmission delay.
> > + */
> > + u8 initial_xmit_delay_low;
> > + /**
> > + * @initial_dec_delay:
> > + *
> > + * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
> > + * of pixel times that the decoder accumulates data in its rate buffer
> > + * before starting to decode and output pixels.
> > + */
> > + __be16 initial_dec_delay;
> > + /**
> > + * @pps20_reserved:
> > + *
> > + * PPS20[7:0] - Reserved
> > + */
> > + u8 pps20_reserved;
> > + /**
> > + * @initial_scale_value:
> > + * PPS21[5:0] - Initial rcXformScale factor used at beginning
> > + * of a slice.
> > + * PPS21[7:6] - Reserved
> > + */
> > + u8 initial_scale_value;
> > + /**
> > + * @scale_increment_interval:
> > + * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
> > + * the rcXformScale factor at end of a slice.
> > + */
> > + __be16 scale_increment_interval;
> > + /**
> > + * @scale_decrement_interval_high:
> > + * PPS24[3:0] - Higher 4 bits indicating number of group times between
> > + * decrementing the rcXformScale factor at beginning of a slice.
> > + * PPS24[7:4] - Reserved
> > + */
> > + u8 scale_decrement_interval_high;
> > + /**
> > + * @scale_decrement_interval_low:
> > + * PPS25[7:0] - Lower 8 bits of scale decrement interval
> > + */
> > + u8 scale_decrement_interval_low;
> > + /**
> > + * @pps26_reserved:
> > + * PPS26[7:0]
> > + */
> > + u8 pps26_reserved;
> > + /**
> > + * @first_line_bpg_offset:
> > + * PPS27[4:0] - Number of additional bits that are allocated
> > + * for each group on first line of a slice.
> > + * PPS27[7:5] - Reserved
> > + */
> > + u8 first_line_bpg_offset;
> > + /**
> > + * @nfl_bpg_offset:
> > + * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
> > + * deallocated for each group for groups after the first line of slice.
> > + */
> > + __be16 nfl_bpg_offset;
> > + /**
> > + * @slice_bpg_offset:
> > + * PPS30, PPS31[7:0] - Number of bits that are deallocated for each
> > + * group to enforce the slice constraint.
> > + */
> > + __be16 slice_bpg_offset;
> > + /**
> > + * @initial_offset:
> > + * PPS32,33[7:0] - Initial value for rcXformOffset
> > + */
> > + __be16 initial_offset;
> > + /**
> > + * @final_offset:
> > + * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
> > + */
> > + __be16 final_offset;
> > + /**
> > + * @flatness_min_qp:
> > + * PPS36[4:0] - Minimum QP at which flatness is signaled and
> > + * flatness QP adjustment is made.
> > + * PPS36[7:5] - Reserved
> > + */
> > + u8 flatness_min_qp;
> > + /**
> > + * @flatness_max_qp:
> > + * PPS37[4:0] - Max QP at which flatness is signalled and
> > + * the flatness adjustment is made.
> > + * PPS37[7:5] - Reserved
> > + */
> > + u8 flatness_max_qp;
> > + /**
> > + * @rc_model_size:
> > + * PPS38,39[7:0] - Number of bits within RC Model.
> > + */
> > + __be16 rc_model_size;
> > + /**
> > + * @rc_edge_factor:
> > + * PPS40[3:0] - Ratio of current activity vs, previous
> > + * activity to determine presence of edge.
> > + * PPS40[7:4] - Reserved
> > + */
> > + u8 rc_edge_factor;
> > + /**
> > + * @rc_quant_incr_limit0:
> > + * PPS41[4:0] - QP threshold used in short term RC
> > + * PPS41[7:5] - Reserved
> > + */
> > + u8 rc_quant_incr_limit0;
> > + /**
> > + * @rc_quant_incr_limit1:
> > + * PPS42[4:0] - QP threshold used in short term RC
> > + * PPS42[7:5] - Reserved
> > + */
> > + u8 rc_quant_incr_limit1;
> > + /**
> > + * @rc_tgt_offset:
> > + * PPS43[3:0] - Lower end of the variability range around the target
> > + * bits per group that is allowed by short term RC.
> > + * PPS43[7:4]- Upper end of the variability range around the target
> > + * bits per group that i allowed by short term rc.
> > + */
> > + u8 rc_tgt_offset;
> > + /**
> > + * @rc_buf_thresh:
> > + * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
> > + * the 15 ranges defined by 14 thresholds.
> > + */
> > + u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
> > + /**
> > + * @rc_range_parameters:
> > + * PPS58[7:0] - PPS87[7:0]
> > + * Parameters that correspond to each of the 15 ranges.
> > + */
> > + __be16 rc_range_parameters[DSC_NUM_BUF_RANGES];
> > + /**
> > + * @native_422_420:
> > + * PPS88[0] - 0 = Native 4:2:2 not used
> > + * 1 = Native 4:2:2 used
> > + * PPS88[1] - 0 = Native 4:2:0 not use
> > + * 1 = Native 4:2:0 used
> > + * PPS88[7:2] - Reserved 6 bits
> > + */
> > + u8 native_422_420;
> > + /**
> > + * @second_line_bpg_offset:
> > + * PPS89[4:0] - Additional bits/group budget for the
> > + * second line of a slice in Native 4:2:0 mode.
> > + * Set to 0 if DSC minor version is 1 or native420 is 0.
> > + * PPS89[7:5] - Reserved
> > + */
> > + u8 second_line_bpg_offset;
> > + /**
> > + * @nsl_bpg_offset:
> > + * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
> > + * for each group that is not in the second line of a slice.
> > + */
> > + __be16 nsl_bpg_offset;
> > + /**
> > + * @second_line_offset_adj:
> > + * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
> > + * line in Native 4:2:0 mode.
> > + */
> > + __be16 second_line_offset_adj;
> > + /**
> > + * @pps_long_94_reserved:
> > + * PPS 94, 95, 96, 97 - Reserved
> > + */
> > + u32 pps_long_94_reserved;
> > + /**
> > + * @pps_long_98_reserved:
> > + * PPS 98, 99, 100, 101 - Reserved
> > + */
> > + u32 pps_long_98_reserved;
> > + /**
> > + * @pps_long_102_reserved:
> > + * PPS 102, 103, 104, 105 - Reserved
> > + */
> > + u32 pps_long_102_reserved;
> > + /**
> > + * @pps_long_106_reserved:
> > + * PPS 106, 107, 108, 109 - reserved
> > + */
> > + u32 pps_long_106_reserved;
> > + /**
> > + * @pps_long_110_reserved:
> > + * PPS 110, 111, 112, 113 - reserved
> > + */
> > + u32 pps_long_110_reserved;
> > + /**
> > + * @pps_long_114_reserved:
> > + * PPS 114 - 117 - reserved
> > + */
> > + u32 pps_long_114_reserved;
> > + /**
> > + * @pps_long_118_reserved:
> > + * PPS 118 - 121 - reserved
> > + */
> > + u32 pps_long_118_reserved;
> > + /**
> > + * @pps_long_122_reserved:
> > + * PPS 122- 125 - reserved
> > + */
> > + u32 pps_long_122_reserved;
> > + /**
> > + * @pps_short_126_reserved:
> > + * PPS 126, 127 - reserved
> > + */
> > + __be16 pps_short_126_reserved;
> > +};
> > +
> > +/**
> > + * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter
> > + * Set Metadata
> > + *
> > + * This structure represents the DSC PPS infoframe required to send the Picture
> > + * Parameter Set metadata required before enabling VESA Display Stream
> > + * Compression. This is based on the DP Secondary Data Packet structure and
> > + * comprises of SDP Header as defined in drm_dp_helper.h and PPS payload.
> > + *
> > + * @pps_header:
> > + *
> > + * Header for PPS as per DP SDP header format
> > + *
> > + * @pps_payload:
> > + *
> > + * PPS payload fields as per DSC specification Table 4-1
> > + */
> > +struct drm_dsc_pps_infoframe {
> > + struct dp_sdp_header pps_header;
> > + struct picture_parameter_set pps_payload;
> > +} __packed;
> > +
> > +#endif /* _DRM_DSC_H_ */
> >
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities
2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare
` (3 preceding siblings ...)
2018-07-31 21:07 ` [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
@ 2018-07-31 21:07 ` Manasi Navare
2018-08-23 20:01 ` Harry Wentland
2018-07-31 21:07 ` [PATCH v2 09/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
` (2 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Harry Wentland
From: Gaurav K Singh <gaurav.k.singh@intel.com>
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Manasi)
v3 (From Manasi)
* Remove the duplicate define (Suggested By:Harry Wentland)
v2: Define this struct in DRM (From Manasi)
* Changed the data types to u8/u16 instead of unsigned longs (Manasi)
* Remove driver specific fields (Manasi)
* Move this struct definition to DRM (Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
include/drm/drm_dsc.h | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 110 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 678e8e6..eda323d 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -30,6 +30,116 @@
/* VESA Display Stream Compression DSC 1.2 constants */
#define DSC_NUM_BUF_RANGES 15
+#define DSC_MUX_WORD_SIZE_8_10_BPC 48
+#define DSC_MUX_WORD_SIZE_12_BPC 64
+
+/* Configuration for a single Rate Control model range */
+struct dsc_rc_range_parameters {
+ /* Min Quantization Parameters allowed for this range */
+ u8 range_min_qp;
+ /* Max Quantization Parameters allowed for this range */
+ u8 range_max_qp;
+ /* Bits/group offset to apply to target for this group */
+ u8 range_bpg_offset;
+};
+
+struct drm_dsc_config {
+ /* Bits / component for previous reconstructed line buffer */
+ u8 line_buf_depth;
+ /* Bits per component to code (must be 8, 10, or 12) */
+ u8 bits_per_component;
+ /*
+ * Flag indicating to do RGB - YCoCg conversion
+ * and back (should be 1 for RGB input)
+ */
+ bool convert_rgb;
+ u8 slice_count;
+ /* Slice Width */
+ u16 slice_width;
+ /* Slice Height */
+ u16 slice_height;
+ /*
+ * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+ * outside of DSC encode/decode algorithm)
+ */
+ bool enable422;
+ /* Picture Width */
+ u16 pic_width;
+ /* Picture Height */
+ u16 pic_height;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_high;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_low;
+ /* Bits/pixel target << 4 (ie., 4 fractional bits) */
+ u16 bits_per_pixel;
+ /*
+ * Factor to determine if an edge is present based
+ * on the bits produced
+ */
+ u8 rc_edge_factor;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit1;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit0;
+ /* Number of pixels to delay the initial transmission */
+ u16 initial_xmit_delay;
+ /* Number of pixels to delay the VLD on the decoder,not including SSM */
+ u16 initial_dec_delay;
+ /* Block prediction enable */
+ bool block_pred_enable;
+ /* Bits/group offset to use for first line of the slice */
+ u8 first_line_bpg_offset;
+ /* Value to use for RC model offset at slice start */
+ u16 initial_offset;
+ /* Thresholds defining each of the buffer ranges */
+ u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+ /* Parameters for each of the RC ranges */
+ struct dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+ /* Total size of RC model */
+ u16 rc_model_size;
+ /* Minimum QP where flatness information is sent */
+ u8 flatness_min_qp;
+ /* Maximum QP where flatness information is sent */
+ u8 flatness_max_qp;
+ /* Initial value for scale factor */
+ u8 initial_scale_value;
+ /* Decrement scale factor every scale_decrement_interval groups */
+ u16 scale_decrement_interval;
+ /* Increment scale factor every scale_increment_interval groups */
+ u16 scale_increment_interval;
+ /* Non-first line BPG offset to use */
+ u16 nfl_bpg_offset;
+ /* BPG offset used to enforce slice bit */
+ u16 slice_bpg_offset;
+ /* Final RC linear transformation offset value */
+ u16 final_offset;
+ /* Enable on-off VBR (ie., disable stuffing bits) */
+ bool vbr_enable;
+ /* Mux word size (in bits) for SSM mode */
+ u8 mux_word_size;
+ /*
+ * The (max) size in bytes of the "chunks" that are
+ * used in slice multiplexing
+ */
+ u16 slice_chunk_size;
+ /* Rate Control buffer siz in bits */
+ u16 rc_bits;
+ /* DSC Minor Version */
+ u8 dsc_version_minor;
+ /* DSC Major version */
+ u8 dsc_version_major;
+ /* Native 4:2:2 support */
+ bool native_422;
+ /* Native 4:2:0 support */
+ bool native_420;
+ /* Additional bits/grp for seconnd line of slice for native 4:2:0 */
+ u8 second_line_bpg_offset;
+ /* Num of bits deallocated for each grp that is not in second line of slice */
+ u16 nsl_bpg_offset;
+ /* Offset adj fr second line in Native 4:2:0 mode */
+ u16 second_line_offset_adj;
+};
/**
* struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
--
2.7.4
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities
2018-07-31 21:07 ` [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
@ 2018-08-23 20:01 ` Harry Wentland
2018-08-28 21:12 ` Srivatsa, Anusha
0 siblings, 1 reply; 23+ messages in thread
From: Harry Wentland @ 2018-08-23 20:01 UTC (permalink / raw)
To: Manasi Navare, intel-gfx; +Cc: Anusha Srivatsa, Gaurav K Singh, dri-devel
On 2018-07-31 05:07 PM, Manasi Navare wrote:
> From: Gaurav K Singh <gaurav.k.singh@intel.com>
>
> This defines all the DSC parameters as per the VESA DSC spec
> that will be required for DSC encoder/decoder
>
> v4 (From Manasi)
> * Add the DSC_MUX_WORD_SIZE constants (Manasi)
>
> v3 (From Manasi)
> * Remove the duplicate define (Suggested By:Harry Wentland)
>
> v2: Define this struct in DRM (From Manasi)
> * Changed the data types to u8/u16 instead of unsigned longs (Manasi)
> * Remove driver specific fields (Manasi)
> * Move this struct definition to DRM (Manasi)
> * Define DSC 1.2 parameters (Manasi)
> * Use DSC_NUM_BUF_RANGES (Manasi)
> * Call it drm_dsc_config (Manasi)
>
> Cc: dri-devel@lists.freedesktop.org
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> include/drm/drm_dsc.h | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 110 insertions(+)
>
> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> index 678e8e6..eda323d 100644
> --- a/include/drm/drm_dsc.h
> +++ b/include/drm/drm_dsc.h
> @@ -30,6 +30,116 @@
>
> /* VESA Display Stream Compression DSC 1.2 constants */
> #define DSC_NUM_BUF_RANGES 15
> +#define DSC_MUX_WORD_SIZE_8_10_BPC 48
> +#define DSC_MUX_WORD_SIZE_12_BPC 64
> +
> +/* Configuration for a single Rate Control model range */
> +struct dsc_rc_range_parameters {
> + /* Min Quantization Parameters allowed for this range */
> + u8 range_min_qp;
> + /* Max Quantization Parameters allowed for this range */
> + u8 range_max_qp;
> + /* Bits/group offset to apply to target for this group */
> + u8 range_bpg_offset;
> +};
> +
> +struct drm_dsc_config {
> + /* Bits / component for previous reconstructed line buffer */
> + u8 line_buf_depth;
> + /* Bits per component to code (must be 8, 10, or 12) */
> + u8 bits_per_component;
> + /*
> + * Flag indicating to do RGB - YCoCg conversion
> + * and back (should be 1 for RGB input)
> + */
> + bool convert_rgb;
> + u8 slice_count;
> + /* Slice Width */
> + u16 slice_width;
> + /* Slice Height */
> + u16 slice_height;
> + /*
> + * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
> + * outside of DSC encode/decode algorithm)
> + */
> + bool enable422;
> + /* Picture Width */
> + u16 pic_width;
> + /* Picture Height */
> + u16 pic_height;
> + /* Offset to bits/group used by RC to determine QP adjustment */
> + u8 rc_tgt_offset_high;
> + /* Offset to bits/group used by RC to determine QP adjustment */
> + u8 rc_tgt_offset_low;
> + /* Bits/pixel target << 4 (ie., 4 fractional bits) */
> + u16 bits_per_pixel;
> + /*
> + * Factor to determine if an edge is present based
> + * on the bits produced
> + */
> + u8 rc_edge_factor;
> + /* Slow down incrementing once the range reaches this value */
> + u8 rc_quant_incr_limit1;
> + /* Slow down incrementing once the range reaches this value */
> + u8 rc_quant_incr_limit0;
> + /* Number of pixels to delay the initial transmission */
> + u16 initial_xmit_delay;
> + /* Number of pixels to delay the VLD on the decoder,not including SSM */
> + u16 initial_dec_delay;
> + /* Block prediction enable */
> + bool block_pred_enable;
> + /* Bits/group offset to use for first line of the slice */
> + u8 first_line_bpg_offset;
> + /* Value to use for RC model offset at slice start */
> + u16 initial_offset;
> + /* Thresholds defining each of the buffer ranges */
> + u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
> + /* Parameters for each of the RC ranges */
> + struct dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> + /* Total size of RC model */
> + u16 rc_model_size;
> + /* Minimum QP where flatness information is sent */
> + u8 flatness_min_qp;
> + /* Maximum QP where flatness information is sent */
> + u8 flatness_max_qp;
> + /* Initial value for scale factor */
> + u8 initial_scale_value;
> + /* Decrement scale factor every scale_decrement_interval groups */
> + u16 scale_decrement_interval;
> + /* Increment scale factor every scale_increment_interval groups */
> + u16 scale_increment_interval;
> + /* Non-first line BPG offset to use */
> + u16 nfl_bpg_offset;
> + /* BPG offset used to enforce slice bit */
> + u16 slice_bpg_offset;
> + /* Final RC linear transformation offset value */
> + u16 final_offset;
> + /* Enable on-off VBR (ie., disable stuffing bits) */
> + bool vbr_enable;
> + /* Mux word size (in bits) for SSM mode */
> + u8 mux_word_size;
> + /*
> + * The (max) size in bytes of the "chunks" that are
> + * used in slice multiplexing
> + */
> + u16 slice_chunk_size;
> + /* Rate Control buffer siz in bits */
> + u16 rc_bits;
> + /* DSC Minor Version */
> + u8 dsc_version_minor;
> + /* DSC Major version */
> + u8 dsc_version_major;
> + /* Native 4:2:2 support */
> + bool native_422;
> + /* Native 4:2:0 support */
> + bool native_420;
> + /* Additional bits/grp for seconnd line of slice for native 4:2:0 */
> + u8 second_line_bpg_offset;
> + /* Num of bits deallocated for each grp that is not in second line of slice */
> + u16 nsl_bpg_offset;
> + /* Offset adj fr second line in Native 4:2:0 mode */
> + u16 second_line_offset_adj;
> +};
>
> /**
> * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities
2018-08-23 20:01 ` Harry Wentland
@ 2018-08-28 21:12 ` Srivatsa, Anusha
0 siblings, 0 replies; 23+ messages in thread
From: Srivatsa, Anusha @ 2018-08-28 21:12 UTC (permalink / raw)
To: Harry Wentland, Navare, Manasi D, intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
>-----Original Message-----
>From: Harry Wentland [mailto:harry.wentland@amd.com]
>Sent: Thursday, August 23, 2018 1:01 PM
>To: Navare, Manasi D <manasi.d.navare@intel.com>; intel-
>gfx@lists.freedesktop.org
>Cc: Singh, Gaurav K <gaurav.k.singh@intel.com>; dri-
>devel@lists.freedesktop.org; Jani Nikula <jani.nikula@linux.intel.com>; Ville
>Syrjala <ville.syrjala@linux.intel.com>; Srivatsa, Anusha
><anusha.srivatsa@intel.com>
>Subject: Re: [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression
>Capabilities
>
>On 2018-07-31 05:07 PM, Manasi Navare wrote:
>> From: Gaurav K Singh <gaurav.k.singh@intel.com>
>>
>> This defines all the DSC parameters as per the VESA DSC spec that will
>> be required for DSC encoder/decoder
>>
>> v4 (From Manasi)
>> * Add the DSC_MUX_WORD_SIZE constants (Manasi)
>>
>> v3 (From Manasi)
>> * Remove the duplicate define (Suggested By:Harry Wentland)
>>
>> v2: Define this struct in DRM (From Manasi)
>> * Changed the data types to u8/u16 instead of unsigned longs (Manasi)
>> * Remove driver specific fields (Manasi)
>> * Move this struct definition to DRM (Manasi)
>> * Define DSC 1.2 parameters (Manasi)
>> * Use DSC_NUM_BUF_RANGES (Manasi)
>> * Call it drm_dsc_config (Manasi)
>>
>> Cc: dri-devel@lists.freedesktop.org
>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Cc: Harry Wentland <harry.wentland@amd.com>
>> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>
>Acked-by: Harry Wentland <harry.wentland@amd.com>
>
>Harry
Double checked with the Spec, looks good.
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> ---
>> include/drm/drm_dsc.h | 110
>> ++++++++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 110 insertions(+)
>>
>> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index
>> 678e8e6..eda323d 100644
>> --- a/include/drm/drm_dsc.h
>> +++ b/include/drm/drm_dsc.h
>> @@ -30,6 +30,116 @@
>>
>> /* VESA Display Stream Compression DSC 1.2 constants */
>> #define DSC_NUM_BUF_RANGES 15
>> +#define DSC_MUX_WORD_SIZE_8_10_BPC 48
>> +#define DSC_MUX_WORD_SIZE_12_BPC 64
>> +
>> +/* Configuration for a single Rate Control model range */ struct
>> +dsc_rc_range_parameters {
>> + /* Min Quantization Parameters allowed for this range */
>> + u8 range_min_qp;
>> + /* Max Quantization Parameters allowed for this range */
>> + u8 range_max_qp;
>> + /* Bits/group offset to apply to target for this group */
>> + u8 range_bpg_offset;
>> +};
>> +
>> +struct drm_dsc_config {
>> + /* Bits / component for previous reconstructed line buffer */
>> + u8 line_buf_depth;
>> + /* Bits per component to code (must be 8, 10, or 12) */
>> + u8 bits_per_component;
>> + /*
>> + * Flag indicating to do RGB - YCoCg conversion
>> + * and back (should be 1 for RGB input)
>> + */
>> + bool convert_rgb;
>> + u8 slice_count;
>> + /* Slice Width */
>> + u16 slice_width;
>> + /* Slice Height */
>> + u16 slice_height;
>> + /*
>> + * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
>> + * outside of DSC encode/decode algorithm)
>> + */
>> + bool enable422;
>> + /* Picture Width */
>> + u16 pic_width;
>> + /* Picture Height */
>> + u16 pic_height;
>> + /* Offset to bits/group used by RC to determine QP adjustment */
>> + u8 rc_tgt_offset_high;
>> + /* Offset to bits/group used by RC to determine QP adjustment */
>> + u8 rc_tgt_offset_low;
>> + /* Bits/pixel target << 4 (ie., 4 fractional bits) */
>> + u16 bits_per_pixel;
>> + /*
>> + * Factor to determine if an edge is present based
>> + * on the bits produced
>> + */
>> + u8 rc_edge_factor;
>> + /* Slow down incrementing once the range reaches this value */
>> + u8 rc_quant_incr_limit1;
>> + /* Slow down incrementing once the range reaches this value */
>> + u8 rc_quant_incr_limit0;
>> + /* Number of pixels to delay the initial transmission */
>> + u16 initial_xmit_delay;
>> + /* Number of pixels to delay the VLD on the decoder,not including SSM
>*/
>> + u16 initial_dec_delay;
>> + /* Block prediction enable */
>> + bool block_pred_enable;
>> + /* Bits/group offset to use for first line of the slice */
>> + u8 first_line_bpg_offset;
>> + /* Value to use for RC model offset at slice start */
>> + u16 initial_offset;
>> + /* Thresholds defining each of the buffer ranges */
>> + u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
>> + /* Parameters for each of the RC ranges */
>> + struct dsc_rc_range_parameters
>rc_range_params[DSC_NUM_BUF_RANGES];
>> + /* Total size of RC model */
>> + u16 rc_model_size;
>> + /* Minimum QP where flatness information is sent */
>> + u8 flatness_min_qp;
>> + /* Maximum QP where flatness information is sent */
>> + u8 flatness_max_qp;
>> + /* Initial value for scale factor */
>> + u8 initial_scale_value;
>> + /* Decrement scale factor every scale_decrement_interval groups */
>> + u16 scale_decrement_interval;
>> + /* Increment scale factor every scale_increment_interval groups */
>> + u16 scale_increment_interval;
>> + /* Non-first line BPG offset to use */
>> + u16 nfl_bpg_offset;
>> + /* BPG offset used to enforce slice bit */
>> + u16 slice_bpg_offset;
>> + /* Final RC linear transformation offset value */
>> + u16 final_offset;
>> + /* Enable on-off VBR (ie., disable stuffing bits) */
>> + bool vbr_enable;
>> + /* Mux word size (in bits) for SSM mode */
>> + u8 mux_word_size;
>> + /*
>> + * The (max) size in bytes of the "chunks" that are
>> + * used in slice multiplexing
>> + */
>> + u16 slice_chunk_size;
>> + /* Rate Control buffer siz in bits */
>> + u16 rc_bits;
>> + /* DSC Minor Version */
>> + u8 dsc_version_minor;
>> + /* DSC Major version */
>> + u8 dsc_version_major;
>> + /* Native 4:2:2 support */
>> + bool native_422;
>> + /* Native 4:2:0 support */
>> + bool native_420;
>> + /* Additional bits/grp for seconnd line of slice for native 4:2:0 */
>> + u8 second_line_bpg_offset;
>> + /* Num of bits deallocated for each grp that is not in second line of slice
>*/
>> + u16 nsl_bpg_offset;
>> + /* Offset adj fr second line in Native 4:2:0 mode */
>> + u16 second_line_offset_adj;
>> +};
>>
>> /**
>> * struct picture_parameter_set - Represents 128 bytes of Picture
>> Parameter Set
>>
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 09/23] drm/dsc: Define Rate Control values that do not change over configurations
2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare
` (4 preceding siblings ...)
2018-07-31 21:07 ` [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
@ 2018-07-31 21:07 ` Manasi Navare
2018-09-10 19:41 ` Manasi Navare
2018-07-31 21:07 ` [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-07-31 21:07 ` [PATCH v2 14/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
7 siblings, 1 reply; 23+ messages in thread
From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Srivatsa, Anusha, Manasi Navare, dri-devel, Gaurav K Singh
From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-devel@lists.freedesktop.org
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
include/drm/drm_dsc.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index eda323d..ebd99d7 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -33,6 +33,12 @@
#define DSC_MUX_WORD_SIZE_8_10_BPC 48
#define DSC_MUX_WORD_SIZE_12_BPC 64
+/* DSC Rate Control Constants */
+#define DSC_RC_MODEL_SIZE_CONST 8192
+#define DSC_RC_EDGE_FACTOR_CONST 6
+#define DSC_RC_TGT_OFFSET_HI_CONST 3
+#define DSC_RC_TGT_OFFSET_LO_CONST 3
+
/* Configuration for a single Rate Control model range */
struct dsc_rc_range_parameters {
/* Min Quantization Parameters allowed for this range */
--
2.7.4
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^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 09/23] drm/dsc: Define Rate Control values that do not change over configurations
2018-07-31 21:07 ` [PATCH v2 09/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
@ 2018-09-10 19:41 ` Manasi Navare
0 siblings, 0 replies; 23+ messages in thread
From: Manasi Navare @ 2018-09-10 19:41 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Harry Wentland
On Tue, Jul 31, 2018 at 02:07:05PM -0700, Manasi Navare wrote:
> From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
>
> DSC has some Rate Control values that remain constant
> across all configurations. These are as per the DSC
> standard.
>
> v3:
> * Define them in drm_dsc.h as they are
> DSC constants (Manasi)
> v2:
> * Add DP_DSC_ prefix (Jani Nikula)
>
> Cc: dri-devel@lists.freedesktop.org
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Tested and double checked the values with DSC spec so
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> include/drm/drm_dsc.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> index eda323d..ebd99d7 100644
> --- a/include/drm/drm_dsc.h
> +++ b/include/drm/drm_dsc.h
> @@ -33,6 +33,12 @@
> #define DSC_MUX_WORD_SIZE_8_10_BPC 48
> #define DSC_MUX_WORD_SIZE_12_BPC 64
>
> +/* DSC Rate Control Constants */
> +#define DSC_RC_MODEL_SIZE_CONST 8192
> +#define DSC_RC_EDGE_FACTOR_CONST 6
> +#define DSC_RC_TGT_OFFSET_HI_CONST 3
> +#define DSC_RC_TGT_OFFSET_LO_CONST 3
> +
> /* Configuration for a single Rate Control model range */
> struct dsc_rc_range_parameters {
> /* Min Quantization Parameters allowed for this range */
> --
> 2.7.4
>
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes
2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare
` (5 preceding siblings ...)
2018-07-31 21:07 ` [PATCH v2 09/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
@ 2018-07-31 21:07 ` Manasi Navare
2018-07-31 21:16 ` Chris Wilson
2018-08-23 19:58 ` Harry Wentland
2018-07-31 21:07 ` [PATCH v2 14/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
7 siblings, 2 replies; 23+ messages in thread
From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Anusha Srivatsa, Manasi Navare, dri-devel
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload according to the DSC 1.2 specification.
v5:
Do not use bitfields for DRM structs (Jani N)
v4:
* Use DSC constants for params that dont change across
configurations
v3:
* Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst
(Daniel Vetter)
v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
Documentation/gpu/drm-kms-helpers.rst | 12 ++
drivers/gpu/drm/Makefile | 2 +-
drivers/gpu/drm/drm_dsc.c | 221 ++++++++++++++++++++++++++++++++++
include/drm/drm_dsc.h | 22 ++++
4 files changed, 256 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/drm_dsc.c
diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst
index f9cfcdc..50bb717 100644
--- a/Documentation/gpu/drm-kms-helpers.rst
+++ b/Documentation/gpu/drm-kms-helpers.rst
@@ -223,6 +223,18 @@ MIPI DSI Helper Functions Reference
.. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
:export:
+Display Stream Compression Helper Functions Reference
+=====================================================
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :doc: dsc helpers
+
+.. kernel-doc:: include/drm/drm_dsc.h
+ :internal:
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :export:
+
Output Probing Helper Functions Reference
=========================================
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index a6771ce..961e511 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -31,7 +31,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
+drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o drm_probe_helper.o \
drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
drm_simple_kms_helper.o drm_modeset_helper.o \
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
new file mode 100644
index 0000000..99a8794
--- /dev/null
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -0,0 +1,221 @@
+/*
+ *Copyright © 2018 Intel Corp
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ *
+ * Author:
+ * Manasi Navare <manasi.d.navare@intel.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_dsc.h>
+
+/**
+ * DOC: dsc helpers
+ *
+ * These functions contain some common logic and helpers to deal with VESA
+ * Display Stream Compression standard required for DSC on Display Port/eDP or
+ * MIPI display interfaces.
+ */
+
+/**
+ * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
+ * for DisplayPort as per the DP 1.4 spec.
+ * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
+ */
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
+{
+ memset(&pps_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
+
+ pps_sdp->pps_header.HB1 = DP_SDP_PPS;
+ pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
+}
+EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
+
+/**
+ * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
+ * using the DSC configuration parameters in the order expected
+ * by the DSC Display Sink device. For the DSC, the sink device
+ * expects the PPS payload in the big endian format for the fields
+ * that span more than 1 byte.
+ *
+ * @pps_sdp:
+ * Secondary data packet for DSC Picture Parameter Set
+ * @dsc_cfg:
+ * DSC Configuration data filled by driver
+ */
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+ struct drm_dsc_config *dsc_cfg)
+{
+ u8 i = 0;
+
+ memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
+
+ /* PPS 0 */
+ pps_sdp->pps_payload.dsc_version = dsc_cfg->dsc_version_minor |
+ dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
+
+ /* PPS 1, 2 is 0 */
+
+ /* PPS 3 */
+ pps_sdp->pps_payload.pps_3 = dsc_cfg->line_buf_depth |
+ dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
+
+ /* PPS 4 */
+ pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel &
+ DSC_PPS_BPP_HIGH_MASK) >>
+ DSC_PPS_MSB_SHIFT) |
+ (u8)dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
+ (u8)dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
+ (u8)dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
+ (u8)dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
+
+ /* PPS 5 */
+ pps_sdp->pps_payload.bits_per_pixel_low = (u8)(dsc_cfg->bits_per_pixel &
+ DSC_PPS_LSB_MASK);
+
+ /*
+ * The DSC panel expects the PPS packet to have big endian format
+ * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
+ * to big endian format. If format is little endian, it will swap
+ * bytes to convert to Big endian else keep it unchanged.
+ */
+
+ /* PPS 6, 7 */
+ pps_sdp->pps_payload.pic_height = cpu_to_be16(dsc_cfg->pic_height);
+
+ /* PPS 8, 9 */
+ pps_sdp->pps_payload.pic_width = cpu_to_be16(dsc_cfg->pic_width);
+
+ /* PPS 10, 11 */
+ pps_sdp->pps_payload.slice_height = cpu_to_be16(dsc_cfg->slice_height);
+
+ /* PPS 12, 13 */
+ pps_sdp->pps_payload.slice_width = cpu_to_be16(dsc_cfg->slice_width);
+
+ /* PPS 14, 15 */
+ pps_sdp->pps_payload.chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
+
+ /* PPS 16 */
+ pps_sdp->pps_payload.initial_xmit_delay_high = (u8)((dsc_cfg->initial_xmit_delay &
+ DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
+ DSC_PPS_MSB_SHIFT);
+
+ /* PPS 17 */
+ pps_sdp->pps_payload.initial_xmit_delay_low = (u8)(dsc_cfg->initial_xmit_delay &
+ DSC_PPS_LSB_MASK);
+
+ /* PPS 18, 19 */
+ pps_sdp->pps_payload.initial_dec_delay = cpu_to_be16(dsc_cfg->initial_dec_delay);
+
+ /* PPS 20 is 0 */
+
+ /* PPS 21 */
+ pps_sdp->pps_payload.initial_scale_value = (u8)dsc_cfg->initial_scale_value;
+
+ /* PPS 22, 23 */
+ pps_sdp->pps_payload.scale_increment_interval = cpu_to_be16(dsc_cfg->scale_increment_interval);
+
+ /* PPS 24 */
+ pps_sdp->pps_payload.scale_decrement_interval_high = (u8)((dsc_cfg->scale_decrement_interval &
+ DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
+ DSC_PPS_MSB_SHIFT);
+
+ /* PPS 25 */
+ pps_sdp->pps_payload.scale_decrement_interval_low = (u8)(dsc_cfg->scale_decrement_interval &
+ DSC_PPS_LSB_MASK);
+
+ /* PPS 26[7:0], PPS 27[7:5] RESERVED */
+
+ /* PPS 27 */
+ pps_sdp->pps_payload.first_line_bpg_offset = (u8)dsc_cfg->first_line_bpg_offset;
+
+ /* PPS 28, 29 */
+ pps_sdp->pps_payload.nfl_bpg_offset = cpu_to_be16(dsc_cfg->nfl_bpg_offset);
+
+ /* PPS 30, 31 */
+ pps_sdp->pps_payload.slice_bpg_offset = cpu_to_be16(dsc_cfg->slice_bpg_offset);
+
+ /* PPS 32, 33 */
+ pps_sdp->pps_payload.initial_offset = cpu_to_be16(dsc_cfg->initial_offset);
+
+ /* PPS 34, 35 */
+ pps_sdp->pps_payload.final_offset = cpu_to_be16(dsc_cfg->final_offset);
+
+ /* PPS 36 */
+ pps_sdp->pps_payload.flatness_min_qp = (u8)dsc_cfg->flatness_min_qp;
+
+ /* PPS 37 */
+ pps_sdp->pps_payload.flatness_max_qp = (u8)dsc_cfg->flatness_max_qp;
+
+ /* PPS 38, 39 */
+ pps_sdp->pps_payload.rc_model_size = cpu_to_be16((u16)DSC_RC_MODEL_SIZE_CONST);
+
+ /* PPS 40 */
+ pps_sdp->pps_payload.rc_edge_factor = (u8)DSC_RC_EDGE_FACTOR_CONST;
+
+ /* PPS 41 */
+ pps_sdp->pps_payload.rc_quant_incr_limit0 = (u8)dsc_cfg->rc_quant_incr_limit0;
+
+ /* PPS 42 */
+ pps_sdp->pps_payload.rc_quant_incr_limit1 = (u8)dsc_cfg->rc_quant_incr_limit1;
+
+ /* PPS 43 */
+ pps_sdp->pps_payload.rc_tgt_offset = (u8)DSC_RC_TGT_OFFSET_LO_CONST |
+ (u8)DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
+
+ /* PPS 44 - 57 */
+ for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
+ pps_sdp->pps_payload.rc_buf_thresh[i] = dsc_cfg->rc_buf_thresh[i];
+
+ /* PPS 58 - 87 */
+ /*
+ * For DSC sink programming the RC Range parameter fields
+ * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
+ */
+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+ pps_sdp->pps_payload.rc_range_parameters[i] =
+ (u16)((dsc_cfg->rc_range_params[i].range_min_qp <<
+ DSC_PPS_RC_RANGE_MINQP_SHIFT) |
+ (dsc_cfg->rc_range_params[i].range_max_qp <<
+ DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
+ (dsc_cfg->rc_range_params[i].range_bpg_offset));
+ pps_sdp->pps_payload.rc_range_parameters[i] = cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]);
+ }
+
+ /* PPS 88 */
+ pps_sdp->pps_payload.native_422_420 = (u8)dsc_cfg->native_422 |
+ (u8)dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
+
+ /* PPS 89 */
+ pps_sdp->pps_payload.second_line_bpg_offset = (u8)dsc_cfg->second_line_bpg_offset;
+
+ /* PPS 90, 91 */
+ pps_sdp->pps_payload.nsl_bpg_offset = cpu_to_be16(dsc_cfg->nsl_bpg_offset);
+
+ /* PPS 92, 93 */
+ pps_sdp->pps_payload.second_line_offset_adj = cpu_to_be16(dsc_cfg->second_line_offset_adj);
+
+ /* PPS 94 - 127 are O */
+}
+EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index ebd99d7..30adc15 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -26,6 +26,7 @@
#ifndef DRM_DSC_H_
#define DRM_DSC_H_
+#include <linux/byteorder/generic.h>
#include <drm/drm_dp_helper.h>
/* VESA Display Stream Compression DSC 1.2 constants */
@@ -39,6 +40,23 @@
#define DSC_RC_TGT_OFFSET_HI_CONST 3
#define DSC_RC_TGT_OFFSET_LO_CONST 3
+/* DSC PPS constants and macros */
+#define DSC_PPS_VERSION_MAJOR_SHIFT 4
+#define DSC_PPS_BPC_SHIFT 4
+#define DSC_PPS_MSB_SHIFT 8
+#define DSC_PPS_LSB_MASK (0xFF << 0)
+#define DSC_PPS_BPP_HIGH_MASK (0x3 << 8)
+#define DSC_PPS_VBR_EN_SHIFT 2
+#define DSC_PPS_SIMPLE422_SHIFT 3
+#define DSC_PPS_CONVERT_RGB_SHIFT 4
+#define DSC_PPS_BLOCK_PRED_EN_SHIFT 5
+#define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK (0x3 << 8)
+#define DSC_PPS_SCALE_DEC_INT_HIGH_MASK (0xF << 8)
+#define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT 4
+#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
+#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
+#define DSC_PPS_NATIVE_420_SHIFT 1
+
/* Configuration for a single Rate Control model range */
struct dsc_rc_range_parameters {
/* Min Quantization Parameters allowed for this range */
@@ -478,4 +496,8 @@ struct drm_dsc_pps_infoframe {
struct picture_parameter_set pps_payload;
} __packed;
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp);
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+ struct drm_dsc_config *dsc_cfg);
+
#endif /* _DRM_DSC_H_ */
--
2.7.4
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^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes
2018-07-31 21:07 ` [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
@ 2018-07-31 21:16 ` Chris Wilson
2018-08-03 19:18 ` Manasi Navare
2018-08-23 19:58 ` Harry Wentland
1 sibling, 1 reply; 23+ messages in thread
From: Chris Wilson @ 2018-07-31 21:16 UTC (permalink / raw)
To: Manasi Navare, intel-gfx; +Cc: dri-devel
Quoting Manasi Navare (2018-07-31 22:07:06)
> + /* PPS 4 */
> + pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel &
> + DSC_PPS_BPP_HIGH_MASK) >>
> + DSC_PPS_MSB_SHIFT) |
To avoid overhanging cliffs, insert the newline after the sequence
point. Quite a few examples throughout the series that would benefit
from more judicial placement of line breaks.
> + (u8)dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
> + (u8)dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
> + (u8)dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
> + (u8)dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
Furthermore, you only need the SPDX shorthand rather than full licence
text.
-Chris
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes
2018-07-31 21:16 ` Chris Wilson
@ 2018-08-03 19:18 ` Manasi Navare
2018-08-03 19:43 ` Chris Wilson
0 siblings, 1 reply; 23+ messages in thread
From: Manasi Navare @ 2018-08-03 19:18 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, dri-devel
On Tue, Jul 31, 2018 at 10:16:45PM +0100, Chris Wilson wrote:
> Quoting Manasi Navare (2018-07-31 22:07:06)
> > + /* PPS 4 */
> > + pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel &
> > + DSC_PPS_BPP_HIGH_MASK) >>
> > + DSC_PPS_MSB_SHIFT) |
>
> To avoid overhanging cliffs, insert the newline after the sequence
> point. Quite a few examples throughout the series that would benefit
> from more judicial placement of line breaks.
What exactly are you refering to by sequence point here?
I am adding newline here after the operator if the next operand exceeds the 80 column limit.
>
> > + (u8)dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
> > + (u8)dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
> > + (u8)dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
> > + (u8)dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
>
> Furthermore, you only need the SPDX shorthand rather than full licence
> text.
Here the header is what all the other .c files in drm have. They all tend to use
complete text.
Are you suggesting just adding SPDX-License-Identifier: GPL-2.0+ at the begining of the file?
Should I remove the entire paragraph about the Copyright?
Manasi
> -Chris
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes
2018-08-03 19:18 ` Manasi Navare
@ 2018-08-03 19:43 ` Chris Wilson
2018-08-03 19:55 ` Manasi Navare
0 siblings, 1 reply; 23+ messages in thread
From: Chris Wilson @ 2018-08-03 19:43 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx, dri-devel
Quoting Manasi Navare (2018-08-03 20:18:42)
> On Tue, Jul 31, 2018 at 10:16:45PM +0100, Chris Wilson wrote:
> > Quoting Manasi Navare (2018-07-31 22:07:06)
> > > + /* PPS 4 */
> > > + pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel &
> > > + DSC_PPS_BPP_HIGH_MASK) >>
> > > + DSC_PPS_MSB_SHIFT) |
> >
> > To avoid overhanging cliffs, insert the newline after the sequence
> > point. Quite a few examples throughout the series that would benefit
> > from more judicial placement of line breaks.
>
> What exactly are you refering to by sequence point here?
Which ever makes sense visually, here '='.
pps_sdp->pps_payload.pps_4 =
dsc_cfg->bits_per_pixel >> X << DSC_PPS_MSB_SHIFT |
dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
If you want to mask with 0xff do it without having to refer to C type promotion
rules.
> > Furthermore, you only need the SPDX shorthand rather than full licence
> > text.
>
> Here the header is what all the other .c files in drm have. They all tend to use
> complete text.
And they all need updating, eventually. There's no reason for new file
to use the old style.
> Are you suggesting just adding SPDX-License-Identifier: GPL-2.0+ at the begining of the file?
> Should I remove the entire paragraph about the Copyright?
No, the code is MIT. You replace the licence with just a SPDX link.
-Chris
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes
2018-08-03 19:43 ` Chris Wilson
@ 2018-08-03 19:55 ` Manasi Navare
0 siblings, 0 replies; 23+ messages in thread
From: Manasi Navare @ 2018-08-03 19:55 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, dri-devel
On Fri, Aug 03, 2018 at 08:43:51PM +0100, Chris Wilson wrote:
> Quoting Manasi Navare (2018-08-03 20:18:42)
> > On Tue, Jul 31, 2018 at 10:16:45PM +0100, Chris Wilson wrote:
> > > Quoting Manasi Navare (2018-07-31 22:07:06)
> > > > + /* PPS 4 */
> > > > + pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel &
> > > > + DSC_PPS_BPP_HIGH_MASK) >>
> > > > + DSC_PPS_MSB_SHIFT) |
> > >
> > > To avoid overhanging cliffs, insert the newline after the sequence
> > > point. Quite a few examples throughout the series that would benefit
> > > from more judicial placement of line breaks.
> >
> > What exactly are you refering to by sequence point here?
>
> Which ever makes sense visually, here '='.
>
> pps_sdp->pps_payload.pps_4 =
> dsc_cfg->bits_per_pixel >> X << DSC_PPS_MSB_SHIFT |
> dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
> dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
> dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
> dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
Ok understood about the sequence point
>
> If you want to mask with 0xff do it without having to refer to C type promotion
> rules.
This point is still not clear. is this not correct:
(dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> DSC_PPS_MSB_SHIFT
>
> > > Furthermore, you only need the SPDX shorthand rather than full licence
> > > text.
> >
> > Here the header is what all the other .c files in drm have. They all tend to use
> > complete text.
>
> And they all need updating, eventually. There's no reason for new file
> to use the old style.
>
> > Are you suggesting just adding SPDX-License-Identifier: GPL-2.0+ at the begining of the file?
> > Should I remove the entire paragraph about the Copyright?
>
> No, the code is MIT. You replace the licence with just a SPDX link.
Could you give an example here for the correct way of adding SPDX info in the header and what part
of the existing header needs to stay?
That would be helpful.
Manasi
> -Chris
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes
2018-07-31 21:07 ` [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-07-31 21:16 ` Chris Wilson
@ 2018-08-23 19:58 ` Harry Wentland
1 sibling, 0 replies; 23+ messages in thread
From: Harry Wentland @ 2018-08-23 19:58 UTC (permalink / raw)
To: Manasi Navare, intel-gfx; +Cc: Anusha Srivatsa, dri-devel
On 2018-07-31 05:07 PM, Manasi Navare wrote:
> According to Display Stream compression spec 1.2, the picture
> parameter set metadata is sent from source to sink device
> using the DP Secondary data packet. An infoframe is formed
> for the PPS SDP header and PPS SDP payload bytes.
> This patch adds helpers to fill the PPS SDP header
> and PPS SDP payload according to the DSC 1.2 specification.
>
> v5:
> Do not use bitfields for DRM structs (Jani N)
> v4:
> * Use DSC constants for params that dont change across
> configurations
> v3:
> * Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst
> (Daniel Vetter)
>
> v2:
> * Add EXPORT_SYMBOL for the drm functions (Manasi)
>
> Cc: dri-devel@lists.freedesktop.org
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> Documentation/gpu/drm-kms-helpers.rst | 12 ++
> drivers/gpu/drm/Makefile | 2 +-
> drivers/gpu/drm/drm_dsc.c | 221 ++++++++++++++++++++++++++++++++++
> include/drm/drm_dsc.h | 22 ++++
> 4 files changed, 256 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/drm_dsc.c
>
> diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst
> index f9cfcdc..50bb717 100644
> --- a/Documentation/gpu/drm-kms-helpers.rst
> +++ b/Documentation/gpu/drm-kms-helpers.rst
> @@ -223,6 +223,18 @@ MIPI DSI Helper Functions Reference
> .. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
> :export:
>
> +Display Stream Compression Helper Functions Reference
> +=====================================================
> +
> +.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
> + :doc: dsc helpers
> +
> +.. kernel-doc:: include/drm/drm_dsc.h
> + :internal:
> +
> +.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
> + :export:
> +
> Output Probing Helper Functions Reference
> =========================================
>
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index a6771ce..961e511 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -31,7 +31,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
> drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
> drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
>
> -drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
> +drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o drm_probe_helper.o \
> drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
> drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
> drm_simple_kms_helper.o drm_modeset_helper.o \
> diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
> new file mode 100644
> index 0000000..99a8794
> --- /dev/null
> +++ b/drivers/gpu/drm/drm_dsc.c
> @@ -0,0 +1,221 @@
> +/*
> + *Copyright © 2018 Intel Corp
> + *
> + * Permission to use, copy, modify, distribute, and sell this software and its
> + * documentation for any purpose is hereby granted without fee, provided that
> + * the above copyright notice appear in all copies and that both that copyright
> + * notice and this permission notice appear in supporting documentation, and
> + * that the name of the copyright holders not be used in advertising or
> + * publicity pertaining to distribution of the software without specific,
> + * written prior permission. The copyright holders make no representations
> + * about the suitability of this software for any purpose. It is provided "as
> + * is" without express or implied warranty.
> + *
> + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
> + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
> + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
> + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
> + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
> + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
> + * OF THIS SOFTWARE.
> + *
> + * Author:
> + * Manasi Navare <manasi.d.navare@intel.com>
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/errno.h>
> +#include <drm/drm_dp_helper.h>
> +#include <drm/drm_dsc.h>
> +
> +/**
> + * DOC: dsc helpers
> + *
> + * These functions contain some common logic and helpers to deal with VESA
> + * Display Stream Compression standard required for DSC on Display Port/eDP or
> + * MIPI display interfaces.
> + */
> +
> +/**
> + * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
> + * for DisplayPort as per the DP 1.4 spec.
> + * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
> + */
> +void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
> +{
> + memset(&pps_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
> +
> + pps_sdp->pps_header.HB1 = DP_SDP_PPS;
> + pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
> +}
> +EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
> +
> +/**
> + * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
> + * using the DSC configuration parameters in the order expected
> + * by the DSC Display Sink device. For the DSC, the sink device
> + * expects the PPS payload in the big endian format for the fields
> + * that span more than 1 byte.
> + *
> + * @pps_sdp:
> + * Secondary data packet for DSC Picture Parameter Set
> + * @dsc_cfg:
> + * DSC Configuration data filled by driver
> + */
> +void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
> + struct drm_dsc_config *dsc_cfg)
> +{
> + u8 i = 0;
> +
> + memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
> +
> + /* PPS 0 */
> + pps_sdp->pps_payload.dsc_version = dsc_cfg->dsc_version_minor |
> + dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
> +
> + /* PPS 1, 2 is 0 */
> +
> + /* PPS 3 */
> + pps_sdp->pps_payload.pps_3 = dsc_cfg->line_buf_depth |
> + dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
> +
> + /* PPS 4 */
> + pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel &
> + DSC_PPS_BPP_HIGH_MASK) >>
> + DSC_PPS_MSB_SHIFT) |
> + (u8)dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
> + (u8)dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
> + (u8)dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
> + (u8)dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
> +
> + /* PPS 5 */
> + pps_sdp->pps_payload.bits_per_pixel_low = (u8)(dsc_cfg->bits_per_pixel &
> + DSC_PPS_LSB_MASK);
> +
> + /*
> + * The DSC panel expects the PPS packet to have big endian format
> + * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
> + * to big endian format. If format is little endian, it will swap
> + * bytes to convert to Big endian else keep it unchanged.
> + */
> +
> + /* PPS 6, 7 */
> + pps_sdp->pps_payload.pic_height = cpu_to_be16(dsc_cfg->pic_height);
> +
> + /* PPS 8, 9 */
> + pps_sdp->pps_payload.pic_width = cpu_to_be16(dsc_cfg->pic_width);
> +
> + /* PPS 10, 11 */
> + pps_sdp->pps_payload.slice_height = cpu_to_be16(dsc_cfg->slice_height);
> +
> + /* PPS 12, 13 */
> + pps_sdp->pps_payload.slice_width = cpu_to_be16(dsc_cfg->slice_width);
> +
> + /* PPS 14, 15 */
> + pps_sdp->pps_payload.chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
> +
> + /* PPS 16 */
> + pps_sdp->pps_payload.initial_xmit_delay_high = (u8)((dsc_cfg->initial_xmit_delay &
> + DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
> + DSC_PPS_MSB_SHIFT);
> +
> + /* PPS 17 */
> + pps_sdp->pps_payload.initial_xmit_delay_low = (u8)(dsc_cfg->initial_xmit_delay &
> + DSC_PPS_LSB_MASK);
> +
> + /* PPS 18, 19 */
> + pps_sdp->pps_payload.initial_dec_delay = cpu_to_be16(dsc_cfg->initial_dec_delay);
> +
> + /* PPS 20 is 0 */
> +
> + /* PPS 21 */
> + pps_sdp->pps_payload.initial_scale_value = (u8)dsc_cfg->initial_scale_value;
> +
> + /* PPS 22, 23 */
> + pps_sdp->pps_payload.scale_increment_interval = cpu_to_be16(dsc_cfg->scale_increment_interval);
> +
> + /* PPS 24 */
> + pps_sdp->pps_payload.scale_decrement_interval_high = (u8)((dsc_cfg->scale_decrement_interval &
> + DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
> + DSC_PPS_MSB_SHIFT);
> +
> + /* PPS 25 */
> + pps_sdp->pps_payload.scale_decrement_interval_low = (u8)(dsc_cfg->scale_decrement_interval &
> + DSC_PPS_LSB_MASK);
> +
> + /* PPS 26[7:0], PPS 27[7:5] RESERVED */
> +
> + /* PPS 27 */
> + pps_sdp->pps_payload.first_line_bpg_offset = (u8)dsc_cfg->first_line_bpg_offset;
> +
> + /* PPS 28, 29 */
> + pps_sdp->pps_payload.nfl_bpg_offset = cpu_to_be16(dsc_cfg->nfl_bpg_offset);
> +
> + /* PPS 30, 31 */
> + pps_sdp->pps_payload.slice_bpg_offset = cpu_to_be16(dsc_cfg->slice_bpg_offset);
> +
> + /* PPS 32, 33 */
> + pps_sdp->pps_payload.initial_offset = cpu_to_be16(dsc_cfg->initial_offset);
> +
> + /* PPS 34, 35 */
> + pps_sdp->pps_payload.final_offset = cpu_to_be16(dsc_cfg->final_offset);
> +
> + /* PPS 36 */
> + pps_sdp->pps_payload.flatness_min_qp = (u8)dsc_cfg->flatness_min_qp;
> +
> + /* PPS 37 */
> + pps_sdp->pps_payload.flatness_max_qp = (u8)dsc_cfg->flatness_max_qp;
> +
> + /* PPS 38, 39 */
> + pps_sdp->pps_payload.rc_model_size = cpu_to_be16((u16)DSC_RC_MODEL_SIZE_CONST);
> +
> + /* PPS 40 */
> + pps_sdp->pps_payload.rc_edge_factor = (u8)DSC_RC_EDGE_FACTOR_CONST;
> +
> + /* PPS 41 */
> + pps_sdp->pps_payload.rc_quant_incr_limit0 = (u8)dsc_cfg->rc_quant_incr_limit0;
> +
> + /* PPS 42 */
> + pps_sdp->pps_payload.rc_quant_incr_limit1 = (u8)dsc_cfg->rc_quant_incr_limit1;
> +
> + /* PPS 43 */
> + pps_sdp->pps_payload.rc_tgt_offset = (u8)DSC_RC_TGT_OFFSET_LO_CONST |
> + (u8)DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
> +
> + /* PPS 44 - 57 */
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
> + pps_sdp->pps_payload.rc_buf_thresh[i] = dsc_cfg->rc_buf_thresh[i];
> +
> + /* PPS 58 - 87 */
> + /*
> + * For DSC sink programming the RC Range parameter fields
> + * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
> + */
> + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> + pps_sdp->pps_payload.rc_range_parameters[i] =
> + (u16)((dsc_cfg->rc_range_params[i].range_min_qp <<
> + DSC_PPS_RC_RANGE_MINQP_SHIFT) |
> + (dsc_cfg->rc_range_params[i].range_max_qp <<
> + DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
> + (dsc_cfg->rc_range_params[i].range_bpg_offset));
> + pps_sdp->pps_payload.rc_range_parameters[i] = cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]);
> + }
> +
> + /* PPS 88 */
> + pps_sdp->pps_payload.native_422_420 = (u8)dsc_cfg->native_422 |
> + (u8)dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
> +
> + /* PPS 89 */
> + pps_sdp->pps_payload.second_line_bpg_offset = (u8)dsc_cfg->second_line_bpg_offset;
> +
> + /* PPS 90, 91 */
> + pps_sdp->pps_payload.nsl_bpg_offset = cpu_to_be16(dsc_cfg->nsl_bpg_offset);
> +
> + /* PPS 92, 93 */
> + pps_sdp->pps_payload.second_line_offset_adj = cpu_to_be16(dsc_cfg->second_line_offset_adj);
> +
> + /* PPS 94 - 127 are O */
> +}
> +EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> index ebd99d7..30adc15 100644
> --- a/include/drm/drm_dsc.h
> +++ b/include/drm/drm_dsc.h
> @@ -26,6 +26,7 @@
> #ifndef DRM_DSC_H_
> #define DRM_DSC_H_
>
> +#include <linux/byteorder/generic.h>
> #include <drm/drm_dp_helper.h>
>
> /* VESA Display Stream Compression DSC 1.2 constants */
> @@ -39,6 +40,23 @@
> #define DSC_RC_TGT_OFFSET_HI_CONST 3
> #define DSC_RC_TGT_OFFSET_LO_CONST 3
>
> +/* DSC PPS constants and macros */
> +#define DSC_PPS_VERSION_MAJOR_SHIFT 4
> +#define DSC_PPS_BPC_SHIFT 4
> +#define DSC_PPS_MSB_SHIFT 8
> +#define DSC_PPS_LSB_MASK (0xFF << 0)
> +#define DSC_PPS_BPP_HIGH_MASK (0x3 << 8)
> +#define DSC_PPS_VBR_EN_SHIFT 2
> +#define DSC_PPS_SIMPLE422_SHIFT 3
> +#define DSC_PPS_CONVERT_RGB_SHIFT 4
> +#define DSC_PPS_BLOCK_PRED_EN_SHIFT 5
> +#define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK (0x3 << 8)
> +#define DSC_PPS_SCALE_DEC_INT_HIGH_MASK (0xF << 8)
> +#define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT 4
> +#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
> +#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
> +#define DSC_PPS_NATIVE_420_SHIFT 1
> +
> /* Configuration for a single Rate Control model range */
> struct dsc_rc_range_parameters {
> /* Min Quantization Parameters allowed for this range */
> @@ -478,4 +496,8 @@ struct drm_dsc_pps_infoframe {
> struct picture_parameter_set pps_payload;
> } __packed;
>
> +void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp);
> +void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
> + struct drm_dsc_config *dsc_cfg);
> +
> #endif /* _DRM_DSC_H_ */
> -- 2.7.4
>
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 14/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare
` (6 preceding siblings ...)
2018-07-31 21:07 ` [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
@ 2018-07-31 21:07 ` Manasi Navare
7 siblings, 0 replies; 23+ messages in thread
From: Manasi Navare @ 2018-07-31 21:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Manasi Navare, Gaurav K Singh, dri-devel
From: Gaurav K Singh <gaurav.k.singh@intel.com>
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
include/drm/drm_dsc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 30adc15..4cfcd03 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -56,6 +56,9 @@
#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
#define DSC_PPS_NATIVE_420_SHIFT 1
+#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16
+#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0
+#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13
/* Configuration for a single Rate Control model range */
struct dsc_rc_range_parameters {
--
2.7.4
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