From: jacopo mondi <jacopo@jmondi.org>
To: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 04/16] drm: bridge: thc63: Restrict modes based on hardware operating frequency
Date: Tue, 11 Sep 2018 15:31:55 +0200 [thread overview]
Message-ID: <20180911133155.GV28160@w540> (raw)
In-Reply-To: <20180904121027.24031-5-laurent.pinchart+renesas@ideasonboard.com>
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Hi Laurent,
sorry, I might be confused but,
On Tue, Sep 04, 2018 at 03:10:15PM +0300, Laurent Pinchart wrote:
> The THC63LVD1024 is restricted to a pixel clock frequency in the range
> of 8 to 135 MHz. Implement the bridge .mode_valid() operation
> accordingly.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> drivers/gpu/drm/bridge/thc63lvd1024.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/bridge/thc63lvd1024.c b/drivers/gpu/drm/bridge/thc63lvd1024.c
> index c8b9edd5a7f4..63609ba16b6d 100644
> --- a/drivers/gpu/drm/bridge/thc63lvd1024.c
> +++ b/drivers/gpu/drm/bridge/thc63lvd1024.c
> @@ -45,6 +45,23 @@ static int thc63_attach(struct drm_bridge *bridge)
> return drm_bridge_attach(bridge->encoder, thc63->next, bridge);
> }
>
> +static enum drm_mode_status thc63_mode_valid(struct drm_bridge *bridge,
> + const struct drm_display_mode *mode)
> +{
> + /*
> + * The THC63LVD0124 clock frequency range is 8 to 135 MHz in single-in,
> + * single-out mode. Note that the limits depends on the mode and will
> + * need to be adjusted accordingly.
> + */
> + if (mode->clock < 8000)
> + return MODE_CLOCK_LOW;
> +
> + if (mode->clock > 135000)
> + return MODE_CLOCK_HIGH;
> +
> + return MODE_OK;
> +}
> +
Are we talking about the CLKOUT frequency? Because that's the one I
see depending on the dual/single output mode, and I assume we're
checking for the mode->clock of the DRM mode to be applied to the
connector (which receives an RGB stream from this bridge).
In case we're talking about CLKOUT, I read
"Dual LVDS port IN/Dual TTL port Out Mode:
8 - 135MHz(CLKOUT)
Dual LVDS port IN/Single TTL port Out Mode:
40 - 150MHz(CLKOUT)"
If we're talking about the PLL input clock (RCLK) then used to
generate CLKOUT it's indeed defined in the 8-135Mhz range, but
I don't see mention on it depending on the mode.
> static void thc63_enable(struct drm_bridge *bridge)
> {
> struct thc63_dev *thc63 = to_thc63(bridge);
> @@ -77,6 +94,7 @@ static void thc63_disable(struct drm_bridge *bridge)
>
> static const struct drm_bridge_funcs thc63_bridge_func = {
> .attach = thc63_attach,
> + .mode_valid = thc63_mode_valid,
> .enable = thc63_enable,
> .disable = thc63_disable,
> };
> --
> Regards,
>
> Laurent Pinchart
>
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next prev parent reply other threads:[~2018-09-11 13:32 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-04 12:10 [PATCH 00/16] R-Car D3/E3 display support (with LVDS PLL) Laurent Pinchart
2018-09-04 12:10 ` [PATCH 01/16] dt-bindings: display: renesas: du: Document r8a77990 bindings Laurent Pinchart
2018-09-14 7:56 ` jacopo mondi
2018-09-17 5:44 ` Rob Herring
2018-09-04 12:10 ` [PATCH 02/16] dt-bindings: display: renesas: lvds: " Laurent Pinchart
2018-09-14 7:57 ` jacopo mondi
2018-09-17 5:44 ` Rob Herring
2018-09-04 12:10 ` [PATCH 03/16] dt-bindings: display: renesas: lvds: Add EXTAL and DU_DOTCLKIN clocks Laurent Pinchart
2018-09-14 8:00 ` jacopo mondi
2018-09-14 8:24 ` Laurent Pinchart
2018-09-14 8:35 ` jacopo mondi
2018-09-04 12:10 ` [PATCH 04/16] drm: bridge: thc63: Restrict modes based on hardware operating frequency Laurent Pinchart
2018-09-11 13:31 ` jacopo mondi [this message]
2018-09-13 21:08 ` Laurent Pinchart
2018-09-13 12:36 ` Andrzej Hajda
2018-09-04 12:10 ` [PATCH 05/16] drm: rcar-du: lvds: D3/E3 support Laurent Pinchart
2018-09-04 14:29 ` Geert Uytterhoeven
2018-09-05 14:01 ` Laurent Pinchart
2018-09-11 13:23 ` jacopo mondi
2018-09-13 21:14 ` Laurent Pinchart
2018-09-04 12:10 ` [PATCH 06/16] drm: rcar-du: Perform the initial CRTC setup from rcar_du_crtc_get() Laurent Pinchart
2018-09-07 18:19 ` jacopo mondi
2018-09-09 16:44 ` Laurent Pinchart
2018-09-04 12:10 ` [PATCH 07/16] drm: rcar-du: Use LVDS PLL clock as dot clock when possible Laurent Pinchart
2018-09-11 14:59 ` jacopo mondi
2018-09-13 21:17 ` Laurent Pinchart
2018-09-04 12:10 ` [PATCH 08/16] drm: rcar-du: Enable configurable DPAD0 routing on Gen3 Laurent Pinchart
2018-09-11 15:46 ` jacopo mondi
2018-09-13 21:25 ` Laurent Pinchart
2018-09-04 12:10 ` [PATCH 09/16] drm: rcar-du: Cache DSYSR value to ensure known initial value Laurent Pinchart
2018-09-04 12:10 ` [PATCH 10/16] drm: rcar-du: Don't use TV sync mode when not supported by the hardware Laurent Pinchart
2018-09-04 12:10 ` [PATCH 11/16] drm: rcar-du: Add r8a77990 and r8a77995 device support Laurent Pinchart
2018-09-04 12:10 ` [PATCH 12/16] arm64: dts: renesas: r8a77990: Add I2C device nodes Laurent Pinchart
2018-09-04 14:32 ` Geert Uytterhoeven
2018-09-04 14:49 ` jacopo mondi
2018-09-05 13:53 ` Laurent Pinchart
2018-09-06 9:26 ` Simon Horman
2018-09-06 9:48 ` Laurent Pinchart
2018-09-05 13:52 ` Laurent Pinchart
2018-09-04 12:10 ` [PATCH 13/16] arm64: dts: renesas: r8a77990: Add display output support Laurent Pinchart
2018-09-04 12:10 ` [PATCH 14/16] arm64: dts: renesas: r8a77995: Add LVDS support Laurent Pinchart
2018-09-04 12:10 ` [PATCH 15/16] arm64: dts: renesas: r8a77990: ebisu: Enable VGA and HDMI outputs Laurent Pinchart
2018-09-04 12:10 ` [PATCH 16/16] arm64: dts: renesas: r8a77995: draak: Enable HDMI display output Laurent Pinchart
2018-09-05 16:22 ` [PATCH 00/16] R-Car D3/E3 display support (with LVDS PLL) jacopo mondi
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