dri-devel.lists.freedesktop.org archive mirror
 help / color / mirror / Atom feed
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH v5 19/28] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
Date: Tue, 16 Oct 2018 22:19:06 +0300	[thread overview]
Message-ID: <20181016191906.GM9144@intel.com> (raw)
In-Reply-To: <20181016190111.GL9144@intel.com>

On Tue, Oct 16, 2018 at 10:01:11PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 05, 2018 at 04:22:57PM -0700, Manasi Navare wrote:
> > On Icelake, a separate power well PG2 is created for
> > VDSC engine used for eDP/MIPI DSI. This patch adds a new
> > display power domain for Power well 2.
> > 
> > v2:
> > * Fix the power well mismatch CI error (Ville)
> > * Rename as VDSC_PIPE_A (Imre)
> > * Fix a whitespace (Anusha)
> > * Fix Comments (Imre)
> > 
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.h    | 1 +
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
> >  2 files changed, 4 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> > index 9eaba1bccae8..4c513169960c 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -256,6 +256,7 @@ enum intel_display_power_domain {
> >  	POWER_DOMAIN_MODESET,
> >  	POWER_DOMAIN_GT_IRQ,
> >  	POWER_DOMAIN_INIT,
> > +	POWER_DOMAIN_VDSC_PIPE_A,
> 
> I'd probably put it next to the other pipe related power domains.
> So maybe after POWER_DOMAIN_PIPE_C_PANEL_FITTER.
> 
> And to match the current naming pattern it should be called
> POWER_DOMAIN_PIPE_A_VDSC.

Hmm. We could also give it an alias TRANSCODER_EDP_VDSC. Making
it an alias would avoid wasting yet another bit, but would make
the code easier to understand as we wouldn't have to add comments
explaining why we use a PIPE_A_VDSC power domain based on the
usage of the EDP transcoder.

The only slightly confusing piece would be
intel_display_power_domain_str() as that would have to reuturn
a string with both names perhaps?

> 
> >  
> >  	POWER_DOMAIN_NUM,
> >  };
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 3cf8533e0834..3ed0a3a1015a 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -146,6 +146,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
> >  		return "MODESET";
> >  	case POWER_DOMAIN_GT_IRQ:
> >  		return "GT_IRQ";
> > +	case POWER_DOMAIN_VDSC_PIPE_A:
> > +		return "VDSC_PIPE_A";
> >  	default:
> >  		MISSING_CASE(domain);
> >  		return "?";
> > @@ -1971,9 +1973,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> >  	 */
> >  #define ICL_PW_2_POWER_DOMAINS (			\
> >  	ICL_PW_3_POWER_DOMAINS |			\
> > +	BIT_ULL(POWER_DOMAIN_VDSC_PIPE_A) |		\
> >  	BIT_ULL(POWER_DOMAIN_INIT))
> >  	/*
> > -	 * - eDP/DSI VDSC
> >  	 * - KVMR (HW control)
> >  	 */
> >  #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
> > -- 
> > 2.18.0
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

  reply	other threads:[~2018-10-16 19:19 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-05 23:22 [PATCH v5 00/28] Display Stream Compression enabling on eDP/DP Manasi Navare
2018-10-05 23:22 ` [PATCH v5 01/28] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Manasi Navare
2018-10-05 23:22 ` [PATCH v5 02/28] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
2018-10-05 23:22 ` [PATCH v5 03/28] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare
2018-10-05 23:22 ` [PATCH v5 04/28] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
2018-10-05 23:22 ` [PATCH v5 05/28] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare
2018-10-05 23:22 ` [PATCH v5 06/28] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare
2018-10-05 23:22 ` [PATCH v5 07/28] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare
2018-10-05 23:22 ` [PATCH v5 08/28] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-10-05 23:22 ` [PATCH v5 09/28] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-10-05 23:22 ` [PATCH v5 10/28] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-10-05 23:22 ` [PATCH v5 11/28] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-10-16  1:27   ` Manasi Navare
2018-10-05 23:22 ` [PATCH v5 12/28] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-10-05 23:22 ` [PATCH v5 13/28] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-10-16  1:29   ` Manasi Navare
2018-10-22 23:53   ` Srivatsa, Anusha
2018-10-05 23:22 ` [PATCH v5 14/28] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-10-05 23:22 ` [PATCH v5 15/28] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-10-22 22:04   ` [Intel-gfx] " Srivatsa, Anusha
2018-10-05 23:22 ` [PATCH v5 16/28] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-10-16  1:31   ` Manasi Navare
2018-10-22 22:26   ` Srivatsa, Anusha
2018-10-05 23:22 ` [PATCH v5 17/28] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-10-22 23:34   ` Srivatsa, Anusha
2018-10-23 18:42     ` Manasi Navare
2018-10-23 18:45       ` Srivatsa, Anusha
2018-10-05 23:22 ` [PATCH v5 18/28] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-10-22 18:50   ` Manasi Navare
2018-10-05 23:22 ` [PATCH v5 19/28] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-10-16  1:22   ` Manasi Navare
2018-10-16 19:01   ` Ville Syrjälä
2018-10-16 19:19     ` Ville Syrjälä [this message]
2018-10-16 19:42       ` Manasi Navare
2018-10-16 19:45         ` Ville Syrjälä
2018-10-16 21:04           ` Manasi Navare
2018-10-16 21:21             ` [Intel-gfx] " Manasi Navare
2018-10-16 19:19     ` Manasi Navare
2018-10-16 19:33       ` Ville Syrjälä
2018-10-05 23:22 ` [PATCH v5 20/28] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-10-16 19:58   ` Srivatsa, Anusha
2018-10-16 21:02     ` Manasi Navare
2018-10-17 16:58       ` Srivatsa, Anusha
2018-10-05 23:22 ` [PATCH v5 21/28] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-10-05 23:23 ` [PATCH v5 22/28] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-10-05 23:23 ` [PATCH v5 23/28] drm/i915/icl: Add Display Stream Splitter control registers Manasi Navare
2018-10-05 23:23 ` [PATCH v5 24/28] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-10-18 17:02   ` Ville Syrjälä
2018-10-19 22:40     ` Manasi Navare
2018-10-05 23:23 ` [PATCH v5 25/28] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-10-05 23:23 ` [PATCH v5 26/28] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-10-16  1:23   ` Manasi Navare
2018-10-16 19:31   ` Ville Syrjälä
2018-10-05 23:23 ` [PATCH v5 27/28] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Manasi Navare
2018-10-05 23:34   ` Lyude Paul
2018-10-09 22:20     ` Manasi Navare
2018-10-09 22:24       ` Lyude Paul
2018-10-05 23:23 ` [PATCH v5 28/28] drm/i915/dsc: Force DSC enable if requested by IGT/userspace Manasi Navare
2018-10-24 17:51   ` Srivatsa, Anusha

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20181016191906.GM9144@intel.com \
    --to=ville.syrjala@linux.intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=manasi.d.navare@intel.com \
    --cc=rodrigo.vivi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).