From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Anusha Srivatsa <anusha.srivatsa@intel.com>,
dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v8 13/19] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
Date: Tue, 6 Nov 2018 16:36:08 +0200 [thread overview]
Message-ID: <20181106143608.GW9144@intel.com> (raw)
In-Reply-To: <20181102213138.301-14-manasi.d.navare@intel.com>
On Fri, Nov 02, 2018 at 02:31:32PM -0700, Manasi Navare wrote:
> After encoder->pre_enable() hook, after link training sequence is
> completed, PPS registers for DSC encoder are configured using the
> DSC state parameters in intel_crtc_state as part of DSC enabling
> routine in the source. DSC enabling routine is called after
> encoder->pre_enable() before enbaling the pipe and after
> compression is enabled on the sink.
>
> v6:
> intel_dsc_enable to be part of pre_enable hook (Ville)
> v5:
> * make crtc_state const (Ville)
> v4:
> * Use cpu_transcoder instead of encoder->type for using EDP transcoder
> DSC registers(Ville)
> * Keep all PSS regs together (Anusha)
>
> v3:
> * Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
> are used (Manasi)
> * Add DSC slice_row_per_frame in PPS16 (Manasi)
>
> v2:
> * Enable PG2 power well for VDSC on eDP
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/intel_ddi.c | 6 +
> drivers/gpu/drm/i915/intel_display.c | 1 +
> drivers/gpu/drm/i915/intel_vdsc.c | 419 +++++++++++++++++++++++++++
> 4 files changed, 428 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d7797a41c648..f347d0d7b9eb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3485,6 +3485,8 @@ extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
> bool interactive);
> extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
> bool enable);
> +extern void intel_dsc_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
>
> int i915_reg_read_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index af12c15ed94f..bba08322afb7 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2962,6 +2962,12 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
>
> if (!is_mst)
> intel_ddi_enable_pipe_clock(crtc_state);
> +
> + /*
> + * Enable and Configure Display Stream Compression in the source
> + * if enabled in intel_crtc_state.
> + */
> + intel_dsc_enable(encoder, crtc_state);
> }
>
> static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 477e53c37353..d3aa77f4d606 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5417,6 +5417,7 @@ static void intel_encoders_pre_enable(struct drm_crtc *crtc,
>
> if (encoder->pre_enable)
> encoder->pre_enable(encoder, crtc_state, conn_state);
> +
Bogus whitespace leftover. Please try to read through your own patches
before sending them. That generally helps catch silly things like this.
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> index a76f78b9c0ee..0eaa69778160 100644
> --- a/drivers/gpu/drm/i915/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -580,3 +580,422 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>
> return 0;
> }
> +
> +static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
> + enum pipe pipe = crtc->pipe;
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 pps_val = 0;
> + u32 rc_buf_thresh_dword[4];
> + u32 rc_range_params_dword[8];
> + u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
> + int i = 0;
> +
> + /* Populate PICTURE_PARAMETER_SET_0 registers */
> + pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
> + DSC_VER_MIN_SHIFT |
> + vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
> + vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
> + if (vdsc_cfg->block_pred_enable)
> + pps_val |= DSC_BLOCK_PREDICTION;
> + else
> + pps_val &= ~DSC_BLOCK_PREDICTION;
> + if (vdsc_cfg->convert_rgb)
> + pps_val |= DSC_COLOR_SPACE_CONVERSION;
> + else
> + pps_val &= ~DSC_COLOR_SPACE_CONVERSION;
> + if (vdsc_cfg->enable422)
> + pps_val |= DSC_422_ENABLE;
> + else
> + pps_val &= ~DSC_422_ENABLE;
> + if (vdsc_cfg->vbr_enable)
> + pps_val |= DSC_VBR_ENABLE;
> + else
> + pps_val &= ~DSC_VBR_ENABLE;
> +
> + DRM_INFO("PPS0 = 0x%08x\n", pps_val);
> + if (cpu_transcoder == TRANSCODER_EDP) {
> + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
> + /*
> + * If 2 VDSC instances are needed, configure PPS for second
> + * VDSC
> + */
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
> + } else {
> + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
> + pps_val);
> + }
> +
> + /* Populate PICTURE_PARAMETER_SET_1 registers */
> + pps_val = 0;
> + pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
> + DRM_INFO("PPS1 = 0x%08x\n", pps_val);
> + if (cpu_transcoder == TRANSCODER_EDP) {
> + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val);
> + /*
> + * If 2 VDSC instances are needed, configure PPS for second
> + * VDSC
> + */
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val);
> + } else {
> + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val);
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
> + pps_val);
> + }
> +
> + /* Populate PICTURE_PARAMETER_SET_2 registers */
> + pps_val = 0;
> + pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
> + DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
> + DRM_INFO("PPS2 = 0x%08x\n", pps_val);
> + if (encoder->type == INTEL_OUTPUT_EDP) {
> + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val);
> + /*
> + * If 2 VDSC instances are needed, configure PPS for second
> + * VDSC
> + */
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val);
> + } else {
> + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val);
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
> + pps_val);
> + }
> +
> + /* Populate PICTURE_PARAMETER_SET_3 registers */
> + pps_val = 0;
> + pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
> + DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
> + DRM_INFO("PPS3 = 0x%08x\n", pps_val);
> + if (cpu_transcoder == TRANSCODER_EDP) {
> + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val);
> + /*
> + * If 2 VDSC instances are needed, configure PPS for second
> + * VDSC
> + */
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val);
> + } else {
> + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val);
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
> + pps_val);
> + }
> +
> + /* Populate PICTURE_PARAMETER_SET_4 registers */
> + pps_val = 0;
> + pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
> + DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
> + DRM_INFO("PPS4 = 0x%08x\n", pps_val);
> + if (cpu_transcoder == TRANSCODER_EDP) {
> + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val);
> + /*
> + * If 2 VDSC instances are needed, configure PPS for second
> + * VDSC
> + */
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val);
> + } else {
> + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val);
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
> + pps_val);
> + }
> +
> + /* Populate PICTURE_PARAMETER_SET_5 registers */
> + pps_val = 0;
> + pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
> + DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
> + DRM_INFO("PPS5 = 0x%08x\n", pps_val);
> + if (cpu_transcoder == TRANSCODER_EDP) {
> + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val);
> + /*
> + * If 2 VDSC instances are needed, configure PPS for second
> + * VDSC
> + */
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val);
> + } else {
> + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val);
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
> + pps_val);
> + }
> +
> + /* Populate PICTURE_PARAMETER_SET_6 registers */
> + pps_val = 0;
> + pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
> + DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
> + DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
> + DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
> + DRM_INFO("PPS6 = 0x%08x\n", pps_val);
> + if (cpu_transcoder == TRANSCODER_EDP) {
> + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val);
> + /*
> + * If 2 VDSC instances are needed, configure PPS for second
> + * VDSC
> + */
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val);
> + } else {
> + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val);
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
> + pps_val);
> + }
> +
> + /* Populate PICTURE_PARAMETER_SET_7 registers */
> + pps_val = 0;
> + pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
> + DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
> + DRM_INFO("PPS7 = 0x%08x\n", pps_val);
> + if (cpu_transcoder == TRANSCODER_EDP) {
> + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val);
> + /*
> + * If 2 VDSC instances are needed, configure PPS for second
> + * VDSC
> + */
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val);
> + } else {
> + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val);
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
> + pps_val);
> + }
> +
> + /* Populate PICTURE_PARAMETER_SET_8 registers */
> + pps_val = 0;
> + pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
> + DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
> + DRM_INFO("PPS8 = 0x%08x\n", pps_val);
> + if (cpu_transcoder == TRANSCODER_EDP) {
> + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val);
> + /*
> + * If 2 VDSC instances are needed, configure PPS for second
> + * VDSC
> + */
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val);
> + } else {
> + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val);
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
> + pps_val);
> + }
> +
> + /* Populate PICTURE_PARAMETER_SET_9 registers */
> + pps_val = 0;
> + pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |
> + DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
> + DRM_INFO("PPS9 = 0x%08x\n", pps_val);
> + if (cpu_transcoder == TRANSCODER_EDP) {
> + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val);
> + /*
> + * If 2 VDSC instances are needed, configure PPS for second
> + * VDSC
> + */
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val);
> + } else {
> + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val);
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
> + pps_val);
> + }
> +
> + /* Populate PICTURE_PARAMETER_SET_10 registers */
> + pps_val = 0;
> + pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
> + DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
> + DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
> + DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
> + DRM_INFO("PPS10 = 0x%08x\n", pps_val);
> + if (cpu_transcoder == TRANSCODER_EDP) {
> + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val);
> + /*
> + * If 2 VDSC instances are needed, configure PPS for second
> + * VDSC
> + */
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val);
> + } else {
> + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val);
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
> + pps_val);
> + }
> +
> + /* Populate Picture parameter set 16 */
> + pps_val = 0;
> + pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
> + DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
> + vdsc_cfg->slice_width) |
> + DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
> + vdsc_cfg->slice_height);
> + DRM_INFO("PPS16 = 0x%08x\n", pps_val);
> + if (cpu_transcoder == TRANSCODER_EDP) {
> + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val);
> + /*
> + * If 2 VDSC instances are needed, configure PPS for second
> + * VDSC
> + */
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val);
> + } else {
> + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val);
> + if (crtc_state->dsc_params.dsc_split)
> + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
> + pps_val);
> + }
> +
> + /* Populate the RC_BUF_THRESH registers */
> + memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> + rc_buf_thresh_dword[i/4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] <<
> + BITS_PER_BYTE * (i % 4));
> + DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i,
> + rc_buf_thresh_dword[i/4]);
> + }
> + if (cpu_transcoder == TRANSCODER_EDP) {
> + I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]);
> + I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]);
> + I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]);
> + I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]);
> + if (crtc_state->dsc_params.dsc_split) {
> + I915_WRITE(DSCC_RC_BUF_THRESH_0,
> + rc_buf_thresh_dword[0]);
> + I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW,
> + rc_buf_thresh_dword[1]);
> + I915_WRITE(DSCC_RC_BUF_THRESH_1,
> + rc_buf_thresh_dword[2]);
> + I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW,
> + rc_buf_thresh_dword[3]);
> + }
> + } else {
> + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe),
> + rc_buf_thresh_dword[0]);
> + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
> + rc_buf_thresh_dword[1]);
> + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe),
> + rc_buf_thresh_dword[2]);
> + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
> + rc_buf_thresh_dword[3]);
> + if (crtc_state->dsc_params.dsc_split) {
> + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe),
> + rc_buf_thresh_dword[0]);
> + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
> + rc_buf_thresh_dword[1]);
> + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe),
> + rc_buf_thresh_dword[2]);
> + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
> + rc_buf_thresh_dword[3]);
> + }
> + }
> +
> + /* Populate the RC_RANGE_PARAMETERS registers */
> + memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
> + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> + rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
> + RC_BPG_OFFSET_SHIFT) |
> + (vdsc_cfg->rc_range_params[i].range_max_qp <<
> + RC_MAX_QP_SHIFT) |
> + (vdsc_cfg->rc_range_params[i].range_min_qp <<
> + RC_MIN_QP_SHIFT)) << 16 * (i % 2));
> + DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i,
> + rc_range_params_dword[i/2]);
> + }
> + if (cpu_transcoder == TRANSCODER_EDP) {
> + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0,
> + rc_range_params_dword[0]);
> + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW,
> + rc_range_params_dword[1]);
> + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1,
> + rc_range_params_dword[2]);
> + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW,
> + rc_range_params_dword[3]);
> + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2,
> + rc_range_params_dword[4]);
> + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW,
> + rc_range_params_dword[5]);
> + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3,
> + rc_range_params_dword[6]);
> + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW,
> + rc_range_params_dword[7]);
> + if (crtc_state->dsc_params.dsc_split) {
> + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0,
> + rc_range_params_dword[0]);
> + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW,
> + rc_range_params_dword[1]);
> + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1,
> + rc_range_params_dword[2]);
> + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW,
> + rc_range_params_dword[3]);
> + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2,
> + rc_range_params_dword[4]);
> + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW,
> + rc_range_params_dword[5]);
> + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3,
> + rc_range_params_dword[6]);
> + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW,
> + rc_range_params_dword[7]);
> + }
> + } else {
> + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
> + rc_range_params_dword[0]);
> + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
> + rc_range_params_dword[1]);
> + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
> + rc_range_params_dword[2]);
> + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
> + rc_range_params_dword[3]);
> + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
> + rc_range_params_dword[4]);
> + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
> + rc_range_params_dword[5]);
> + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
> + rc_range_params_dword[6]);
> + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
> + rc_range_params_dword[7]);
> + if (crtc_state->dsc_params.dsc_split) {
> + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
> + rc_range_params_dword[0]);
> + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
> + rc_range_params_dword[1]);
> + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
> + rc_range_params_dword[2]);
> + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
> + rc_range_params_dword[3]);
> + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
> + rc_range_params_dword[4]);
> + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
> + rc_range_params_dword[5]);
> + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
> + rc_range_params_dword[6]);
> + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
> + rc_range_params_dword[7]);
> + }
> + }
> +}
> +
> +void intel_dsc_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> +
> + if (!crtc_state->dsc_params.compression_enable)
> + return;
> +
> + intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
> +
> + return;
Pointless return
> +}
> --
> 2.18.0
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2018-11-06 14:36 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-02 21:31 [PATCH v8 00/19] DSC enabling remaining patches respin Manasi Navare
2018-11-02 21:31 ` [PATCH v8 01/19] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-02 21:31 ` [PATCH v8 02/19] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-11-02 21:31 ` [PATCH v8 03/19] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-11-02 21:31 ` [PATCH v8 04/19] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-06 1:38 ` Srivatsa, Anusha
2018-11-06 20:17 ` Manasi Navare
2018-11-02 21:31 ` [PATCH v8 05/19] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-11-02 21:31 ` [PATCH v8 06/19] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-02 21:31 ` [PATCH v8 07/19] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-03 2:09 ` Manasi Navare
2018-11-06 14:42 ` Ville Syrjälä
2018-11-06 20:37 ` Manasi Navare
2018-11-07 22:31 ` Manasi Navare
2018-11-06 22:41 ` Srivatsa, Anusha
2018-11-06 22:48 ` Manasi Navare
2018-11-02 21:31 ` [PATCH v8 08/19] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-02 21:31 ` [PATCH v8 09/19] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-02 21:31 ` [PATCH v8 10/19] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-06 14:33 ` Ville Syrjälä
2018-11-06 16:52 ` Manasi Navare
2018-11-06 17:00 ` Ville Syrjälä
2018-11-06 20:14 ` Manasi Navare
2018-11-06 20:30 ` Ville Syrjälä
2018-11-02 21:31 ` [PATCH v8 11/19] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-02 21:31 ` [PATCH v8 12/19] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-11-02 21:31 ` [PATCH v8 13/19] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-06 14:36 ` Ville Syrjälä [this message]
2018-11-06 16:50 ` Manasi Navare
2018-11-02 21:31 ` [PATCH v8 14/19] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-02 21:31 ` [PATCH v8 15/19] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-02 21:31 ` [PATCH v8 16/19] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-02 21:31 ` [PATCH v8 17/19] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-02 21:31 ` [PATCH v8 18/19] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-02 21:31 ` [PATCH v8 19/19] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Manasi Navare
2018-11-03 2:40 ` Manasi Navare
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