From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v9 01/24] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
Date: Mon, 19 Nov 2018 21:43:38 +0200 [thread overview]
Message-ID: <20181119194338.GK9144@intel.com> (raw)
In-Reply-To: <20181114015232.21952-2-manasi.d.navare@intel.com>
On Tue, Nov 13, 2018 at 05:52:09PM -0800, Manasi Navare wrote:
> DSC DPCD color depth register advertises its color depth capabilities
> by setting each of the bits that corresponding to a specific color
> depth. This patch defines those specific color depths and adds
> a helper to return an array of color depth capabilities.
>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/drm_dp_helper.c | 29 +++++++++++++++++++----------
> include/drm/drm_dp_helper.h | 9 +++++----
> 2 files changed, 24 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 6d483487f2b4..286567063960 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1428,17 +1428,26 @@ u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> }
> EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
>
> -u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> +void drm_dp_dsc_sink_color_depth_cap(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
> + u8 *dsc_sink_color_depth_cap)
> {
> + int i, cnt = 0;
> u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
>
> - if (color_depth & DP_DSC_12_BPC)
> - return 12;
> - if (color_depth & DP_DSC_10_BPC)
> - return 10;
> - if (color_depth & DP_DSC_8_BPC)
> - return 8;
> -
> - return 0;
> + for (i = 1; i <= 3; i++) {
> + if (!(color_depth & BIT(i)))
> + continue;
> + switch (i) {
> + case 1:
> + dsc_sink_color_depth_cap[cnt++] = DP_DSC_8_BPC;
> + break;
> + case 2:
> + dsc_sink_color_depth_cap[cnt++] = DP_DSC_10_BPC;
> + break;
> + case 3:
> + dsc_sink_color_depth_cap[cnt++] = DP_DSC_12_BPC;
> + break;
> + }
> + }
> }
> -EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth);
> +EXPORT_SYMBOL(drm_dp_dsc_sink_color_depth_cap);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 3314e91f6eb3..ea3233b0a790 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -242,9 +242,9 @@
> # define DP_DSC_YCbCr420_Native (1 << 4)
>
> #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
> -# define DP_DSC_8_BPC (1 << 1)
> -# define DP_DSC_10_BPC (1 << 2)
> -# define DP_DSC_12_BPC (1 << 3)
> +# define DP_DSC_8_BPC 8
> +# define DP_DSC_10_BPC 10
> +# define DP_DSC_12_BPC 12
I'd suggest something simpler like:
int foo(u8 bpc[3])
{
int num_bpc = 0;
if (color_depth & DP_DSC_12_BPC)
bpc[num_bpc++] = 12;
if (color_depth & DP_DSC_10_BPC)
bpc[num_bpc++] = 10;
if (color_depth & DP_DSC_8_BPC)
bpc[num_bpc++] = 8;
return num_bpc;
}
>
> #define DP_DSC_PEAK_THROUGHPUT 0x06B
> # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
> @@ -1123,7 +1123,8 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
> bool is_edp);
> u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
> -u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE]);
> +void drm_dp_dsc_sink_color_depth_cap(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
> + u8 *dsc_sink_color_depth_cap);
>
> static inline bool
> drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> --
> 2.19.1
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2018-11-19 19:43 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-14 1:52 [PATCH v9 00/24] Remaining DSC + FEC patches Manasi Navare
2018-11-14 1:52 ` [PATCH v9 01/24] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Manasi Navare
2018-11-19 19:43 ` Ville Syrjälä [this message]
2018-11-19 20:10 ` Manasi Navare
2018-11-19 20:33 ` Ville Syrjälä
2018-11-19 22:11 ` Manasi Navare
2018-11-14 1:52 ` [PATCH v9 02/24] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-14 1:52 ` [PATCH v9 03/24] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-11-14 1:52 ` [PATCH v9 04/24] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-11-14 1:52 ` [PATCH v9 05/24] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-14 1:52 ` [PATCH v9 06/24] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-11-14 1:52 ` [PATCH v9 07/24] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-14 1:52 ` [PATCH v9 08/24] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-19 20:11 ` Ville Syrjälä
2018-11-19 21:54 ` Manasi Navare
2018-11-14 1:52 ` [PATCH v9 09/24] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-14 1:52 ` [PATCH v9 10/24] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-14 1:52 ` [PATCH v9 11/24] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-14 1:52 ` [PATCH v9 12/24] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-14 1:52 ` [PATCH v9 13/24] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-11-14 1:52 ` [PATCH v9 14/24] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-19 20:17 ` Ville Syrjälä
2018-11-14 1:52 ` [PATCH v9 15/24] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-14 1:52 ` [PATCH v9 16/24] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-14 1:52 ` [PATCH v9 17/24] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-14 1:52 ` [PATCH v9 18/24] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-14 1:52 ` [PATCH v9 19/24] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-14 1:52 ` [PATCH v9 20/24] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Manasi Navare
2018-11-16 1:39 ` Manasi Navare
2018-11-19 20:27 ` Ville Syrjälä
2018-11-19 22:28 ` Manasi Navare
2018-11-14 1:52 ` [PATCH v9 21/24] i915/dp/fec: Add fec_enable to the crtc state Manasi Navare
2018-11-14 1:52 ` [PATCH v9 22/24] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Manasi Navare
2018-11-19 20:19 ` Ville Syrjälä
2018-11-20 0:43 ` Manasi Navare
2018-11-20 17:13 ` Manasi Navare
2018-11-14 1:52 ` [PATCH v9 23/24] i915/dp/fec: Configure the Forward Error Correction bits Manasi Navare
2018-11-14 1:52 ` [PATCH v9 24/24] drm/i915/fec: Disable FEC state Manasi Navare
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