From: Alexander Shiyan <shc_work@mail.ru>
To: dri-devel@lists.freedesktop.org
Cc: Alexander Shiyan <shc_work@mail.ru>
Subject: [PATCH] gpu: ipu-v3: Fix i.MX51 CSI control registers offset
Date: Thu, 20 Dec 2018 11:06:38 +0300 [thread overview]
Message-ID: <20181220080638.1708-1-shc_work@mail.ru> (raw)
The CSI0/CSI1 registers offset is at +0xe030000/+0xe038000 relative
to the control module registers on IPUv3EX.
This patch fixes wrong values for i.MX51 CSI0/CSI1.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
drivers/gpu/ipu-v3/ipu-common.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index 474b00e19697..5b7cdbfe062f 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -898,8 +898,8 @@ static struct ipu_devtype ipu_type_imx51 = {
.cpmem_ofs = 0x1f000000,
.srm_ofs = 0x1f040000,
.tpm_ofs = 0x1f060000,
- .csi0_ofs = 0x1f030000,
- .csi1_ofs = 0x1f038000,
+ .csi0_ofs = 0x1e030000,
+ .csi1_ofs = 0x1e038000,
.ic_ofs = 0x1e020000,
.disp0_ofs = 0x1e040000,
.disp1_ofs = 0x1e048000,
--
2.13.0
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next reply other threads:[~2018-12-20 8:06 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-20 8:06 Alexander Shiyan [this message]
2019-01-02 12:10 ` [PATCH] gpu: ipu-v3: Fix i.MX51 CSI control registers offset Philipp Zabel
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