From: Thierry Reding <thierry.reding@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-tegra@vger.kernel.org, Dmitry Osipenko <digetx@gmail.com>,
dri-devel@lists.freedesktop.org,
Mikko Perttunen <mperttunen@nvidia.com>
Subject: [PATCH v2 09/13] drm/tegra: Setup shared IOMMU domain after initialization
Date: Thu, 24 Jan 2019 19:02:50 +0100 [thread overview]
Message-ID: <20190124180254.20080-10-thierry.reding@gmail.com> (raw)
In-Reply-To: <20190124180254.20080-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
Move initialization of the shared IOMMU domain after the host1x device
has been initialized. At this point all the Tegra DRM clients have been
attached to the shared IOMMU domain.
This is important because Tegra186 and later use an ARM SMMU, for which
the driver defers setting up the geometry for a domain until a device is
attached to it. This is to ensure that the domain is properly set up for
a specific ARM SMMU instance, which is unknown at allocation time.
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/gpu/drm/tegra/drm.c | 54 ++++++++++++++++++++-----------------
1 file changed, 29 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 61dcbd218ffc..271c7a5fc954 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -92,10 +92,6 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
return -ENOMEM;
if (iommu_present(&platform_bus_type)) {
- u64 carveout_start, carveout_end, gem_start, gem_end;
- struct iommu_domain_geometry *geometry;
- unsigned long order;
-
tegra->domain = iommu_domain_alloc(&platform_bus_type);
if (!tegra->domain) {
err = -ENOMEM;
@@ -105,27 +101,6 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
err = iova_cache_get();
if (err < 0)
goto domain;
-
- geometry = &tegra->domain->geometry;
- gem_start = geometry->aperture_start;
- gem_end = geometry->aperture_end - CARVEOUT_SZ;
- carveout_start = gem_end + 1;
- carveout_end = geometry->aperture_end;
-
- order = __ffs(tegra->domain->pgsize_bitmap);
- init_iova_domain(&tegra->carveout.domain, 1UL << order,
- carveout_start >> order);
-
- tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
- tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
-
- drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
- mutex_init(&tegra->mm_lock);
-
- DRM_DEBUG("IOMMU apertures:\n");
- DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
- DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
- carveout_end);
}
mutex_init(&tegra->clients_lock);
@@ -159,6 +134,35 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
if (err < 0)
goto fbdev;
+ if (tegra->domain) {
+ u64 carveout_start, carveout_end, gem_start, gem_end;
+ dma_addr_t start, end;
+ unsigned long order;
+
+ start = tegra->domain->geometry.aperture_start;
+ end = tegra->domain->geometry.aperture_end;
+
+ gem_start = start;
+ gem_end = end - CARVEOUT_SZ;
+ carveout_start = gem_end + 1;
+ carveout_end = end;
+
+ order = __ffs(tegra->domain->pgsize_bitmap);
+ init_iova_domain(&tegra->carveout.domain, 1UL << order,
+ carveout_start >> order);
+
+ tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
+ tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
+
+ drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
+ mutex_init(&tegra->mm_lock);
+
+ DRM_DEBUG("IOMMU apertures:\n");
+ DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
+ DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
+ carveout_end);
+ }
+
if (tegra->hub) {
err = tegra_display_hub_prepare(tegra->hub);
if (err < 0)
--
2.19.1
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next prev parent reply other threads:[~2019-01-24 18:03 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-24 18:02 [PATCH v2 00/13] drm/tegra: Fix IOVA space on Tegra186 and later Thierry Reding
2019-01-24 18:02 ` [PATCH v2 01/13] gpu: host1x: Set up stream ID table Thierry Reding
2019-01-24 18:02 ` [PATCH v2 02/13] gpu: host1x: Program the channel stream ID Thierry Reding
2019-01-24 18:02 ` [PATCH v2 03/13] gpu: host1x: Support 40-bit addressing Thierry Reding
2019-01-25 9:13 ` Mikko Perttunen
2019-01-25 9:20 ` Thierry Reding
2019-01-25 9:32 ` Mikko Perttunen
2019-01-25 9:34 ` Mikko Perttunen
2019-01-24 18:02 ` [PATCH v2 04/13] gpu: host1x: Use direct DMA with IOMMU API usage Thierry Reding
2019-01-28 14:30 ` Dmitry Osipenko
2019-01-24 18:02 ` [PATCH v2 05/13] gpu: host1x: Restrict IOVA space to DMA mask Thierry Reding
2019-01-24 18:02 ` [PATCH v2 06/13] gpu: host1x: Support 40-bit addressing on Tegra186 Thierry Reding
2019-01-24 18:02 ` [PATCH v2 07/13] drm/tegra: Store parent pointer in Tegra DRM clients Thierry Reding
2019-01-28 14:10 ` Dmitry Osipenko
2019-01-24 18:02 ` [PATCH v2 08/13] drm/tegra: vic: Load firmware on demand Thierry Reding
2019-01-28 14:12 ` Dmitry Osipenko
2019-01-24 18:02 ` Thierry Reding [this message]
2019-01-24 18:02 ` [PATCH v2 10/13] drm/tegra: Restrict IOVA space to DMA mask Thierry Reding
2019-01-24 18:02 ` [PATCH v2 11/13] drm/tegra: vic: Do not clear driver data Thierry Reding
2019-01-24 18:02 ` [PATCH v2 12/13] drm/tegra: vic: Support stream ID register programming Thierry Reding
2019-01-24 18:02 ` [PATCH v2 13/13] arm64: tegra: Enable SMMU for VIC on Tegra186 Thierry Reding
2019-01-24 21:38 ` [PATCH v2 00/13] drm/tegra: Fix IOVA space on Tegra186 and later Dmitry Osipenko
2019-01-25 9:23 ` Thierry Reding
2019-01-25 13:14 ` Dmitry Osipenko
2019-01-24 21:53 ` Dmitry Osipenko
2019-01-25 8:57 ` Mikko Perttunen
2019-01-25 13:18 ` Dmitry Osipenko
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