From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Subject: Re: [PATCH v2 03/13] gpu: host1x: Support 40-bit addressing Date: Fri, 25 Jan 2019 10:20:55 +0100 Message-ID: <20190125092055.GA22320@ulmo> References: <20190124180254.20080-1-thierry.reding@gmail.com> <20190124180254.20080-4-thierry.reding@gmail.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0595554697==" Return-path: Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by gabe.freedesktop.org (Postfix) with ESMTPS id A38806E166 for ; Fri, 25 Jan 2019 09:20:58 +0000 (UTC) Received: by mail-wr1-x441.google.com with SMTP id u4so9485753wrp.3 for ; Fri, 25 Jan 2019 01:20:58 -0800 (PST) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Mikko Perttunen Cc: linux-tegra@vger.kernel.org, Dmitry Osipenko , dri-devel@lists.freedesktop.org, Mikko Perttunen List-Id: dri-devel@lists.freedesktop.org --===============0595554697== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="45Z9DzgjV8m4Oswq" Content-Disposition: inline --45Z9DzgjV8m4Oswq Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Jan 25, 2019 at 11:13:41AM +0200, Mikko Perttunen wrote: > On 24.1.2019 20.02, Thierry Reding wrote: > > From: Thierry Reding > >=20 > > Tegra186 and later support 40 bits of address space. Additional > > registers need to be programmed to store the full 40 bits of push > > buffer addresses. > >=20 > > Since command stream gathers can also reside in buffers in a 40-bit > > address space, a new variant of the GATHER opcode is also introduced. > > It takes two parameters: the first parameter contains the lower 32 > > bits of the address and the second parameter contains bits 32 to 39. > >=20 > > Signed-off-by: Thierry Reding > > --- > > drivers/gpu/host1x/hw/cdma_hw.c | 13 ++++++++--- > > drivers/gpu/host1x/hw/channel_hw.c | 28 +++++++++++++++++++---- > > drivers/gpu/host1x/hw/host1x06_hardware.h | 5 ++++ > > drivers/gpu/host1x/hw/host1x07_hardware.h | 5 ++++ > > 4 files changed, 44 insertions(+), 7 deletions(-) > >=20 > > diff --git a/drivers/gpu/host1x/hw/cdma_hw.c b/drivers/gpu/host1x/hw/cd= ma_hw.c > > index ce320534cbed..6d2b7af2af89 100644 > > --- a/drivers/gpu/host1x/hw/cdma_hw.c > > +++ b/drivers/gpu/host1x/hw/cdma_hw.c > > @@ -68,20 +68,27 @@ static void cdma_timeout_cpu_incr(struct host1x_cdm= a *cdma, u32 getptr, > > static void cdma_start(struct host1x_cdma *cdma) > > { > > struct host1x_channel *ch =3D cdma_to_channel(cdma); > > + u64 start, end; > > if (cdma->running) > > return; > > cdma->last_pos =3D cdma->push_buffer.pos; > > + start =3D cdma->push_buffer.dma; > > + end =3D cdma->push_buffer.dma + cdma->push_buffer.size + 4; > > host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP, > > HOST1X_CHANNEL_DMACTRL); > > /* set base, put and end pointer */ > > - host1x_ch_writel(ch, cdma->push_buffer.dma, HOST1X_CHANNEL_DMASTART); > > + host1x_ch_writel(ch, lower_32_bits(start), HOST1X_CHANNEL_DMASTART); > > host1x_ch_writel(ch, cdma->push_buffer.pos, HOST1X_CHANNEL_DMAPUT); > > - host1x_ch_writel(ch, cdma->push_buffer.dma + cdma->push_buffer.size += 4, > > - HOST1X_CHANNEL_DMAEND); > > + host1x_ch_writel(ch, lower_32_bits(end), HOST1X_CHANNEL_DMAEND); > > + > > +#if HOST1X_HW >=3D 6 > > + host1x_ch_writel(ch, upper_32_bits(start), HOST1X_CHANNEL_DMASTART_HI= ); > > + host1x_ch_writel(ch, upper_32_bits(end), HOST1X_CHANNEL_DMAEND_HI); > > +#endif > > /* reset GET */ > > host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP | > > diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw= /channel_hw.c > > index ff137fe72d34..78fb49539e8c 100644 > > --- a/drivers/gpu/host1x/hw/channel_hw.c > > +++ b/drivers/gpu/host1x/hw/channel_hw.c > > @@ -64,11 +64,31 @@ static void submit_gathers(struct host1x_job *job) > > for (i =3D 0; i < job->num_gathers; i++) { > > struct host1x_job_gather *g =3D &job->gathers[i]; > > - u32 op1 =3D host1x_opcode_gather(g->words); > > - u32 op2 =3D g->base + g->offset; > > + dma_addr_t addr =3D g->base + g->offset; > > + u32 op2, op3; > > - trace_write_gather(cdma, g->bo, g->offset, op1 & 0xffff); > > - host1x_cdma_push(cdma, op1, op2); > > + op2 =3D lower_32_bits(addr); > > + op3 =3D upper_32_bits(addr); > > + > > + trace_write_gather(cdma, g->bo, g->offset, g->words); > > + > > + if (op3 !=3D 0) { > > +#if HOST1X_HW >=3D 6 > > + u32 op1 =3D host1x_opcode_gather_wide(g->words); > > + u32 op4 =3D HOST1X_OPCODE_NOP; > > + > > + host1x_cdma_push(cdma, op1, op2); > > + host1x_cdma_push(cdma, op3, op4); >=20 > This will break if the first push goes as the last slot of the ringbuffer > and the second push goes as the first slot of the ringbuffer. >=20 > Otherwise looks good to me. Why would that break? Isn't the purpose of a ringbuffer to behave as if it was infinitely sequential? If this really is a problem, how do we fix it? Would we have to stash NOPs into the pushbuffer until we wrap around? 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