From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>,
Andrzej Hajda <a.hajda@samsung.com>,
Sasha Levin <sashal@kernel.org>,
dri-devel@lists.freedesktop.org
Subject: [PATCH AUTOSEL 4.20 20/42] drm/bridge: tc358767: fix output H/V syncs
Date: Sat, 9 Feb 2019 13:47:12 -0500 [thread overview]
Message-ID: <20190209184734.125935-20-sashal@kernel.org> (raw)
In-Reply-To: <20190209184734.125935-1-sashal@kernel.org>
From: Tomi Valkeinen <tomi.valkeinen@ti.com>
[ Upstream commit 7923e09c7a766e2d58de7fc395bb84c18e5bc625 ]
The H and V syncs of the DP output are always set to active high. This
patch fixes the syncs by configuring them according to the videomode.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190103115954.12785-7-tomi.valkeinen@ti.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpu/drm/bridge/tc358767.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index a1f3dd2afbb1..391547358756 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -98,6 +98,8 @@
#define DP0_STARTVAL 0x064c
#define DP0_ACTIVEVAL 0x0650
#define DP0_SYNCVAL 0x0654
+#define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15)
+#define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31)
#define DP0_MISC 0x0658
#define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
#define BPC_6 (0 << 5)
@@ -726,7 +728,9 @@ static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay));
- tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0));
+ tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0) |
+ ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) |
+ ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0));
tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
--
2.19.1
next prev parent reply other threads:[~2019-02-09 18:47 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20190209184734.125935-1-sashal@kernel.org>
2019-02-09 18:47 ` [PATCH AUTOSEL 4.20 15/42] drm/bridge: tc358767: add bus flags Sasha Levin
2019-02-09 18:47 ` [PATCH AUTOSEL 4.20 16/42] drm/bridge: tc358767: add defines for DP1_SRCCTRL & PHY_2LANE Sasha Levin
2019-02-09 18:47 ` [PATCH AUTOSEL 4.20 17/42] drm/bridge: tc358767: fix single lane configuration Sasha Levin
2019-02-09 18:47 ` [PATCH AUTOSEL 4.20 18/42] drm/bridge: tc358767: fix initial DP0/1_SRCCTRL value Sasha Levin
2019-02-09 18:47 ` [PATCH AUTOSEL 4.20 19/42] drm/bridge: tc358767: reject modes which require too much BW Sasha Levin
2019-02-09 18:47 ` Sasha Levin [this message]
2019-02-09 18:47 ` [PATCH AUTOSEL 4.20 26/42] drm/amdgpu: fix CPDMA hang in PRT mode for VEGA20 Sasha Levin
2019-02-09 18:47 ` [PATCH AUTOSEL 4.20 27/42] drm/amdgpu: set WRITE_BURST_LENGTH to 64B to workaround SDMA1 hang Sasha Levin
2019-02-09 18:47 ` [PATCH AUTOSEL 4.20 28/42] drm/amdgpu: disable system memory page tables for now Sasha Levin
2019-02-09 18:47 ` [PATCH AUTOSEL 4.20 36/42] drm/nouveau: Don't disable polling in fallback mode Sasha Levin
[not found] ` <20190209184734.125935-1-sashal-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
2019-02-09 18:47 ` [PATCH AUTOSEL 4.20 37/42] drm/nouveau/falcon: avoid touching registers if engine is off Sasha Levin
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