From: Alyssa Rosenzweig <alyssa@rosenzweig.io>
To: Qiang Yu <yuq825@gmail.com>
Cc: lima@lists.freedesktop.org,
Maxime Ripard <maxime.ripard@bootlin.com>,
dri-devel@lists.freedesktop.org, David Airlie <airlied@linux.ie>,
Sean Paul <sean@poorly.run>
Subject: Re: [PATCH v2] drm/fourcc: add ARM GPU tile format
Date: Sat, 9 Mar 2019 18:08:24 -0800 [thread overview]
Message-ID: <20190310020823.GA881@rosenzweig.io> (raw)
In-Reply-To: <20190309140902.9871-1-yuq825@gmail.com>
> +/*
> + * Arm Device code
> + *
> + * Arm has multiple devices which do not share buffer format,
> + * so add a device field at the MSB of the format field to seperate
> + * each device's encoding.
> + */
> +#define DRM_FORMAT_MOD_ARM_DEVICE_AFBC 0x00
> +#define DRM_FORMAT_MOD_ARM_DEVICE_GPU 0x01
> +
> +#define DRM_FORMAT_MOD_ARM_CODE(device, val) \
> + fourcc_mod_code(ARM, ((__u64)device << 48) | ((val) & 0x0000ffffffffffffULL))
> +
> /*
> * Arm Framebuffer Compression (AFBC) modifiers
> *
> @@ -615,7 +628,8 @@ extern "C" {
> * Further information on the use of AFBC modifiers can be found in
> * Documentation/gpu/afbc.rst
> */
> -#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
> +#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
> + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_DEVICE_AFBC, __afbc_mode)
>
> /*
> * AFBC superblock size
> @@ -709,6 +723,21 @@ extern "C" {
> */
> #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
>
> +/*
> + * Arm GPU modifiers
> + */
> +#define DRM_FORMAT_MOD_ARM_GPU(mode) \
> + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_DEVICE_GPU, mode)
> +
Although Utgard does not support AFBC, both Midgard and Bifrost natively
support AFBC for both texturing and rendering. Separating "AFBC" from
"GPU" is incorrect.
It's okay that lima does not support all Arm format codes, but it is
confusing to create a new "device" to describe that.
These hunks are therefore:
NAKed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
> +/*
> + * Arm GPU tiled format
> + *
> + * This is used by ARM Mali Utgard/Midgard GPU. It divides buffer into
> + * 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
> + * in the block are reordered.
> + */
> +#define DRM_FORMAT_MOD_ARM_GPU_TILED DRM_FORMAT_MOD_ARM_GPU(1)
Per above, "DRM_FORMAT_MOD_ARM_GPU(1)" should be "fourcc_mod_code(ARM,
...)" for a suitable number. Besides that, this hunk is:
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
---
Does lima import/export tiled BOs? Panfrost does not, because AFBC is
our preferred format for shared buffers. As far as I know, Midgard
cannot render into the tiled format, only linear or AFBC. I'm curious
what your use case is.
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next prev parent reply other threads:[~2019-03-10 2:08 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-09 14:09 [PATCH v2] drm/fourcc: add ARM GPU tile format Qiang Yu
2019-03-10 2:08 ` Alyssa Rosenzweig [this message]
2019-03-10 2:35 ` Qiang Yu
2019-03-10 2:53 ` Alyssa Rosenzweig
2019-03-10 3:01 ` Qiang Yu
2019-03-10 3:04 ` Alyssa Rosenzweig
2019-03-11 16:00 ` Ayan Halder
2019-03-11 16:39 ` Alyssa Rosenzweig
2019-03-12 1:50 ` Qiang Yu
2019-03-12 15:41 ` Ayan Halder
2019-03-13 13:16 ` Qiang Yu
2019-03-14 22:58 ` Alyssa Rosenzweig
2019-03-14 22:54 ` Alyssa Rosenzweig
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