From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bjorn Andersson Subject: Re: [PATCH RFC 4/6] ARM: dts: msm8974: add display support Date: Mon, 6 May 2019 23:39:02 -0700 Message-ID: <20190507063902.GA2085@tuxbook-pro> References: <20190505130413.32253-1-masneyb@onstation.org> <20190505130413.32253-5-masneyb@onstation.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20190505130413.32253-5-masneyb@onstation.org> Sender: linux-kernel-owner@vger.kernel.org To: Brian Masney Cc: robdclark@gmail.com, sean@poorly.run, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, airlied@linux.ie, daniel@ffwll.ch, linux-kernel@vger.kernel.org, linus.walleij@linaro.org List-Id: dri-devel@lists.freedesktop.org On Sun 05 May 06:04 PDT 2019, Brian Masney wrote: > diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi [..] > + dsi0: dsi@fd922800 { > + status = "disabled"; > + > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0xfd922800 0x1f8>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; > + > + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, > + <&mmcc PCLK0_CLK_SRC>; > + assigned-clock-parents = <&dsi_phy0 0>, > + <&dsi_phy0 1>; > + > + clocks = <&mmcc MDSS_MDP_CLK>, > + <&mmcc MDSS_AHB_CLK>, > + <&mmcc MDSS_AXI_CLK>, > + <&mmcc MDSS_BYTE0_CLK>, > + <&mmcc MDSS_PCLK0_CLK>, > + <&mmcc MDSS_ESC0_CLK>, > + <&mmcc MMSS_MISC_AHB_CLK>; > + clock-names = "mdp_core", > + "iface", > + "bus", > + "byte", > + "pixel", > + "core", > + "core_mmss"; Unless I enable MMSS_MMSSNOC_AXI_CLK and MMSS_S0_AXI_CLK I get some underrun error from DSI. You don't see anything like this? (These clocks are controlled by msm_bus downstream and should be driven by interconnect upstream) Apart from this, I think this looks nice. Happy to see the progress. Regards, Bjorn