From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark Rutland Subject: Re: [PATCH 1/2] drm: add cache support for arm64 Date: Tue, 6 Aug 2019 15:34:57 +0100 Message-ID: <20190806143457.GF475@lakrids.cambridge.arm.com> References: <20190805211451.20176-1-robdclark@gmail.com> <20190806084821.GA17129@lst.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Rob Clark Cc: Christoph Hellwig , Rob Clark , dri-devel , Catalin Marinas , Will Deacon , Maarten Lankhorst , Maxime Ripard , Sean Paul , David Airlie , Daniel Vetter , Allison Randal , Greg Kroah-Hartman , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, LKML List-Id: dri-devel@lists.freedesktop.org On Tue, Aug 06, 2019 at 07:11:41AM -0700, Rob Clark wrote: > On Tue, Aug 6, 2019 at 1:48 AM Christoph Hellwig wrote: > > > > This goes in the wrong direction. drm_cflush_* are a bad API we need to > > get rid of, not add use of it. The reason for that is two-fold: > > > > a) it doesn't address how cache maintaince actually works in most > > platforms. When talking about a cache we three fundamental operations: > > > > 1) write back - this writes the content of the cache back to the > > backing memory > > 2) invalidate - this remove the content of the cache > > 3) write back + invalidate - do both of the above > > Agreed that drm_cflush_* isn't a great API. In this particular case > (IIUC), I need wb+inv so that there aren't dirty cache lines that drop > out to memory later, and so that I don't get a cache hit on > uncached/wc mmap'ing. Is there a cacheable alias lying around (e.g. the linear map), or are these addresses only mapped uncached/wc? If there's a cacheable alias, performing an invalidate isn't sufficient, since a CPU can allocate a new (clean) entry at any point in time (e.g. as a result of prefetching or arbitrary speculation). Thanks, Mark.