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Mon, 31 Aug 2020 20:41:27 -0700 (PDT) Date: Mon, 31 Aug 2020 22:41:23 -0500 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH 03/19] iommu/arm-smmu: Add support for split pagetables Message-ID: <20200901034123.GL3715@yoga> References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-4-robdclark@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200814024114.1177553-4-robdclark@gmail.com> X-Mailman-Approved-At: Tue, 01 Sep 2020 07:31:54 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Sai Prakash Ranjan , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Joerg Roedel , Robin Murphy , dri-devel@lists.freedesktop.org, Stephen Boyd , iommu@lists.linux-foundation.org, Krishna Reddy , Sibi Sankar , Vivek Gautam , Greg Kroah-Hartman , Jon Hunter , freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu 13 Aug 21:40 CDT 2020, Rob Clark wrote: > From: Jordan Crouse > > Enable TTBR1 for a context bank if IO_PGTABLE_QUIRK_ARM_TTBR1 is selected > by the io-pgtable configuration. > > Signed-off-by: Jordan Crouse > Signed-off-by: Rob Clark > --- > drivers/iommu/arm/arm-smmu/arm-smmu.c | 21 ++++++++++++++++----- > drivers/iommu/arm/arm-smmu/arm-smmu.h | 25 +++++++++++++++++++------ > 2 files changed, 35 insertions(+), 11 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c > index 37d8d49299b4..976d43a7f2ff 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c > @@ -552,11 +552,15 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, > cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr; > cb->ttbr[1] = 0; > } else { > - cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > - cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, > - cfg->asid); > + cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, > + cfg->asid); > cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, > - cfg->asid); > + cfg->asid); The old indentation seems more appropriate. Apart from that this looks sensible. Reviewed-by: Bjorn Andersson Regards, Bjorn > + > + if (pgtbl_cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) > + cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > + else > + cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > } > } else { > cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; > @@ -822,7 +826,14 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, > > /* Update the domain's page sizes to reflect the page table format */ > domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; > - domain->geometry.aperture_end = (1UL << ias) - 1; > + > + if (pgtbl_cfg.quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) { > + domain->geometry.aperture_start = ~0UL << ias; > + domain->geometry.aperture_end = ~0UL; > + } else { > + domain->geometry.aperture_end = (1UL << ias) - 1; > + } > + > domain->geometry.force_aperture = true; > > /* Initialise the context bank with our page table cfg */ > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index 83294516ac08..f3e456893f28 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -169,10 +169,12 @@ enum arm_smmu_cbar_type { > #define ARM_SMMU_CB_TCR 0x30 > #define ARM_SMMU_TCR_EAE BIT(31) > #define ARM_SMMU_TCR_EPD1 BIT(23) > +#define ARM_SMMU_TCR_A1 BIT(22) > #define ARM_SMMU_TCR_TG0 GENMASK(15, 14) > #define ARM_SMMU_TCR_SH0 GENMASK(13, 12) > #define ARM_SMMU_TCR_ORGN0 GENMASK(11, 10) > #define ARM_SMMU_TCR_IRGN0 GENMASK(9, 8) > +#define ARM_SMMU_TCR_EPD0 BIT(7) > #define ARM_SMMU_TCR_T0SZ GENMASK(5, 0) > > #define ARM_SMMU_VTCR_RES1 BIT(31) > @@ -350,12 +352,23 @@ struct arm_smmu_domain { > > static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg) > { > - return ARM_SMMU_TCR_EPD1 | > - FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) | > - FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) | > - FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) | > - FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) | > - FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz); > + u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) | > + FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) | > + FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) | > + FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) | > + FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz); > + > + /* > + * When TTBR1 is selected shift the TCR fields by 16 bits and disable > + * translation in TTBR0 > + */ > + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) { > + tcr = (tcr << 16) & ~ARM_SMMU_TCR_A1; > + tcr |= ARM_SMMU_TCR_EPD0; > + } else > + tcr |= ARM_SMMU_TCR_EPD1; > + > + return tcr; > } > > static inline u32 arm_smmu_lpae_tcr2(struct io_pgtable_cfg *cfg) > -- > 2.26.2 > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel