From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
John Harrison <John.C.Harrison@Intel.com>,
dri-devel@lists.freedesktop.org
Subject: [PATCH 06/53] drm/i915/selftests: Allow for larger engine counts
Date: Thu, 1 Jul 2021 13:23:40 -0700 [thread overview]
Message-ID: <20210701202427.1547543-7-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210701202427.1547543-1-matthew.d.roper@intel.com>
From: John Harrison <John.C.Harrison@Intel.com>
Increasing the engine count causes a couple of local array variables
to exceed the kernel stack limit. So make them dynamic allocations
instead.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 10 ++++--
.../gpu/drm/i915/gt/selftest_workarounds.c | 32 ++++++++++++-------
2 files changed, 29 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 08896ae027d5..1e7fe2222479 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -3561,12 +3561,16 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags)
#define BATCH BIT(0)
{
struct task_struct *tsk[I915_NUM_ENGINES] = {};
- struct preempt_smoke arg[I915_NUM_ENGINES];
+ struct preempt_smoke *arg;
struct intel_engine_cs *engine;
enum intel_engine_id id;
unsigned long count;
int err = 0;
+ arg = kmalloc_array(I915_NUM_ENGINES, sizeof(*arg), GFP_KERNEL);
+ if (!arg)
+ return -ENOMEM;
+
for_each_engine(engine, smoke->gt, id) {
arg[id] = *smoke;
arg[id].engine = engine;
@@ -3574,7 +3578,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags)
arg[id].batch = NULL;
arg[id].count = 0;
- tsk[id] = kthread_run(smoke_crescendo_thread, &arg,
+ tsk[id] = kthread_run(smoke_crescendo_thread, arg,
"igt/smoke:%d", id);
if (IS_ERR(tsk[id])) {
err = PTR_ERR(tsk[id]);
@@ -3603,6 +3607,8 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags)
pr_info("Submitted %lu crescendo:%x requests across %d engines and %d contexts\n",
count, flags, smoke->gt->info.num_engines, smoke->ncontext);
+
+ kfree(arg);
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 7ebc4edb8ecf..7a38ce40feb2 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -1175,31 +1175,36 @@ live_gpu_reset_workarounds(void *arg)
{
struct intel_gt *gt = arg;
intel_wakeref_t wakeref;
- struct wa_lists lists;
+ struct wa_lists *lists;
bool ok;
if (!intel_has_gpu_reset(gt))
return 0;
+ lists = kzalloc(sizeof(*lists), GFP_KERNEL);
+ if (!lists)
+ return -ENOMEM;
+
pr_info("Verifying after GPU reset...\n");
igt_global_reset_lock(gt);
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
- reference_lists_init(gt, &lists);
+ reference_lists_init(gt, lists);
- ok = verify_wa_lists(gt, &lists, "before reset");
+ ok = verify_wa_lists(gt, lists, "before reset");
if (!ok)
goto out;
intel_gt_reset(gt, ALL_ENGINES, "live_workarounds");
- ok = verify_wa_lists(gt, &lists, "after reset");
+ ok = verify_wa_lists(gt, lists, "after reset");
out:
- reference_lists_fini(gt, &lists);
+ reference_lists_fini(gt, lists);
intel_runtime_pm_put(gt->uncore->rpm, wakeref);
igt_global_reset_unlock(gt);
+ kfree(lists);
return ok ? 0 : -ESRCH;
}
@@ -1214,16 +1219,20 @@ live_engine_reset_workarounds(void *arg)
struct igt_spinner spin;
struct i915_request *rq;
intel_wakeref_t wakeref;
- struct wa_lists lists;
+ struct wa_lists *lists;
int ret = 0;
if (!intel_has_reset_engine(gt))
return 0;
+ lists = kzalloc(sizeof(*lists), GFP_KERNEL);
+ if (!lists)
+ return -ENOMEM;
+
igt_global_reset_lock(gt);
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
- reference_lists_init(gt, &lists);
+ reference_lists_init(gt, lists);
for_each_engine(engine, gt, id) {
bool ok;
@@ -1235,7 +1244,7 @@ live_engine_reset_workarounds(void *arg)
break;
}
- ok = verify_wa_lists(gt, &lists, "before reset");
+ ok = verify_wa_lists(gt, lists, "before reset");
if (!ok) {
ret = -ESRCH;
goto err;
@@ -1247,7 +1256,7 @@ live_engine_reset_workarounds(void *arg)
goto err;
}
- ok = verify_wa_lists(gt, &lists, "after idle reset");
+ ok = verify_wa_lists(gt, lists, "after idle reset");
if (!ok) {
ret = -ESRCH;
goto err;
@@ -1282,7 +1291,7 @@ live_engine_reset_workarounds(void *arg)
igt_spinner_end(&spin);
igt_spinner_fini(&spin);
- ok = verify_wa_lists(gt, &lists, "after busy reset");
+ ok = verify_wa_lists(gt, lists, "after busy reset");
if (!ok) {
ret = -ESRCH;
goto err;
@@ -1294,9 +1303,10 @@ live_engine_reset_workarounds(void *arg)
break;
}
- reference_lists_fini(gt, &lists);
+ reference_lists_fini(gt, lists);
intel_runtime_pm_put(gt->uncore->rpm, wakeref);
igt_global_reset_unlock(gt);
+ kfree(lists);
igt_flush_test(gt->i915);
--
2.25.4
next prev parent reply other threads:[~2021-07-01 20:26 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-01 20:23 [PATCH 00/53] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper
2021-07-01 20:23 ` [PATCH 01/53] drm/i915: Add "release id" version Matt Roper
2021-07-02 12:33 ` [Intel-gfx] " Tvrtko Ursulin
2021-07-05 11:52 ` Jani Nikula
2021-07-06 21:09 ` Lucas De Marchi
2021-07-07 8:34 ` Jani Nikula
2021-07-07 15:40 ` Lucas De Marchi
2021-07-06 20:57 ` Lucas De Marchi
2021-07-01 20:23 ` [PATCH 02/53] drm/i915: Add XE_HP initial definitions Matt Roper
2021-07-01 20:23 ` [PATCH 03/53] drm/i915: Fork DG1 interrupt handler Matt Roper
2021-07-02 9:21 ` Daniel Vetter
2021-07-06 22:48 ` [Intel-gfx] " Lucas De Marchi
2021-07-07 7:39 ` Daniel Vetter
2021-07-07 15:53 ` Lucas De Marchi
2021-07-01 20:23 ` [PATCH 04/53] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Matt Roper
2021-07-01 22:06 ` Lucas De Marchi
2021-07-01 20:23 ` [PATCH 05/53] drm/i915/gen12: Use fuse info to enable SFC Matt Roper
2021-07-01 22:19 ` [Intel-gfx] " Lucas De Marchi
2021-07-02 12:08 ` Tvrtko Ursulin
2021-07-01 20:23 ` Matt Roper [this message]
2021-07-01 22:33 ` [PATCH 06/53] drm/i915/selftests: Allow for larger engine counts Lucas De Marchi
2021-07-01 20:23 ` [PATCH 07/53] drm/i915/xehp: Extra media engines - Part 1 (engine definitions) Matt Roper
2021-07-02 12:22 ` [Intel-gfx] " Tvrtko Ursulin
2021-07-01 20:23 ` [PATCH 08/53] drm/i915/xehp: Extra media engines - Part 2 (interrupts) Matt Roper
2021-07-02 12:42 ` [Intel-gfx] " Tvrtko Ursulin
2021-07-06 21:15 ` Lucas De Marchi
2021-07-07 7:46 ` Tvrtko Ursulin
2021-07-01 20:23 ` [PATCH 09/53] drm/i915/xehp: Extra media engines - Part 3 (reset) Matt Roper
2021-07-01 20:23 ` [PATCH 10/53] drm/i915/xehp: Xe_HP forcewake support Matt Roper
2021-07-01 20:23 ` [PATCH 11/53] drm/i915/xehp: Define multicast register ranges Matt Roper
2021-07-01 20:23 ` [PATCH 12/53] drm/i915/xehp: Handle new device context ID format Matt Roper
2021-07-01 20:23 ` [PATCH 13/53] drm/i915/xehp: New engine context offsets Matt Roper
2021-07-01 20:23 ` [PATCH 14/53] drm/i915/xehp: handle new steering options Matt Roper
2021-07-01 20:23 ` [PATCH 15/53] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper
2021-07-01 20:23 ` [PATCH 16/53] drm/i915/xehpsdv: add initial XeHP SDV definitions Matt Roper
2021-07-01 21:41 ` Rodrigo Vivi
2021-07-02 7:57 ` Jani Nikula
2021-07-01 20:23 ` [PATCH 17/53] drm/i915/xehp: Changes to ss/eu definitions Matt Roper
2021-07-01 20:23 ` [PATCH 18/53] drm/i915/xehpsdv: Add maximum sseu limits Matt Roper
2021-07-01 20:23 ` [PATCH 19/53] drm/i915/xehpsdv: Add compute DSS type Matt Roper
2021-07-01 20:23 ` [PATCH 20/53] drm/i915/xehpsdv: Define steering tables Matt Roper
2021-07-01 20:23 ` [PATCH 21/53] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper
2021-07-01 20:23 ` [PATCH 22/53] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper
2021-07-01 20:23 ` [PATCH 23/53] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper
2021-07-01 21:41 ` Rodrigo Vivi
2021-07-01 20:23 ` [PATCH 24/53] drm/i915/dg2: add DG2 platform info Matt Roper
2021-07-01 20:23 ` [PATCH 25/53] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV Matt Roper
2021-07-01 20:24 ` [PATCH 26/53] drm/i915/dg2: Add forcewake table Matt Roper
2021-07-01 20:24 ` [PATCH 27/53] drm/i915/dg2: Update LNCF steering ranges Matt Roper
2021-07-01 20:24 ` [PATCH 28/53] drm/i915/dg2: Add SQIDI steering Matt Roper
2021-07-01 20:24 ` [PATCH 29/53] drm/i915/dg2: Add new LRI reg offsets Matt Roper
2021-07-01 20:24 ` [PATCH 30/53] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper
2021-07-01 20:24 ` [PATCH 31/53] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper
2021-07-02 8:57 ` Lionel Landwerlin
2021-07-01 20:24 ` [PATCH 32/53] drm/i915/dg2: Define MOCS table for DG2 Matt Roper
2021-07-01 20:24 ` [PATCH 33/53] drm/i915/dg2: Add fake PCH Matt Roper
2021-07-06 21:47 ` Lucas De Marchi
2021-07-01 20:24 ` [PATCH 34/53] drm/i915/dg2: Add cdclk table and reference clock Matt Roper
2021-07-01 20:24 ` [PATCH 35/53] drm/i915/dg2: Skip shared DPLL handling Matt Roper
2021-07-01 20:24 ` [PATCH 36/53] drm/i915/dg2: Don't wait for AUX power well enable ACKs Matt Roper
2021-07-01 20:24 ` [PATCH 37/53] drm/i915/dg2: Setup display outputs Matt Roper
2021-07-01 20:24 ` [PATCH 38/53] drm/i915/dg2: Add dbuf programming Matt Roper
2021-07-01 20:24 ` [PATCH 39/53] drm/i915/dg2: Don't program BW_BUDDY registers Matt Roper
2021-07-01 20:24 ` [PATCH 40/53] drm/i915/dg2: Don't read DRAM info Matt Roper
2021-07-01 20:24 ` [PATCH 41/53] drm/i915/dg2: DG2 has fixed memory bandwidth Matt Roper
2021-07-01 20:24 ` [PATCH 42/53] drm/i915/dg2: Add MPLLB programming for SNPS PHY Matt Roper
2021-07-01 20:24 ` [PATCH 43/53] drm/i915/dg2: Add MPLLB programming for HDMI Matt Roper
2021-07-01 20:24 ` [PATCH 44/53] drm/i915/dg2: Add vswing programming for SNPS phys Matt Roper
2021-07-02 8:14 ` Jani Nikula
2021-07-01 20:24 ` [PATCH 45/53] drm/i915/dg2: Update modeset sequences Matt Roper
2021-07-02 8:16 ` [Intel-gfx] " Jani Nikula
2021-07-01 20:24 ` [PATCH 46/53] drm/i915/dg2: Classify DG2 PHY types Matt Roper
2021-07-01 20:24 ` [PATCH 47/53] drm/i915/dg2: Wait for SNPS PHY calibration during display init Matt Roper
2021-07-01 20:24 ` [PATCH 48/53] drm/i915/dg2: Update lane disable power state during PSR Matt Roper
2021-07-01 20:24 ` [PATCH 49/53] drm/i915/dg2: Add DG2 to the PSR2 defeature list Matt Roper
2021-07-01 20:24 ` [PATCH 50/53] drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable Matt Roper
2021-07-02 8:19 ` Jani Nikula
2021-08-23 5:42 ` Kulkarni, Vandita
2021-07-01 20:24 ` [PATCH 51/53] drm/i915/display/dsc: Set BPP in the kernel Matt Roper
2021-07-01 20:24 ` [PATCH 52/53] drm/i915/dg2: Update to bigjoiner path Matt Roper
2021-07-09 0:11 ` Navare, Manasi
2021-07-01 20:24 ` [PATCH 53/53] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper
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