From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Stylon Wang <stylon.wang@amd.com>,
Sasha Levin <sashal@kernel.org>,
amd-gfx@lists.freedesktop.org,
Nikola Cornij <nikola.cornij@amd.com>,
Daniel Wheeler <daniel.wheeler@amd.com>,
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>,
dri-devel@lists.freedesktop.org,
Alex Deucher <alexander.deucher@amd.com>
Subject: [PATCH AUTOSEL 5.10 067/137] drm/amd/display: Fix DCN 3.01 DSCCLK validation
Date: Tue, 6 Jul 2021 07:20:53 -0400 [thread overview]
Message-ID: <20210706112203.2062605-67-sashal@kernel.org> (raw)
In-Reply-To: <20210706112203.2062605-1-sashal@kernel.org>
From: Nikola Cornij <nikola.cornij@amd.com>
[ Upstream commit 346cf627fb27c0fea63a041cedbaa4f31784e504 ]
[why]
DSCCLK validation is not necessary because DSCCLK is derrived from
DISPCLK, therefore if DISPCLK validation passes, DSCCLK is valid, too.
Doing DSCLK validation in addition to DISPCLK leads to modes being
wrongly rejected when DSCCLK was incorrectly set outside of DML.
[how]
Remove DSCCLK validation because it's implicitly validated under DISPCLK
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
.../dc/dml/dcn30/display_mode_vba_30.c | 64 ++++++-------------
1 file changed, 21 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 9e0ae18e71fa..d66e89283c48 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -64,6 +64,7 @@ typedef struct {
#define BPP_INVALID 0
#define BPP_BLENDED_PIPE 0xffffffff
#define DCN30_MAX_DSC_IMAGE_WIDTH 5184
+#define DCN30_MAX_FMT_420_BUFFER_WIDTH 4096
static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
@@ -3987,19 +3988,30 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
} else if (v->PlaneRequiredDISPCLKWithoutODMCombine > v->MaxDispclkRoundedDownToDFSGranularity) {
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
- } else if (v->DSCEnabled[k] && (v->HActive[k] > DCN30_MAX_DSC_IMAGE_WIDTH)) {
- v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
- v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
} else {
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
- /*420 format workaround*/
- if (v->HActive[k] > 4096 && v->OutputFormat[k] == dm_420) {
+ }
+ if (v->DSCEnabled[k] && v->HActive[k] > DCN30_MAX_DSC_IMAGE_WIDTH
+ && v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
+ if (v->HActive[k] / 2 > DCN30_MAX_DSC_IMAGE_WIDTH) {
+ v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+ v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
+ } else {
+ v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
+ v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
+ }
+ }
+ if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN30_MAX_FMT_420_BUFFER_WIDTH
+ && v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
+ if (v->HActive[k] / 2 > DCN30_MAX_FMT_420_BUFFER_WIDTH) {
+ v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+ v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
+ } else {
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
}
}
-
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
v->MPCCombine[i][j][k] = false;
v->NoOfDPP[i][j][k] = 4;
@@ -4281,42 +4293,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
}
}
- for (i = 0; i < v->soc.num_states; i++) {
- v->DSCCLKRequiredMoreThanSupported[i] = false;
- for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
- if (v->BlendingAndTiming[k] == k) {
- if (v->Output[k] == dm_dp || v->Output[k] == dm_edp) {
- if (v->OutputFormat[k] == dm_420) {
- v->DSCFormatFactor = 2;
- } else if (v->OutputFormat[k] == dm_444) {
- v->DSCFormatFactor = 1;
- } else if (v->OutputFormat[k] == dm_n422) {
- v->DSCFormatFactor = 2;
- } else {
- v->DSCFormatFactor = 1;
- }
- if (v->RequiresDSC[i][k] == true) {
- if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
- if (v->PixelClockBackEnd[k] / 12.0 / v->DSCFormatFactor
- > (1.0 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * v->MaxDSCCLK[i]) {
- v->DSCCLKRequiredMoreThanSupported[i] = true;
- }
- } else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
- if (v->PixelClockBackEnd[k] / 6.0 / v->DSCFormatFactor
- > (1.0 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * v->MaxDSCCLK[i]) {
- v->DSCCLKRequiredMoreThanSupported[i] = true;
- }
- } else {
- if (v->PixelClockBackEnd[k] / 3.0 / v->DSCFormatFactor
- > (1.0 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * v->MaxDSCCLK[i]) {
- v->DSCCLKRequiredMoreThanSupported[i] = true;
- }
- }
- }
- }
- }
- }
- }
+ /* Skip dscclk validation: as long as dispclk is supported, dscclk is also implicitly supported */
+
for (i = 0; i < v->soc.num_states; i++) {
v->NotEnoughDSCUnits[i] = false;
v->TotalDSCUnitsRequired = 0.0;
@@ -5319,7 +5297,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
for (j = 0; j < 2; j++) {
if (v->ScaleRatioAndTapsSupport == 1 && v->SourceFormatPixelAndScanSupport == 1 && v->ViewportSizeSupport[i][j] == 1
&& v->DIOSupport[i] == 1 && v->ODMCombine4To1SupportCheckOK[i] == 1
- && v->NotEnoughDSCUnits[i] == 0 && v->DSCCLKRequiredMoreThanSupported[i] == 0
+ && v->NotEnoughDSCUnits[i] == 0
&& v->DTBCLKRequiredMoreThanSupported[i] == 0
&& v->ROBSupport[i][j] == 1 && v->DISPCLK_DPPCLK_Support[i][j] == 1 && v->TotalAvailablePipesSupport[i][j] == 1
&& EnoughWritebackUnits == 1 && WritebackModeSupport == 1
--
2.30.2
next prev parent reply other threads:[~2021-07-06 11:23 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-06 11:19 [PATCH AUTOSEL 5.10 001/137] drm/etnaviv: fix NULL check before some freeing functions is not needed Sasha Levin
2021-07-06 11:19 ` [PATCH AUTOSEL 5.10 002/137] drm/mxsfb: Don't select DRM_KMS_FB_HELPER Sasha Levin
2021-07-06 11:19 ` [PATCH AUTOSEL 5.10 003/137] drm/zte: " Sasha Levin
2021-07-06 11:19 ` [PATCH AUTOSEL 5.10 004/137] drm/ast: Fixed CVE for DP501 Sasha Levin
2021-07-06 11:19 ` [PATCH AUTOSEL 5.10 005/137] drm/amd/display: fix HDCP reset sequence on reinitialize Sasha Levin
2021-07-06 11:19 ` [PATCH AUTOSEL 5.10 006/137] drm/amd/amdgpu/sriov disable all ip hw status by default Sasha Levin
2021-07-06 11:19 ` [PATCH AUTOSEL 5.10 007/137] drm/vc4: fix argument ordering in vc4_crtc_get_margins() Sasha Levin
2021-07-06 11:19 ` [PATCH AUTOSEL 5.10 008/137] drm/bridge: nwl-dsi: Force a full modeset when crtc_state->active is changed to be true Sasha Levin
2021-07-06 11:19 ` [PATCH AUTOSEL 5.10 010/137] drm/amd/display: fix use_max_lb flag for 420 pixel formats Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 017/137] drm/mediatek: Fix PM reference leak in mtk_crtc_ddp_hw_init() Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 019/137] drm/bridge: lt9611: Add missing MODULE_DEVICE_TABLE Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 021/137] drm/virtio: Fixes a potential NULL pointer dereference on probe failure Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 022/137] drm/virtio: Fix double free " Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 027/137] drm/scheduler: Fix hang when sched_entity released Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 028/137] drm/sched: Avoid data corruptions Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 030/137] drm/vc4: Fix clock source for VEC PixelValve on BCM2711 Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 031/137] drm/vc4: hdmi: Fix PM reference leak in vc4_hdmi_encoder_pre_crtc_co() Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 035/137] drm/bridge: cdns: Fix PM reference leak in cdns_dsi_transfer() Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 039/137] drm: rockchip: add missing registers for RK3188 Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 040/137] drm: rockchip: add missing registers for RK3066 Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 045/137] drm: bridge: cdns-mhdp8546: Fix PM reference leak in Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 050/137] drm/amd/display: Avoid HDCP over-read and corruption Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 051/137] drm/amdgpu: remove unsafe optimization to drop preamble ib Sasha Levin
2021-07-06 11:20 ` Sasha Levin [this message]
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 068/137] drm/amd/display: Update scaling settings on modeset Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 069/137] drm/amd/display: Release MST resources on switch from MST to SST Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 070/137] drm/amd/display: Set DISPCLK_MAX_ERRDET_CYCLES to 7 Sasha Levin
2021-07-06 11:20 ` [PATCH AUTOSEL 5.10 071/137] drm/amd/display: Fix off-by-one error in DML Sasha Levin
2021-07-06 11:21 ` [PATCH AUTOSEL 5.10 075/137] drm/amdkfd: use allowed domain for vmbo validation Sasha Levin
2021-07-06 11:21 ` [PATCH AUTOSEL 5.10 079/137] drm/amd/display: Verify Gamma & Degamma LUT sizes in amdgpu_dm_atomic_check Sasha Levin
2021-07-06 11:21 ` [PATCH AUTOSEL 5.10 085/137] drm/amdkfd: fix circular locking on get_wave_state Sasha Levin
2021-07-06 11:21 ` [PATCH AUTOSEL 5.10 086/137] drm/amdkfd: Fix circular lock in nocpsch path Sasha Levin
2021-07-06 11:21 ` [PATCH AUTOSEL 5.10 095/137] drm/amdgpu: fix bad address translation for sienna_cichlid Sasha Levin
2021-07-06 11:21 ` [PATCH AUTOSEL 5.10 096/137] drm/amdkfd: Walk through list with dqm lock hold Sasha Levin
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