From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0605DC07E96 for ; Wed, 7 Jul 2021 00:40:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B9BD361416 for ; Wed, 7 Jul 2021 00:40:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B9BD361416 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 166AE6E7DD; Wed, 7 Jul 2021 00:40:19 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id E11C86E7DD; Wed, 7 Jul 2021 00:40:17 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10037"; a="209038526" X-IronPort-AV: E=Sophos;i="5.83,330,1616482800"; d="scan'208";a="209038526" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jul 2021 17:40:15 -0700 X-IronPort-AV: E=Sophos;i="5.83,330,1616482800"; d="scan'208";a="427760290" Received: from ramaling-i9x.iind.intel.com (HELO intel.com) ([10.99.66.205]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jul 2021 17:40:11 -0700 Date: Wed, 7 Jul 2021 06:11:51 +0530 From: Ramalingam C To: Matthew Auld Subject: Re: [PATCH v3 4/5] drm/i915/uapi: convert drm_i915_gem_set_domain to kernel doc Message-ID: <20210707004151.GC26377@intel.com> References: <20210705135310.1502437-1-matthew.auld@intel.com> <20210705135310.1502437-4-matthew.auld@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210705135310.1502437-4-matthew.auld@intel.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas =?utf-8?Q?Hellstr=C3=B6m?= , Jason Ekstrand , Tvrtko Ursulin , Jordan Justen , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Kenneth Graunke , Daniel Vetter Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 2021-07-05 at 14:53:09 +0100, Matthew Auld wrote: > Convert all the drm_i915_gem_set_domain bits to proper kernel doc. LGTM. Reviewed-by: Ramalingam C > > Suggested-by: Daniel Vetter > Signed-off-by: Matthew Auld > Cc: Thomas Hellström > Cc: Maarten Lankhorst > Cc: Tvrtko Ursulin > Cc: Jordan Justen > Cc: Kenneth Graunke > Cc: Jason Ekstrand > Cc: Daniel Vetter > Cc: Ramalingam C > --- > include/uapi/drm/i915_drm.h | 34 +++++++++++++++++++++++++++++++--- > 1 file changed, 31 insertions(+), 3 deletions(-) > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index a4faceeb8c32..6f94e5e7569a 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -880,14 +880,42 @@ struct drm_i915_gem_mmap_offset { > __u64 extensions; > }; > > + > +/** > + * struct drm_i915_gem_set_domain - Adjust the objects write or read domain, in > + * preparation for accessing the pages via some CPU domain. > + * > + * Specifying a new write or read domain will flush the object out of the > + * previous domain(if required), before then updating the objects domain > + * tracking with the new domain. > + * > + * Note this might involve waiting for the object first if it is still active on > + * the GPU. > + * > + * Supported values for @read_domains and @write_domain: > + * > + * - I915_GEM_DOMAIN_WC: Uncached write-combined domain > + * - I915_GEM_DOMAIN_CPU: CPU cache domain > + * - I915_GEM_DOMAIN_GTT: Mappable aperture domain > + * > + * All other domains are rejected. > + * > + */ > struct drm_i915_gem_set_domain { > - /** Handle for the object */ > + /** @handle: Handle for the object. */ > __u32 handle; > > - /** New read domains */ > + /** > + * @read_domains: New read domains. > + */ > __u32 read_domains; > > - /** New write domain */ > + /** > + * @write_domain: New write domain. > + * > + * Note that having something in the write domain implies it's in the > + * read domain, and only that read domain. > + */ > __u32 write_domain; > }; > > -- > 2.26.3 >