From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED843C07E96 for ; Wed, 7 Jul 2021 00:47:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A6E4161C98 for ; Wed, 7 Jul 2021 00:47:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A6E4161C98 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AB6936E7EC; Wed, 7 Jul 2021 00:47:31 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6ADBD6E7EA; Wed, 7 Jul 2021 00:47:30 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10037"; a="209175854" X-IronPort-AV: E=Sophos;i="5.83,330,1616482800"; d="scan'208";a="209175854" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jul 2021 17:47:29 -0700 X-IronPort-AV: E=Sophos;i="5.83,330,1616482800"; d="scan'208";a="647627472" Received: from ramaling-i9x.iind.intel.com (HELO intel.com) ([10.99.66.205]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jul 2021 17:47:25 -0700 Date: Wed, 7 Jul 2021 06:19:05 +0530 From: Ramalingam C To: Matthew Auld Subject: Re: [PATCH v3 5/5] drm/i915/uapi: reject set_domain for discrete Message-ID: <20210707004904.GD26377@intel.com> References: <20210705135310.1502437-1-matthew.auld@intel.com> <20210705135310.1502437-5-matthew.auld@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210705135310.1502437-5-matthew.auld@intel.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas =?utf-8?Q?Hellstr=C3=B6m?= , Jason Ekstrand , Tvrtko Ursulin , Jordan Justen , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Kenneth Graunke , Daniel Vetter Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 2021-07-05 at 14:53:10 +0100, Matthew Auld wrote: > The CPU domain should be static for discrete, and on DG1 we don't need > any flushing since everything is already coherent, so really all this > does is an object wait, for which we have an ioctl. Longer term the > desired caching should be an immutable creation time property for the > BO, which can be set with something like gem_create_ext. > > One other user is iris + userptr, which uses the set_domain to probe all > the pages to check if the GUP succeeds, however keeping the set_domain > around just for that seems rather scuffed. We could equally just submit > a dummy batch, which should hopefully be good enough, otherwise adding a > new creation time flag for userptr might be an option. Although longer > term we will also have vm_bind, which should also be a nice fit for > this, so adding a whole new flag is likely overkill. > > v2: add some more kernel doc, also add the implicit rules with caching LGTM Reviewed-by: Ramalingam C > > Suggested-by: Daniel Vetter > Signed-off-by: Matthew Auld > Cc: Thomas Hellström > Cc: Maarten Lankhorst > Cc: Tvrtko Ursulin > Cc: Jordan Justen > Cc: Kenneth Graunke > Cc: Jason Ekstrand > Cc: Daniel Vetter > Cc: Ramalingam C > --- > drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++ > include/uapi/drm/i915_drm.h | 18 ++++++++++++++++++ > 2 files changed, 21 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c > index 43004bef55cb..b684a62bf3b0 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c > @@ -490,6 +490,9 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, > u32 write_domain = args->write_domain; > int err; > > + if (IS_DGFX(to_i915(dev))) > + return -ENODEV; > + > /* Only handle setting domains to types used by the CPU. */ > if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) > return -EINVAL; > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index 6f94e5e7569a..fd1a9878730c 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -900,6 +900,24 @@ struct drm_i915_gem_mmap_offset { > * > * All other domains are rejected. > * > + * Note that for discrete, starting from DG1, this is no longer supported, and > + * is instead rejected. On such platforms the CPU domain is effectively static, > + * where we also only support a single &drm_i915_gem_mmap_offset cache mode, > + * which can't be set explicitly and instead depends on the object placements, > + * as per the below. > + * > + * Implicit caching rules, starting from DG1: > + * > + * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) > + * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and > + * mapped as write-combined only. > + * > + * - Everything else is always allocated and mapped as write-back, with the > + * guarantee that everything is also coherent with the GPU. > + * > + * Note that this is likely to change in the future again, where we might need > + * more flexibility on future devices, so making this all explicit as part of a > + * new &drm_i915_gem_create_ext extension is probable. > */ > struct drm_i915_gem_set_domain { > /** @handle: Handle for the object. */ > -- > 2.26.3 >