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[98.233.193.225]) by smtp.gmail.com with ESMTPSA id d15sm1651461qka.3.2022.01.06.21.13.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 21:13:39 -0800 (PST) From: Peter Geis To: Jagan Teki , Thierry Reding , Sam Ravnborg , David Airlie , Daniel Vetter Subject: [PATCH 2/4] drm/panel: feiyang-fy07024di26a30d: make reset gpio optional Date: Fri, 7 Jan 2022 00:13:33 -0500 Message-Id: <20220107051335.3812535-3-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220107051335.3812535-1-pgwipeout@gmail.com> References: <20220107051335.3812535-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org, Peter Geis , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Some implementations do not use the reset signal, instead tying it to dvdd. Make the reset gpio optional to permit this. Signed-off-by: Peter Geis --- drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c index 581661b506f8..1c88d752b14e 100644 --- a/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c +++ b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c @@ -65,7 +65,8 @@ static int feiyang_prepare(struct drm_panel *panel) /* T3 (dvdd rise + avdd start + avdd rise) T3 >= 20ms */ msleep(20); - gpiod_set_value(ctx->reset, 0); + if (ctx->reset) + gpiod_set_value(ctx->reset, 0); /* * T5 + T6 (avdd rise + video & logic signal rise) @@ -73,7 +74,8 @@ static int feiyang_prepare(struct drm_panel *panel) */ msleep(20); - gpiod_set_value(ctx->reset, 1); + if (ctx->reset) + gpiod_set_value(ctx->reset, 1); /* T12 (video & logic signal rise + backlight rise) T12 >= 200ms */ msleep(200); @@ -126,7 +128,8 @@ static int feiyang_unprepare(struct drm_panel *panel) /* T13 (backlight fall + video & logic signal fall) T13 >= 200ms */ msleep(200); - gpiod_set_value(ctx->reset, 0); + if (ctx->reset) + gpiod_set_value(ctx->reset, 0); regulator_disable(ctx->avdd); @@ -211,7 +214,7 @@ static int feiyang_dsi_probe(struct mipi_dsi_device *dsi) return PTR_ERR(ctx->avdd); } - ctx->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW); + ctx->reset = devm_gpiod_get_optional(&dsi->dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(ctx->reset)) { dev_err(&dsi->dev, "Couldn't get our reset GPIO\n"); return PTR_ERR(ctx->reset); -- 2.32.0