From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ABABBC433F5 for ; Tue, 3 May 2022 12:13:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 34B6110F76C; Tue, 3 May 2022 12:13:54 +0000 (UTC) Received: from wout5-smtp.messagingengine.com (wout5-smtp.messagingengine.com [64.147.123.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id B0ED410F76C for ; Tue, 3 May 2022 12:13:52 +0000 (UTC) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.west.internal (Postfix) with ESMTP id 63279320098C; Tue, 3 May 2022 08:13:51 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); Tue, 03 May 2022 08:13:52 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cerno.tech; h=cc :cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm3; t=1651580030; x=1651666430; bh=sv TxL8uNAr19t7v6+3OIHon2dv9U1c1TfS/m8XQSAvI=; b=It8ADgzqpYoRjks9Q7 Ox/SI6eaLWjOlKPvE/Iau89g/O63OR1Z7cBvgULkLIeyaJfhaFDOLjis7mQzJZMK 9hDhpmq9wJQCZ94G0l75lOILSwJDN8QuQU+9rQoOb572mf0EI9s35PHN+1mSLmYs MPcpPO4H86WWSQc+3r8dHJZx2JEtY2iaB74NR7z9v+zBU8NmcAOsJPN94SbvOZdy eRQXIs5bDDRfcBx2NYp5gAcazYYYbC3bZVlfBwNvZiJz/i8Igd5HuPidj46/77W+ iqW/OwRDyIlFnOLjtJPgGYK3nq/bzagp7Iz6Yrr/L2txLIY2deNnWb7sxdFCnqd1 I+Kg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t= 1651580030; x=1651666430; bh=svTxL8uNAr19t7v6+3OIHon2dv9U1c1TfS/ m8XQSAvI=; b=QT6oAMuLG/PbacSSLgR5xMMrtlCoTS/yCVxUoZ4/HAj4QzgHfOn m3FtuA8F5mzOHkGwvQPPZOQb4q6J1aKn3Hfyz4glAVUuEfXYo1GBaz8QjTkTXW+W pZovByM5DhOQ+/qui3bBXpboeBeGQsRiwyUTmGuG/E7eJdvxUuHPyjgus/fSbaIe 82zP9nXOSE8MtEqMTtqOowEU8kJl+IrrFeEJLG7z8Q/P5EPuX6mTDged98VK+wUB aZpubSNjvaB7Qs2TE+61aG8XNTusgPR25mtWOTzZfxyzczf8yVksDld5MJU6/j9k vpM5AyUwS8TDJZdECVXKRa2Csu6cpbimaoA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrvdejgdeglecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpeforgigihhm vgcutfhiphgrrhguuceomhgrgihimhgvsegtvghrnhhordhtvggthheqnecuggftrfgrth htvghrnhepleekfeetudfhkeejiefhtedugfeuvdevkeekteetkefhkefhtdelgfefuddv jefhnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepmh grgihimhgvsegtvghrnhhordhtvggthh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 3 May 2022 08:13:50 -0400 (EDT) From: Maxime Ripard To: Daniel Vetter , David Airlie , Maarten Lankhorst , Thomas Zimmermann , Maxime Ripard Subject: [PATCH 01/14] drm/vc4: plane: Prevent async update if we don't have a dlist Date: Tue, 3 May 2022 14:13:28 +0200 Message-Id: <20220503121341.983842-2-maxime@cerno.tech> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503121341.983842-1-maxime@cerno.tech> References: <20220503121341.983842-1-maxime@cerno.tech> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Melissa Wen , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The vc4 planes are setup in hardware by creating a hardware descriptor in a dedicated RAM. As part of the process to setup a plane in KMS, we thus need to allocate some part of that dedicated RAM to store our descriptor there. The async update path will just reuse the descriptor already allocated for that plane and will modify it directly in RAM to match whatever has been asked for. In order to do that, it will compare the descriptor for the old plane state and the new plane state, will make sure they fit in the same size, and check that only the position or buffer address have changed. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_plane.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c index b3438f4a81ce..811a2d004cc4 100644 --- a/drivers/gpu/drm/vc4/vc4_plane.c +++ b/drivers/gpu/drm/vc4/vc4_plane.c @@ -1321,6 +1321,10 @@ static int vc4_plane_atomic_async_check(struct drm_plane *plane, old_vc4_state = to_vc4_plane_state(plane->state); new_vc4_state = to_vc4_plane_state(new_plane_state); + + if (!new_vc4_state->hw_dlist) + return -EINVAL; + if (old_vc4_state->dlist_count != new_vc4_state->dlist_count || old_vc4_state->pos0_offset != new_vc4_state->pos0_offset || old_vc4_state->pos2_offset != new_vc4_state->pos2_offset || -- 2.35.1