From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: [PATCH 04/11] drm/i915: Fix FEC pipe A vs. DDI A mixup
Date: Tue, 2 May 2023 17:38:59 +0300 [thread overview]
Message-ID: <20230502143906.2401-5-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230502143906.2401-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On pre-TGL FEC is a port level feature, not a transcoder
level features, and it's DDI A which doesn't have it, not
trancodere A. Check for the correct thing when determining
whether FEC is supported or not.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4361c1ac65c3..b27b4fb71ed7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1212,13 +1212,13 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
const struct intel_crtc_state *pipe_config)
{
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- /* On TGL, FEC is supported on all Pipes */
if (DISPLAY_VER(dev_priv) >= 12)
return true;
- if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
+ if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
return true;
return false;
--
2.39.2
next prev parent reply other threads:[~2023-05-02 14:39 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-02 14:38 [PATCH 00/11] drm/i915: MST+DSC nukage and state stuff Ville Syrjala
2023-05-02 14:38 ` [PATCH 01/11] drm/dp_mst: Fix fractional DSC bpp handling Ville Syrjala
2023-05-03 20:37 ` Lyude Paul
2023-05-02 14:38 ` [PATCH 02/11] drm/i915/mst: Remove broken MST DSC support Ville Syrjala
2023-05-03 7:17 ` Lisovskiy, Stanislav
2023-05-03 7:36 ` Lisovskiy, Stanislav
2023-05-03 11:07 ` Ville Syrjälä
2023-05-03 12:23 ` Lisovskiy, Stanislav
2023-06-15 22:11 ` Dave Airlie
2023-05-02 14:38 ` [PATCH 03/11] drm/i915/mst: Read out FEC state Ville Syrjala
2023-05-25 7:56 ` [Intel-gfx] " Luca Coelho
2023-05-02 14:38 ` Ville Syrjala [this message]
2023-05-25 8:00 ` [Intel-gfx] [PATCH 04/11] drm/i915: Fix FEC pipe A vs. DDI A mixup Luca Coelho
2023-05-02 14:39 ` [PATCH 05/11] drm/i915: Check lane count when determining FEC support Ville Syrjala
2023-05-25 8:09 ` [Intel-gfx] " Luca Coelho
2023-09-13 14:41 ` Ville Syrjälä
2023-05-02 14:39 ` [PATCH 06/11] drm/i915: Fix FEC state dump Ville Syrjala
2023-05-25 8:37 ` [Intel-gfx] " Luca Coelho
2023-05-02 14:39 ` [PATCH 07/11] drm/i915: Split some long lines Ville Syrjala
2023-05-25 8:40 ` [Intel-gfx] " Luca Coelho
2023-05-02 14:39 ` [PATCH 08/11] drm/i915: Introduce crtc_state->enhanced_framing Ville Syrjala
2023-05-03 11:36 ` [PATCH v2 " Ville Syrjala
2023-05-25 9:51 ` [Intel-gfx] " Luca Coelho
2023-09-13 14:36 ` Ville Syrjälä
2023-05-02 14:39 ` [PATCH 09/11] drm/i915: Stop spamming the logs with PLL state Ville Syrjala
2023-05-25 9:52 ` [Intel-gfx] " Luca Coelho
2023-05-02 14:39 ` [PATCH 10/11] drm/i915: Drop some redundant eDP checks Ville Syrjala
2023-05-25 9:54 ` [Intel-gfx] " Luca Coelho
2023-05-02 14:39 ` [PATCH 11/11] drm/i915: Reduce combo PHY log spam Ville Syrjala
2023-05-25 9:58 ` [Intel-gfx] " Luca Coelho
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