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From: Lucas Stach <l.stach@pengutronix.de>
To: Andrzej Hajda <andrzej.hajda@intel.com>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Robert Foss <rfoss@kernel.org>
Cc: Marek Vasut <marex@denx.de>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	Jonas Karlman <jonas@kwiboo.se>,
	dri-devel@lists.freedesktop.org, patchwork-lst@pengutronix.de,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	kernel@pengutronix.de
Subject: [PATCH 2/2] drm: bridge: tc358767: give VSDELAY some positive value
Date: Fri,  2 Jun 2023 21:15:01 +0200	[thread overview]
Message-ID: <20230602191501.4138433-2-l.stach@pengutronix.de> (raw)
In-Reply-To: <20230602191501.4138433-1-l.stach@pengutronix.de>

From: David Jander <david@protonic.nl>

The documentation is not clear about how this delay works.
Empirical tests have shown that with a VSDELAY of 0, the first
scanline is not properly formatted in the output stream when
DSI->DP mode is used. The calculation spreadsheets from Toshiba
seem to always make this value equal to the HFP + 10 for DSI->DP
use-case. For DSI->DPI this value should be > 2 and for DPI->DP
it seems to always be 0x64.

Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/gpu/drm/bridge/tc358767.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 46916ae30f8f..9f2c67b4a488 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -817,7 +817,7 @@ static int tc_set_common_video_mode(struct tc_data *tc,
 	 * sync signals
 	 */
 	ret = regmap_write(tc->regmap, VPCTRL0,
-			   FIELD_PREP(VSDELAY, 0) |
+			   FIELD_PREP(VSDELAY, right_margin + 10) |
 			   OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
 	if (ret)
 		return ret;
-- 
2.39.2


  reply	other threads:[~2023-06-02 19:15 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-02 19:15 [PATCH 1/2] drm: bridge: tc358767: increase PLL lock time delay Lucas Stach
2023-06-02 19:15 ` Lucas Stach [this message]
2023-06-02 21:34   ` [PATCH 2/2] drm: bridge: tc358767: give VSDELAY some positive value Marek Vasut
2023-06-07 12:53     ` Lucas Stach
2023-06-07 13:54       ` Marek Vasut
2023-06-08  8:11         ` Lucas Stach
2023-07-08 19:01           ` Marek Vasut
2023-06-02 21:31 ` [PATCH 1/2] drm: bridge: tc358767: increase PLL lock time delay Marek Vasut
2023-07-08 19:02 ` Marek Vasut

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