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From: Andi Shyti <andi.shyti@linux.intel.com>
To: Jonathan Cavitt <jonathan.cavitt@intel.com>,
	Matt Roper <matthew.d.roper@intel.com>,
	Chris Wilson <chris@chris-wilson.co.uk>,
	Mika Kuoppala <mika.kuoppala@linux.intel.com>,
	Nirmoy Das <nirmoy.das@intel.com>,
	Andrzej Hajda <andrzej.hajda@intel.com>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>,
	linux-stable <stable@vger.kernel.org>,
	dri-evel <dri-devel@lists.freedesktop.org>,
	Andi Shyti <andi.shyti@linux.intel.com>
Subject: [PATCH v8 3/9] drm/i915/gt: Ensure memory quiesced before invalidation
Date: Fri, 21 Jul 2023 18:15:08 +0200	[thread overview]
Message-ID: <20230721161514.818895-4-andi.shyti@linux.intel.com> (raw)
In-Reply-To: <20230721161514.818895-1-andi.shyti@linux.intel.com>

From: Jonathan Cavitt <jonathan.cavitt@intel.com>

All memory traffic must be quiesced before requesting
an aux invalidation on platforms that use Aux CCS.

Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: <stable@vger.kernel.org> # v5.8+
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 460c9225a50fc..6210b38a2d382 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -214,7 +214,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 {
 	struct intel_engine_cs *engine = rq->engine;
 
-	if (mode & EMIT_FLUSH) {
+	/*
+	 * On Aux CCS platforms the invalidation of the Aux
+	 * table requires quiescing memory traffic beforehand
+	 */
+	if (mode & EMIT_FLUSH || gen12_needs_ccs_aux_inv(engine)) {
 		u32 flags = 0;
 		int err;
 		u32 *cs;
-- 
2.40.1


  parent reply	other threads:[~2023-07-21 16:16 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-21 16:15 [PATCH v8 0/9] Update AUX invalidation sequence Andi Shyti
2023-07-21 16:15 ` [PATCH v8 1/9] drm/i915/gt: Cleanup aux invalidation registers Andi Shyti
2023-07-21 16:15 ` [PATCH v8 2/9] drm/i915: Add the gen12_needs_ccs_aux_inv helper Andi Shyti
2023-07-21 19:12   ` Matt Roper
2023-07-24  7:52   ` Andrzej Hajda
2023-07-24  8:38   ` [Intel-gfx] " Nirmoy Das
2023-07-21 16:15 ` Andi Shyti [this message]
2023-07-21 16:15 ` [PATCH v8 4/9] drm/i915/gt: Rename flags with bit_group_X according to the datasheet Andi Shyti
2023-07-21 16:15 ` [PATCH v8 5/9] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control Andi Shyti
2023-07-21 19:16   ` Matt Roper
2023-07-24  7:53   ` Andrzej Hajda
2023-07-24  8:47   ` [Intel-gfx] " Nirmoy Das
2023-07-21 16:15 ` [PATCH v8 6/9] drm/i915/gt: Refactor intel_emit_pipe_control_cs() in a single function Andi Shyti
2023-07-24  7:54   ` Andrzej Hajda
2023-07-24  9:07   ` Nirmoy Das
2023-07-24  9:16     ` Andi Shyti
2023-07-24  9:37       ` Nirmoy Das
2023-07-21 16:15 ` [PATCH v8 7/9] drm/i915/gt: Ensure memory quiesced before invalidation for all engines Andi Shyti
2023-07-24  8:19   ` Andrzej Hajda
2023-07-24  9:14     ` Andi Shyti
2023-07-24  9:17       ` Andrzej Hajda
2023-07-21 16:15 ` [PATCH v8 8/9] drm/i915/gt: Poll aux invalidation register bit on invalidation Andi Shyti
2023-07-21 16:15 ` [PATCH v8 9/9] drm/i915/gt: Support aux invalidation on all engines Andi Shyti
2023-07-24  9:42   ` [Intel-gfx] " Andrzej Hajda
2023-07-24 14:35     ` Andi Shyti

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