[PATCH 0/9] drm/i915/dp: Implement POST_LT_ADJ_REQ

[PATCH 0/9] drm/i915/dp: Implement POST_LT_ADJ_REQ

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Implement the POST_LT_ADJ_REQ sequence, which is supposed
to be used to further tune the link vswing/pre-emphasis
when TPS4 is not supported.

Unfortunately I don't have any displays/dongles that support
this so I wasn't able to test anything. Hopefully CI has
something...

Ville Syrjälä (9):
  drm/dp: Add definitions for POST_LT_ADJ training sequence
  drm/dp: Add POST_LT_ADJ_REQ helpers
  drm/i915/dp: Clear DPCD training pattern before transmitting the idle
    pattern
  drm/i915/dp: Have intel_dp_get_adjust_train() tell us if anything
    changed
  drm/i915/dp: Implement the POST_LT_ADJ_REQ sequence
  drm/i915/dp: Move intel_dp_training_pattern()
  drm/i915/dp: Implement .set_idle_link_train() for everyone
  drm/i915/dp: Make .set_idle_link_train() mandatory
  hax: drm/i915: Disable TPS4 support to force POST_LT_ADJ_REQ usage

 drivers/gpu/drm/display/drm_dp_helper.c       |   8 +
 drivers/gpu/drm/i915/display/g4x_dp.c         |  33 ++-
 .../drm/i915/display/intel_dp_link_training.c | 267 +++++++++++++-----
 .../drm/i915/display/intel_dp_link_training.h |   4 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   2 +-
 include/drm/display/drm_dp.h                  |   3 +
 include/drm/display/drm_dp_helper.h           |   8 +
 7 files changed, 253 insertions(+), 72 deletions(-)

-- 
2.45.3

[PATCH 1/9] drm/dp: Add definitions for POST_LT_ADJ training sequence

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add the bit definitions needed for POST_LT_ADJ sequence.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 include/drm/display/drm_dp.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index c413ef68f9a3..260948a8f550 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -115,6 +115,7 @@
 
 #define DP_MAX_LANE_COUNT                   0x002
 # define DP_MAX_LANE_COUNT_MASK		    0x1f
+# define DP_POST_LT_ADJ_REQ_SUPPORTED	    (1 << 5) /* 1.3 */
 # define DP_TPS3_SUPPORTED		    (1 << 6) /* 1.2 */
 # define DP_ENHANCED_FRAME_CAP		    (1 << 7)
 
@@ -571,6 +572,7 @@
 
 #define DP_LANE_COUNT_SET	            0x101
 # define DP_LANE_COUNT_MASK		    0x0f
+# define DP_POST_LT_ADJ_REQ_GRANTED         (1 << 5) /* 1.3 */
 # define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
 
 #define DP_TRAINING_PATTERN_SET	            0x102
@@ -791,6 +793,7 @@
 #define  DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE       (1 << 2) /* 2.0 E11 */
 #define  DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE      (1 << 3) /* 2.0 E11 */
 #define  DP_128B132B_LT_FAILED                          (1 << 4) /* 2.0 E11 */
+#define  DP_POST_LT_ADJ_REQ_IN_PROGRESS                 (1 << 5) /* 1.3 */
 #define  DP_DOWNSTREAM_PORT_STATUS_CHANGED              (1 << 6)
 #define  DP_LINK_STATUS_UPDATED                         (1 << 7)
 
-- 
2.45.3

[PATCH 2/9] drm/dp: Add POST_LT_ADJ_REQ helpers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add small helpers (drm_dp_post_lt_adj_req_supported() and
drm_dp_post_lt_adj_req_in_progress()) to help with implementing
the POST_LT_ADJ_REQ sequence.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/display/drm_dp_helper.c | 8 ++++++++
 include/drm/display/drm_dp_helper.h     | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index f5c596234729..252f022f0837 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -122,6 +122,14 @@ bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
 }
 EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
 
+bool drm_dp_post_lt_adj_req_in_progress(const u8 link_status[DP_LINK_STATUS_SIZE])
+{
+	u8 lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
+
+	return lane_align & DP_POST_LT_ADJ_REQ_IN_PROGRESS;
+}
+EXPORT_SYMBOL(drm_dp_post_lt_adj_req_in_progress);
+
 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
 				     int lane)
 {
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 89a34dff85a4..bec97d29bfa2 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -37,6 +37,7 @@ bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
 			  int lane_count);
 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
 			      int lane_count);
+bool drm_dp_post_lt_adj_req_in_progress(const u8 link_status[DP_LINK_STATUS_SIZE]);
 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
 				     int lane);
 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
@@ -155,6 +156,13 @@ drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 		(dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
 }
 
+static inline bool
+drm_dp_post_lt_adj_req_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+	return dpcd[DP_DPCD_REV] >= 0x13 &&
+		(dpcd[DP_MAX_LANE_COUNT] & DP_POST_LT_ADJ_REQ_SUPPORTED);
+}
+
 static inline bool
 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 {
-- 
2.45.3

[PATCH 3/9] drm/i915/dp: Clear DPCD training pattern before transmitting the idle pattern

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We are supposed to switch off the training pattern in DPCD before
we start transmitting the idle pattern. For LTTPRs we do that
correctly, but for the sink DPRX we only do this correctly
for some platforms.

On pre-HSW (where we don't implement the .set_idle_link_train()
hook), we directly switch from transmitting the training pattern
to normal pixel transmission (the hardware should guarantee that
the minimum number of required idle patters will be transmitted
during this transition).

For HSW+ we start transmitting the idle pattern earlier, and only
switch off the DPCD training pattern after we switch from the idle
pattern to normal pixel transmission. Adjust the code to disable
the DPCD training pattern before we start transmitting the idle
patter.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 11953b03bb6a..b2fb641e4e96 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1125,7 +1125,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp,
 {
 	intel_dp->link_trained = true;
 
-	intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
+	if (!intel_dp->set_idle_link_train)
+		intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
+
 	intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
 					       DP_TRAINING_PATTERN_DISABLE);
 
@@ -1357,8 +1359,10 @@ intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
 	if (ret)
 		ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
 
-	if (intel_dp->set_idle_link_train)
+	if (intel_dp->set_idle_link_train) {
+		intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
 		intel_dp->set_idle_link_train(intel_dp, crtc_state);
+	}
 
 	return ret;
 }
-- 
2.45.3

[PATCH 4/9] drm/i915/dp: Have intel_dp_get_adjust_train() tell us if anything changed

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In order to implement the POST_LT_ADJ_REQ sequence we need to
know whether the sink actually requested a changed to the
vswing/pre-emph values.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_dp_link_training.c  | 18 +++++++++++++-----
 .../drm/i915/display/intel_dp_link_training.h  |  2 +-
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index b2fb641e4e96..2506996bf16d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -489,12 +489,13 @@ static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
 	_TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \
 	_TRAIN_REQ_TX_FFE_ARGS(link_status, 3)
 
-void
+bool
 intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 			  const struct intel_crtc_state *crtc_state,
 			  enum drm_dp_phy dp_phy,
 			  const u8 link_status[DP_LINK_STATUS_SIZE])
 {
+	bool changed = false;
 	int lane;
 
 	if (intel_dp_is_uhbr(crtc_state)) {
@@ -513,10 +514,17 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 		       TRAIN_REQ_PREEMPH_ARGS(link_status));
 	}
 
-	for (lane = 0; lane < 4; lane++)
-		intel_dp->train_set[lane] =
-			intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
-						       dp_phy, link_status, lane);
+	for (lane = 0; lane < 4; lane++) {
+		u8 new = intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
+							dp_phy, link_status, lane);
+		if (intel_dp->train_set[lane] == new)
+			continue;
+
+		intel_dp->train_set[lane] = new;
+		changed = true;
+	}
+
+	return changed;
 }
 
 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 46614124569f..1ba22ed6db08 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -23,7 +23,7 @@ void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
 				   int link_bw, int rate_select, int lane_count,
 				   bool enhanced_framing);
 
-void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+bool intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state,
 			       enum drm_dp_phy dp_phy,
 			       const u8 link_status[DP_LINK_STATUS_SIZE]);
-- 
2.45.3

[PATCH 5/9] drm/i915/dp: Implement the POST_LT_ADJ_REQ sequence

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Implement the POST_LT_ADJ_REQ sequence, which should be used
to further fine tune the link if TPS4 is not supported.
The POST_LT_ADJ_REQ sequence will be performed after
the normal link training has succeeded.

Only the final hop between the last LTTPR and DPRX will
perform the POST_LT_ADJ_REQ adjustment. The earlier hops
will use TPS4 instead since it's mandatory for LTTPRs.

start The sequence will terminate when the sink clears the
"in progress" flag, the vswing/pre-emphasis values have
changed six times, or the vswing/pre-emphasis values have
remained unchanged for 200 ms.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_dp_link_training.c | 128 +++++++++++++++++-
 .../drm/i915/display/intel_dp_link_training.h |   2 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   2 +-
 3 files changed, 128 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2506996bf16d..8863fc2c44ff 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -738,11 +738,14 @@ static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
 
 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
 				   int link_bw, int rate_select, int lane_count,
-				   bool enhanced_framing)
+				   bool enhanced_framing, bool post_lt_adj_req)
 {
 	if (enhanced_framing)
 		lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 
+	if (post_lt_adj_req)
+		lane_count |= DP_POST_LT_ADJ_REQ_GRANTED;
+
 	if (link_bw) {
 		/* DP and eDP v1.3 and earlier link bw set method. */
 		u8 link_config[] = { link_bw, lane_count };
@@ -764,12 +767,25 @@ void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
 	}
 }
 
+static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
+				     const struct intel_crtc_state *crtc_state,
+				     enum drm_dp_phy dp_phy);
+
+static bool intel_dp_use_post_lt_adj_req(struct intel_dp *intel_dp,
+					 const struct intel_crtc_state *crtc_state)
+{
+	return intel_dp->set_idle_link_train &&
+		drm_dp_post_lt_adj_req_supported(intel_dp->dpcd) &&
+		intel_dp_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX) != DP_TRAINING_PATTERN_4;
+}
+
 static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
 					const struct intel_crtc_state *crtc_state,
 					u8 link_bw, u8 rate_select)
 {
 	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count,
-				      crtc_state->enhanced_framing);
+				      crtc_state->enhanced_framing,
+				      intel_dp_use_post_lt_adj_req(intel_dp, crtc_state));
 }
 
 /*
@@ -1087,6 +1103,109 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
 	return channel_eq;
 }
 
+static bool
+intel_dp_post_lt_adj_req(struct intel_dp *intel_dp,
+			 const struct intel_crtc_state *crtc_state)
+{
+	u8 link_status[DP_LINK_STATUS_SIZE];
+	unsigned long deadline;
+	bool timeout = false;
+	bool success = false;
+	int changes = 0;
+
+	if (!intel_dp_use_post_lt_adj_req(intel_dp, crtc_state))
+		return true;
+
+	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
+					     link_status) < 0) {
+		lt_err(intel_dp, DP_PHY_DPRX, "Failed to get link status\n");
+		return false;
+	}
+
+	deadline = jiffies + msecs_to_jiffies_timeout(200);
+
+	for (;;) {
+		/* Make sure clock is still ok */
+		if (!drm_dp_clock_recovery_ok(link_status,
+					      crtc_state->lane_count)) {
+			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
+			lt_dbg(intel_dp, DP_PHY_DPRX,
+			       "Clock recovery check failed, cannot continue POST_LT_ADJ_REQ\n");
+			break;
+		}
+
+		if (!drm_dp_channel_eq_ok(link_status,
+					  crtc_state->lane_count)) {
+			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
+			lt_dbg(intel_dp, DP_PHY_DPRX, "Channel EQ check failed. cannot continue POST_LT_ADJ_REQ\n");
+			break;
+		}
+
+		if (!drm_dp_post_lt_adj_req_in_progress(link_status)) {
+			success = true;
+			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
+			lt_dbg(intel_dp, DP_PHY_DPRX,
+			       "POST_LT_ADJ_REQ done (%d changes). DP Training successful\n", changes);
+			break;
+		}
+
+		if (changes == 6) {
+			success = true;
+			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
+			lt_dbg(intel_dp, DP_PHY_DPRX,
+			       "POST_LT_ADJ_REQ limit reached (%d changes). DP Training successful\n", changes);
+			break;
+		}
+
+		if (timeout) {
+			success = true;
+			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
+			lt_dbg(intel_dp, DP_PHY_DPRX,
+			       "POST_LT_ADJ_REQ timeout reached (%d changes). DP Training successful\n", changes);
+			break;
+		}
+
+		fsleep(5000);
+
+		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
+						     link_status) < 0) {
+			lt_err(intel_dp, DP_PHY_DPRX, "Failed to get link status\n");
+			break;
+		}
+
+		/* Update training set as requested by target */
+		if (intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status)) {
+			deadline = jiffies + msecs_to_jiffies_timeout(200);
+			changes++;
+
+			if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
+				lt_err(intel_dp, DP_PHY_DPRX, "Failed to update link training\n");
+				break;
+			}
+		} else if (time_after(jiffies, deadline)) {
+			timeout = true;
+		}
+	}
+
+	return success;
+}
+
+static void intel_dp_stop_post_lt_adj_req(struct intel_dp *intel_dp,
+					  const struct intel_crtc_state *crtc_state)
+{
+	u8 lane_count;
+
+	if (!intel_dp_use_post_lt_adj_req(intel_dp, crtc_state))
+		return;
+
+	/* clear DP_POST_LT_ADJ_REQ_GRANTED */
+	lane_count = crtc_state->lane_count;
+	if (crtc_state->enhanced_framing)
+		lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);
+}
+
 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,
 						   enum drm_dp_phy dp_phy)
 {
@@ -1372,6 +1491,11 @@ intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
 		intel_dp->set_idle_link_train(intel_dp, crtc_state);
 	}
 
+	if (ret)
+		ret = intel_dp_post_lt_adj_req(intel_dp, crtc_state);
+
+	intel_dp_stop_post_lt_adj_req(intel_dp, crtc_state);
+
 	return ret;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 1ba22ed6db08..33dcbde6a408 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -21,7 +21,7 @@ void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
 				     int link_rate, bool is_vrr);
 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
 				   int link_bw, int rate_select, int lane_count,
-				   bool enhanced_framing);
+				   bool enhanced_framing, bool post_lt_adj_req);
 
 bool intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 167e4a70ab12..d937143ed10f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -2109,7 +2109,7 @@ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
 
 	intel_dp_link_training_set_mode(intel_dp, link_rate, false);
 	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
-				      drm_dp_enhanced_frame_cap(intel_dp->dpcd));
+				      drm_dp_enhanced_frame_cap(intel_dp->dpcd), false);
 
 	intel_mst_set_probed_link_params(intel_dp, link_rate, lane_count);
 }
-- 
2.45.3

[PATCH 6/9] drm/i915/dp: Move intel_dp_training_pattern()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move intel_dp_training_pattern() upwards to avoid the forward
declaration for the POST_LT_ADJ_REQ stuff.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_dp_link_training.c | 112 +++++++++---------
 1 file changed, 54 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 8863fc2c44ff..f208b947ef92 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -767,9 +767,62 @@ void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
 	}
 }
 
+/*
+ * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
+ * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or
+ * 1.2 devices that support it, TPS2 otherwise.
+ */
 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
 				     const struct intel_crtc_state *crtc_state,
-				     enum drm_dp_phy dp_phy);
+				     enum drm_dp_phy dp_phy)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	bool source_tps3, sink_tps3, source_tps4, sink_tps4;
+
+	/* UHBR+ use separate 128b/132b TPS2 */
+	if (intel_dp_is_uhbr(crtc_state))
+		return DP_TRAINING_PATTERN_2;
+
+	/*
+	 * TPS4 support is mandatory for all downstream devices that
+	 * support HBR3. There are no known eDP panels that support
+	 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification.
+	 * LTTPRs must support TPS4.
+	 */
+	source_tps4 = intel_dp_source_supports_tps4(display);
+	sink_tps4 = dp_phy != DP_PHY_DPRX ||
+		    drm_dp_tps4_supported(intel_dp->dpcd);
+	if (source_tps4 && sink_tps4) {
+		return DP_TRAINING_PATTERN_4;
+	} else if (crtc_state->port_clock == 810000) {
+		if (!source_tps4)
+			lt_dbg(intel_dp, dp_phy,
+			       "8.1 Gbps link rate without source TPS4 support\n");
+		if (!sink_tps4)
+			lt_dbg(intel_dp, dp_phy,
+			       "8.1 Gbps link rate without sink TPS4 support\n");
+	}
+
+	/*
+	 * TPS3 support is mandatory for downstream devices that
+	 * support HBR2. However, not all sinks follow the spec.
+	 */
+	source_tps3 = intel_dp_source_supports_tps3(display);
+	sink_tps3 = dp_phy != DP_PHY_DPRX ||
+		    drm_dp_tps3_supported(intel_dp->dpcd);
+	if (source_tps3 && sink_tps3) {
+		return  DP_TRAINING_PATTERN_3;
+	} else if (crtc_state->port_clock >= 540000) {
+		if (!source_tps3)
+			lt_dbg(intel_dp, dp_phy,
+			       ">=5.4/6.48 Gbps link rate without source TPS3 support\n");
+		if (!sink_tps3)
+			lt_dbg(intel_dp, dp_phy,
+			       ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
+	}
+
+	return DP_TRAINING_PATTERN_2;
+}
 
 static bool intel_dp_use_post_lt_adj_req(struct intel_dp *intel_dp,
 					 const struct intel_crtc_state *crtc_state)
@@ -971,63 +1024,6 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
 	return false;
 }
 
-/*
- * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
- * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or
- * 1.2 devices that support it, TPS2 otherwise.
- */
-static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
-				     const struct intel_crtc_state *crtc_state,
-				     enum drm_dp_phy dp_phy)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-	bool source_tps3, sink_tps3, source_tps4, sink_tps4;
-
-	/* UHBR+ use separate 128b/132b TPS2 */
-	if (intel_dp_is_uhbr(crtc_state))
-		return DP_TRAINING_PATTERN_2;
-
-	/*
-	 * TPS4 support is mandatory for all downstream devices that
-	 * support HBR3. There are no known eDP panels that support
-	 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification.
-	 * LTTPRs must support TPS4.
-	 */
-	source_tps4 = intel_dp_source_supports_tps4(display);
-	sink_tps4 = dp_phy != DP_PHY_DPRX ||
-		    drm_dp_tps4_supported(intel_dp->dpcd);
-	if (source_tps4 && sink_tps4) {
-		return DP_TRAINING_PATTERN_4;
-	} else if (crtc_state->port_clock == 810000) {
-		if (!source_tps4)
-			lt_dbg(intel_dp, dp_phy,
-			       "8.1 Gbps link rate without source TPS4 support\n");
-		if (!sink_tps4)
-			lt_dbg(intel_dp, dp_phy,
-			       "8.1 Gbps link rate without sink TPS4 support\n");
-	}
-
-	/*
-	 * TPS3 support is mandatory for downstream devices that
-	 * support HBR2. However, not all sinks follow the spec.
-	 */
-	source_tps3 = intel_dp_source_supports_tps3(display);
-	sink_tps3 = dp_phy != DP_PHY_DPRX ||
-		    drm_dp_tps3_supported(intel_dp->dpcd);
-	if (source_tps3 && sink_tps3) {
-		return  DP_TRAINING_PATTERN_3;
-	} else if (crtc_state->port_clock >= 540000) {
-		if (!source_tps3)
-			lt_dbg(intel_dp, dp_phy,
-			       ">=5.4/6.48 Gbps link rate without source TPS3 support\n");
-		if (!sink_tps3)
-			lt_dbg(intel_dp, dp_phy,
-			       ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
-	}
-
-	return DP_TRAINING_PATTERN_2;
-}
-
 /*
  * Perform the link training channel equalization phase on the given DP PHY
  * using one of training pattern 2, 3 or 4 depending on the source and
-- 
2.45.3

[PATCH 7/9] drm/i915/dp: Implement .set_idle_link_train() for everyone

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

All platforms are capable of explicitly transmitting the idle
pattern. Implement it for everyone (so far it as implemented
only for HSW+).

The immediate benefit is that we gain support for the
POST_LT_ADJ_REQ sequence for all platforms.

Another potential future use would be a pseudo port sync mode on
pre-BDW where we attempt to sync up multiple ports/pipes by trying
to turn on the transcoders at the same time, and switching the
links to normal pixel transmission at the same time.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c | 33 +++++++++++++++++++++++++--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 372c3683c193..390f9b476a11 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -621,6 +621,19 @@ cpt_set_link_train(struct intel_dp *intel_dp,
 	intel_de_posting_read(display, intel_dp->output_reg);
 }
 
+static void
+cpt_set_idle_link_train(struct intel_dp *intel_dp,
+			const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
+	intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
+
+	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
+	intel_de_posting_read(display, intel_dp->output_reg);
+}
+
 static void
 g4x_set_link_train(struct intel_dp *intel_dp,
 		   const struct intel_crtc_state *crtc_state,
@@ -649,6 +662,19 @@ g4x_set_link_train(struct intel_dp *intel_dp,
 	intel_de_posting_read(display, intel_dp->output_reg);
 }
 
+static void
+g4x_set_idle_link_train(struct intel_dp *intel_dp,
+			const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
+	intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
+
+	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
+	intel_de_posting_read(display, intel_dp->output_reg);
+}
+
 static void intel_dp_enable_port(struct intel_dp *intel_dp,
 				 const struct intel_crtc_state *crtc_state)
 {
@@ -1353,10 +1379,13 @@ bool g4x_dp_init(struct intel_display *display,
 	intel_encoder->audio_disable = g4x_dp_audio_disable;
 
 	if ((display->platform.ivybridge && port == PORT_A) ||
-	    (HAS_PCH_CPT(dev_priv) && port != PORT_A))
+	    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
 		dig_port->dp.set_link_train = cpt_set_link_train;
-	else
+		dig_port->dp.set_idle_link_train = cpt_set_idle_link_train;
+	} else {
 		dig_port->dp.set_link_train = g4x_set_link_train;
+		dig_port->dp.set_idle_link_train = g4x_set_idle_link_train;
+	}
 
 	if (display->platform.cherryview)
 		intel_encoder->set_signal_levels = chv_set_signal_levels;
-- 
2.45.3

[PATCH 8/9] drm/i915/dp: Make .set_idle_link_train() mandatory

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Everyone implements the .set_idle_link_train() hook now.
Just make it mandatory.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index f208b947ef92..3bd15054effe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -827,8 +827,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
 static bool intel_dp_use_post_lt_adj_req(struct intel_dp *intel_dp,
 					 const struct intel_crtc_state *crtc_state)
 {
-	return intel_dp->set_idle_link_train &&
-		drm_dp_post_lt_adj_req_supported(intel_dp->dpcd) &&
+	return drm_dp_post_lt_adj_req_supported(intel_dp->dpcd) &&
 		intel_dp_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX) != DP_TRAINING_PATTERN_4;
 }
 
@@ -1248,9 +1247,6 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp,
 {
 	intel_dp->link_trained = true;
 
-	if (!intel_dp->set_idle_link_train)
-		intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
-
 	intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
 					       DP_TRAINING_PATTERN_DISABLE);
 
@@ -1482,10 +1478,8 @@ intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
 	if (ret)
 		ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
 
-	if (intel_dp->set_idle_link_train) {
-		intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
-		intel_dp->set_idle_link_train(intel_dp, crtc_state);
-	}
+	intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
+	intel_dp->set_idle_link_train(intel_dp, crtc_state);
 
 	if (ret)
 		ret = intel_dp_post_lt_adj_req(intel_dp, crtc_state);
-- 
2.45.3

[PATCH 9/9] hax: drm/i915: Disable TPS4 support to force POST_LT_ADJ_REQ usage

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Disable TPS4 in favor of POST_LT_ADJ_REQ for testing purposes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 3bd15054effe..7ccfa202dbc0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -792,6 +792,13 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
 	source_tps4 = intel_dp_source_supports_tps4(display);
 	sink_tps4 = dp_phy != DP_PHY_DPRX ||
 		    drm_dp_tps4_supported(intel_dp->dpcd);
+
+	/* hax */
+	if (dp_phy == DP_PHY_DPRX &&
+	    drm_dp_post_lt_adj_req_supported(intel_dp->dpcd) &&
+	    crtc_state->port_clock != 810000)
+		sink_tps4 = false;
+
 	if (source_tps4 && sink_tps4) {
 		return DP_TRAINING_PATTERN_4;
 	} else if (crtc_state->port_clock == 810000) {
-- 
2.45.3

Re: [PATCH 1/9] drm/dp: Add definitions for POST_LT_ADJ training sequence

[Jani Nikula]

On Mon, 24 Feb 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add the bit definitions needed for POST_LT_ADJ sequence.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  include/drm/display/drm_dp.h | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index c413ef68f9a3..260948a8f550 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -115,6 +115,7 @@
>  
>  #define DP_MAX_LANE_COUNT                   0x002
>  # define DP_MAX_LANE_COUNT_MASK		    0x1f
> +# define DP_POST_LT_ADJ_REQ_SUPPORTED	    (1 << 5) /* 1.3 */
>  # define DP_TPS3_SUPPORTED		    (1 << 6) /* 1.2 */
>  # define DP_ENHANCED_FRAME_CAP		    (1 << 7)
>  
> @@ -571,6 +572,7 @@
>  
>  #define DP_LANE_COUNT_SET	            0x101
>  # define DP_LANE_COUNT_MASK		    0x0f
> +# define DP_POST_LT_ADJ_REQ_GRANTED         (1 << 5) /* 1.3 */
>  # define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
>  
>  #define DP_TRAINING_PATTERN_SET	            0x102
> @@ -791,6 +793,7 @@
>  #define  DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE       (1 << 2) /* 2.0 E11 */
>  #define  DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE      (1 << 3) /* 2.0 E11 */
>  #define  DP_128B132B_LT_FAILED                          (1 << 4) /* 2.0 E11 */
> +#define  DP_POST_LT_ADJ_REQ_IN_PROGRESS                 (1 << 5) /* 1.3 */

Should be bit 1. Bit 5 is reserved.

BR,
Jani.


>  #define  DP_DOWNSTREAM_PORT_STATUS_CHANGED              (1 << 6)
>  #define  DP_LINK_STATUS_UPDATED                         (1 << 7)

-- 
Jani Nikula, Intel

[PATCH v2 1/9] drm/dp: Add definitions for POST_LT_ADJ training sequence

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add the bit definitions needed for POST_LT_ADJ sequence.

v2: DP_POST_LT_ADJ_REQ_IN_PROGRESS is bit 1 not 5 (Jani)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 include/drm/display/drm_dp.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index c413ef68f9a3..e2d2ae573d8b 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -115,6 +115,7 @@
 
 #define DP_MAX_LANE_COUNT                   0x002
 # define DP_MAX_LANE_COUNT_MASK		    0x1f
+# define DP_POST_LT_ADJ_REQ_SUPPORTED	    (1 << 5) /* 1.3 */
 # define DP_TPS3_SUPPORTED		    (1 << 6) /* 1.2 */
 # define DP_ENHANCED_FRAME_CAP		    (1 << 7)
 
@@ -571,6 +572,7 @@
 
 #define DP_LANE_COUNT_SET	            0x101
 # define DP_LANE_COUNT_MASK		    0x0f
+# define DP_POST_LT_ADJ_REQ_GRANTED         (1 << 5) /* 1.3 */
 # define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
 
 #define DP_TRAINING_PATTERN_SET	            0x102
@@ -788,6 +790,7 @@
 
 #define DP_LANE_ALIGN_STATUS_UPDATED                    0x204
 #define  DP_INTERLANE_ALIGN_DONE                        (1 << 0)
+#define  DP_POST_LT_ADJ_REQ_IN_PROGRESS                 (1 << 1) /* 1.3 */
 #define  DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE       (1 << 2) /* 2.0 E11 */
 #define  DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE      (1 << 3) /* 2.0 E11 */
 #define  DP_128B132B_LT_FAILED                          (1 << 4) /* 2.0 E11 */
-- 
2.45.3

Re: [PATCH 0/9] drm/i915/dp: Implement POST_LT_ADJ_REQ

[Imre Deak]

On Mon, Feb 24, 2025 at 07:26:36PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Implement the POST_LT_ADJ_REQ sequence, which is supposed
> to be used to further tune the link vswing/pre-emphasis
> when TPS4 is not supported.
> 
> Unfortunately I don't have any displays/dongles that support
> this so I wasn't able to test anything. Hopefully CI has
> something...

On patches 1-8:
Tested-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>

Few nits later on the patches.

> Ville Syrjälä (9):
>   drm/dp: Add definitions for POST_LT_ADJ training sequence
>   drm/dp: Add POST_LT_ADJ_REQ helpers
>   drm/i915/dp: Clear DPCD training pattern before transmitting the idle
>     pattern
>   drm/i915/dp: Have intel_dp_get_adjust_train() tell us if anything
>     changed
>   drm/i915/dp: Implement the POST_LT_ADJ_REQ sequence
>   drm/i915/dp: Move intel_dp_training_pattern()
>   drm/i915/dp: Implement .set_idle_link_train() for everyone
>   drm/i915/dp: Make .set_idle_link_train() mandatory
>   hax: drm/i915: Disable TPS4 support to force POST_LT_ADJ_REQ usage
> 
>  drivers/gpu/drm/display/drm_dp_helper.c       |   8 +
>  drivers/gpu/drm/i915/display/g4x_dp.c         |  33 ++-
>  .../drm/i915/display/intel_dp_link_training.c | 267 +++++++++++++-----
>  .../drm/i915/display/intel_dp_link_training.h |   4 +-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |   2 +-
>  include/drm/display/drm_dp.h                  |   3 +
>  include/drm/display/drm_dp_helper.h           |   8 +
>  7 files changed, 253 insertions(+), 72 deletions(-)
> 
> -- 
> 2.45.3
> 

Re: [PATCH v2 1/9] drm/dp: Add definitions for POST_LT_ADJ training sequence

[Imre Deak]

On Thu, Feb 27, 2025 at 10:42:32PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add the bit definitions needed for POST_LT_ADJ sequence.
> 
> v2: DP_POST_LT_ADJ_REQ_IN_PROGRESS is bit 1 not 5 (Jani)
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  include/drm/display/drm_dp.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index c413ef68f9a3..e2d2ae573d8b 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -115,6 +115,7 @@
>  
>  #define DP_MAX_LANE_COUNT                   0x002
>  # define DP_MAX_LANE_COUNT_MASK		    0x1f
> +# define DP_POST_LT_ADJ_REQ_SUPPORTED	    (1 << 5) /* 1.3 */
>  # define DP_TPS3_SUPPORTED		    (1 << 6) /* 1.2 */
>  # define DP_ENHANCED_FRAME_CAP		    (1 << 7)
>  
> @@ -571,6 +572,7 @@
>  
>  #define DP_LANE_COUNT_SET	            0x101
>  # define DP_LANE_COUNT_MASK		    0x0f
> +# define DP_POST_LT_ADJ_REQ_GRANTED         (1 << 5) /* 1.3 */
>  # define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
>  
>  #define DP_TRAINING_PATTERN_SET	            0x102
> @@ -788,6 +790,7 @@
>  
>  #define DP_LANE_ALIGN_STATUS_UPDATED                    0x204
>  #define  DP_INTERLANE_ALIGN_DONE                        (1 << 0)
> +#define  DP_POST_LT_ADJ_REQ_IN_PROGRESS                 (1 << 1) /* 1.3 */

DP2.1a also uses this flag as
"LANE_CNT_CONVERSION_FAILED" on UHBR, I guess that should be added
separately.

>  #define  DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE       (1 << 2) /* 2.0 E11 */
>  #define  DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE      (1 << 3) /* 2.0 E11 */
>  #define  DP_128B132B_LT_FAILED                          (1 << 4) /* 2.0 E11 */
> -- 
> 2.45.3
> 

Re: [PATCH 5/9] drm/i915/dp: Implement the POST_LT_ADJ_REQ sequence

[Imre Deak]

On Mon, Feb 24, 2025 at 07:26:41PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Implement the POST_LT_ADJ_REQ sequence, which should be used
> to further fine tune the link if TPS4 is not supported.
> The POST_LT_ADJ_REQ sequence will be performed after
> the normal link training has succeeded.
> 
> Only the final hop between the last LTTPR and DPRX will
> perform the POST_LT_ADJ_REQ adjustment. The earlier hops
> will use TPS4 instead since it's mandatory for LTTPRs.
> 
> start The sequence will terminate when the sink clears the
  ^ typo?

> "in progress" flag, the vswing/pre-emphasis values have
> changed six times, or the vswing/pre-emphasis values have
> remained unchanged for 200 ms.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  .../drm/i915/display/intel_dp_link_training.c | 128 +++++++++++++++++-
>  .../drm/i915/display/intel_dp_link_training.h |   2 +-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |   2 +-
>  3 files changed, 128 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 2506996bf16d..8863fc2c44ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -738,11 +738,14 @@ static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
>  
>  void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>  				   int link_bw, int rate_select, int lane_count,
> -				   bool enhanced_framing)
> +				   bool enhanced_framing, bool post_lt_adj_req)
>  {
>  	if (enhanced_framing)
>  		lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>  
> +	if (post_lt_adj_req)
> +		lane_count |= DP_POST_LT_ADJ_REQ_GRANTED;
> +
>  	if (link_bw) {
>  		/* DP and eDP v1.3 and earlier link bw set method. */
>  		u8 link_config[] = { link_bw, lane_count };
> @@ -764,12 +767,25 @@ void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>  	}
>  }
>  
> +static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
> +				     const struct intel_crtc_state *crtc_state,
> +				     enum drm_dp_phy dp_phy);
> +
> +static bool intel_dp_use_post_lt_adj_req(struct intel_dp *intel_dp,
> +					 const struct intel_crtc_state *crtc_state)
> +{
> +	return intel_dp->set_idle_link_train &&
> +		drm_dp_post_lt_adj_req_supported(intel_dp->dpcd) &&
> +		intel_dp_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX) != DP_TRAINING_PATTERN_4;
> +}
> +
>  static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
>  					const struct intel_crtc_state *crtc_state,
>  					u8 link_bw, u8 rate_select)
>  {
>  	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count,
> -				      crtc_state->enhanced_framing);
> +				      crtc_state->enhanced_framing,
> +				      intel_dp_use_post_lt_adj_req(intel_dp, crtc_state));
>  }
>  
>  /*
> @@ -1087,6 +1103,109 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
>  	return channel_eq;
>  }
>  
> +static bool
> +intel_dp_post_lt_adj_req(struct intel_dp *intel_dp,
> +			 const struct intel_crtc_state *crtc_state)
> +{
> +	u8 link_status[DP_LINK_STATUS_SIZE];
> +	unsigned long deadline;
> +	bool timeout = false;
> +	bool success = false;
> +	int changes = 0;
> +
> +	if (!intel_dp_use_post_lt_adj_req(intel_dp, crtc_state))
> +		return true;
> +
> +	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
> +					     link_status) < 0) {
> +		lt_err(intel_dp, DP_PHY_DPRX, "Failed to get link status\n");
> +		return false;
> +	}
> +
> +	deadline = jiffies + msecs_to_jiffies_timeout(200);
> +
> +	for (;;) {
> +		/* Make sure clock is still ok */
> +		if (!drm_dp_clock_recovery_ok(link_status,
> +					      crtc_state->lane_count)) {
> +			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
> +			lt_dbg(intel_dp, DP_PHY_DPRX,
> +			       "Clock recovery check failed, cannot continue POST_LT_ADJ_REQ\n");
> +			break;
> +		}
> +
> +		if (!drm_dp_channel_eq_ok(link_status,
> +					  crtc_state->lane_count)) {
> +			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
> +			lt_dbg(intel_dp, DP_PHY_DPRX, "Channel EQ check failed. cannot continue POST_LT_ADJ_REQ\n");
> +			break;
> +		}
> +
> +		if (!drm_dp_post_lt_adj_req_in_progress(link_status)) {
> +			success = true;
> +			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
> +			lt_dbg(intel_dp, DP_PHY_DPRX,
> +			       "POST_LT_ADJ_REQ done (%d changes). DP Training successful\n", changes);
> +			break;
> +		}
> +
> +		if (changes == 6) {
> +			success = true;
> +			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
> +			lt_dbg(intel_dp, DP_PHY_DPRX,
> +			       "POST_LT_ADJ_REQ limit reached (%d changes). DP Training successful\n", changes);
> +			break;
> +		}
> +
> +		if (timeout) {
> +			success = true;
> +			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
> +			lt_dbg(intel_dp, DP_PHY_DPRX,
> +			       "POST_LT_ADJ_REQ timeout reached (%d changes). DP Training successful\n", changes);
> +			break;
> +		}
> +
> +		fsleep(5000);
> +
> +		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
> +						     link_status) < 0) {
> +			lt_err(intel_dp, DP_PHY_DPRX, "Failed to get link status\n");
> +			break;
> +		}
> +
> +		/* Update training set as requested by target */
> +		if (intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status)) {
> +			deadline = jiffies + msecs_to_jiffies_timeout(200);
> +			changes++;
> +
> +			if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
> +				lt_err(intel_dp, DP_PHY_DPRX, "Failed to update link training\n");
> +				break;
> +			}
> +		} else if (time_after(jiffies, deadline)) {
> +			timeout = true;
> +		}
> +	}
> +
> +	return success;
> +}
> +
> +static void intel_dp_stop_post_lt_adj_req(struct intel_dp *intel_dp,
> +					  const struct intel_crtc_state *crtc_state)
> +{
> +	u8 lane_count;
> +
> +	if (!intel_dp_use_post_lt_adj_req(intel_dp, crtc_state))
> +		return;
> +
> +	/* clear DP_POST_LT_ADJ_REQ_GRANTED */
> +	lane_count = crtc_state->lane_count;
> +	if (crtc_state->enhanced_framing)
> +		lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> +
> +	drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);
> +}
> +
>  static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,
>  						   enum drm_dp_phy dp_phy)
>  {
> @@ -1372,6 +1491,11 @@ intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
>  		intel_dp->set_idle_link_train(intel_dp, crtc_state);
>  	}
>  
> +	if (ret)
> +		ret = intel_dp_post_lt_adj_req(intel_dp, crtc_state);
> +
> +	intel_dp_stop_post_lt_adj_req(intel_dp, crtc_state);
> +
>  	return ret;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> index 1ba22ed6db08..33dcbde6a408 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> @@ -21,7 +21,7 @@ void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
>  				     int link_rate, bool is_vrr);
>  void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>  				   int link_bw, int rate_select, int lane_count,
> -				   bool enhanced_framing);
> +				   bool enhanced_framing, bool post_lt_adj_req);
>  
>  bool intel_dp_get_adjust_train(struct intel_dp *intel_dp,
>  			       const struct intel_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 167e4a70ab12..d937143ed10f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -2109,7 +2109,7 @@ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
>  
>  	intel_dp_link_training_set_mode(intel_dp, link_rate, false);
>  	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
> -				      drm_dp_enhanced_frame_cap(intel_dp->dpcd));
> +				      drm_dp_enhanced_frame_cap(intel_dp->dpcd), false);
>  
>  	intel_mst_set_probed_link_params(intel_dp, link_rate, lane_count);
>  }
> -- 
> 2.45.3
> 

Re: [PATCH 7/9] drm/i915/dp: Implement .set_idle_link_train() for everyone

[Imre Deak]

On Mon, Feb 24, 2025 at 07:26:43PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> All platforms are capable of explicitly transmitting the idle
> pattern. Implement it for everyone (so far it as implemented
                                                ^was
> only for HSW+).
> 
> The immediate benefit is that we gain support for the
> POST_LT_ADJ_REQ sequence for all platforms.
> 
> Another potential future use would be a pseudo port sync mode on
> pre-BDW where we attempt to sync up multiple ports/pipes by trying
> to turn on the transcoders at the same time, and switching the
> links to normal pixel transmission at the same time.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/g4x_dp.c | 33 +++++++++++++++++++++++++--
>  1 file changed, 31 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 372c3683c193..390f9b476a11 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -621,6 +621,19 @@ cpt_set_link_train(struct intel_dp *intel_dp,
>  	intel_de_posting_read(display, intel_dp->output_reg);
>  }
>  
> +static void
> +cpt_set_idle_link_train(struct intel_dp *intel_dp,
> +			const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
> +	intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
> +
> +	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
> +	intel_de_posting_read(display, intel_dp->output_reg);
> +}
> +
>  static void
>  g4x_set_link_train(struct intel_dp *intel_dp,
>  		   const struct intel_crtc_state *crtc_state,
> @@ -649,6 +662,19 @@ g4x_set_link_train(struct intel_dp *intel_dp,
>  	intel_de_posting_read(display, intel_dp->output_reg);
>  }
>  
> +static void
> +g4x_set_idle_link_train(struct intel_dp *intel_dp,
> +			const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
> +	intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
> +
> +	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
> +	intel_de_posting_read(display, intel_dp->output_reg);
> +}

AFAICS the above could be also used in intel_dp_link_down().

> +
>  static void intel_dp_enable_port(struct intel_dp *intel_dp,
>  				 const struct intel_crtc_state *crtc_state)
>  {
> @@ -1353,10 +1379,13 @@ bool g4x_dp_init(struct intel_display *display,
>  	intel_encoder->audio_disable = g4x_dp_audio_disable;
>  
>  	if ((display->platform.ivybridge && port == PORT_A) ||
> -	    (HAS_PCH_CPT(dev_priv) && port != PORT_A))
> +	    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
>  		dig_port->dp.set_link_train = cpt_set_link_train;
> -	else
> +		dig_port->dp.set_idle_link_train = cpt_set_idle_link_train;
> +	} else {
>  		dig_port->dp.set_link_train = g4x_set_link_train;
> +		dig_port->dp.set_idle_link_train = g4x_set_idle_link_train;
> +	}
>  
>  	if (display->platform.cherryview)
>  		intel_encoder->set_signal_levels = chv_set_signal_levels;
> -- 
> 2.45.3
>