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Wed, 18 Jun 2025 07:33:19 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adec81c0135sm1052257566b.47.2025.06.18.07.33.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 07:33:18 -0700 (PDT) From: Krzysztof Kozlowski Date: Wed, 18 Jun 2025 16:32:31 +0200 Subject: [PATCH v7 02/13] dt-bindings: display/msm: dsi-controller-main: Add SM8750 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250618-b4-sm8750-display-v7-2-a591c609743d@linaro.org> References: <20250618-b4-sm8750-display-v7-0-a591c609743d@linaro.org> In-Reply-To: <20250618-b4-sm8750-display-v7-0-a591c609743d@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4373; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=yhNmcVev6YviCoPWMe9VUWm+x64YmaIBhLXpEPpZ7Gk=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoUs4bib0TEGjh6PRC3ElS2V34P5xI8OZ4+ka/N sivMV7mbICJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaFLOGwAKCRDBN2bmhouD 14NhEACDDmu3EbTY6hDUY95YqoiGg3PZANS7q++04+7UPtSdj0ys1bAuZidDqDqhVFaA3Zmlz7y QZ4TCxzra/I7YX3fhJeQLhRxT+R/Cfmt8+cb3vJxMEz6r1cd5m3dIwLHL6kngjuTNIvNY3gCMaA NMOCzYcgyf73U6Yz7a68S2CmJM+ZjXMjZLb4RG5WWOfHmbGtfn3kM5i8KIFjSV0sfGsbpFPrBnu hkTN0bVYhu0TG3EZfrPOAa1V89etmpwA9r7Y6KVLkk1g4S/lKWu1voKp5T8Mb5P1qfH5lwWyDn6 vfT6iU6HsGS1KrvyT3hpD+YG1ZYcMY9CIhO3HryqTLEeIoRS6VBGvMjHhKLy2MNr6t9FwDdAjtt RPqfaxnXJBKTpylwR469a+/0PGndp7cd4kcy4rQp+BGcnP7SGGFXr45ejv3fTh+AIlPBEnf1P4o zM8A4XVW8hJINDJJtDsIgIUgctAlJdwIC2J+q1MuzStRCVM/djebQL8tpftqKSgvb1feH/dN57f nJ6x2WiB7CS974UPU0p5QxHpcxWcZa5Q789njnS5KYGOifRcTHH/X1oEoE/XTYJGFytM2Q92Y4+ 3MXVYF24f/7pYMz9Of7lIJSsbA5f5tKqgacRWgx0eMBPIaJ57ob9Hc6a70dDGoHsk6HRtkzaT4Y mgZsli/RbyL8hhA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add DSI controller for Qualcomm SM8750 SoC which is quite different from previous (SM8650) generation. It does not allow the display clock controller clocks like "byte" and "pixel" to be reparented to DSI PHY PLLs while the DSI PHY PLL is not configured (not prepared, rate not set). Therefore assigned-clock-parents are not working here and driver is responsible for reparenting clocks with proper procedure. These clocks are now inputs to the DSI controller device. Except that SM8750 DSI comes with several differences, new blocks and changes in registers, making it incompatible with SM8650. Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski --- .../bindings/display/msm/dsi-controller-main.yaml | 54 ++++++++++++++++++++-- 1 file changed, 49 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 82fe95a6d9599b5799549356451278564dc070de..d4bb65c660af8ce8a6bda129a8275c579a705871 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -42,6 +42,7 @@ properties: - qcom,sm8450-dsi-ctrl - qcom,sm8550-dsi-ctrl - qcom,sm8650-dsi-ctrl + - qcom,sm8750-dsi-ctrl - const: qcom,mdss-dsi-ctrl - enum: - qcom,dsi-ctrl-6g-qcm2290 @@ -70,11 +71,11 @@ properties: - mnoc:: MNOC clock - pixel:: Display pixel clock. minItems: 3 - maxItems: 9 + maxItems: 12 clock-names: minItems: 3 - maxItems: 9 + maxItems: 12 phys: maxItems: 1 @@ -109,7 +110,8 @@ properties: minItems: 2 maxItems: 4 description: | - Parents of "byte" and "pixel" for the given platform. + For DSI on SM8650 and older: parents of "byte" and "pixel" for the given + platform. For DSIv2 platforms this should contain "byte", "esc", "src" and "pixel_src" clocks. @@ -218,8 +220,6 @@ required: - clocks - clock-names - phys - - assigned-clocks - - assigned-clock-parents - ports allOf: @@ -244,6 +244,9 @@ allOf: - const: byte - const: pixel - const: core + required: + - assigned-clocks + - assigned-clock-parents - if: properties: @@ -266,6 +269,9 @@ allOf: - const: byte - const: pixel - const: core + required: + - assigned-clocks + - assigned-clock-parents - if: properties: @@ -288,6 +294,9 @@ allOf: - const: pixel - const: core - const: core_mmss + required: + - assigned-clocks + - assigned-clock-parents - if: properties: @@ -309,6 +318,9 @@ allOf: - const: core_mmss - const: pixel - const: core + required: + - assigned-clocks + - assigned-clock-parents - if: properties: @@ -346,6 +358,35 @@ allOf: - const: core - const: iface - const: bus + required: + - assigned-clocks + - assigned-clock-parents + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8750-dsi-ctrl + then: + properties: + clocks: + minItems: 12 + maxItems: 12 + clock-names: + items: + - const: byte + - const: byte_intf + - const: pixel + - const: core + - const: iface + - const: bus + - const: dsi_pll_pixel + - const: dsi_pll_byte + - const: esync + - const: osc + - const: byte_src + - const: pixel_src - if: properties: @@ -369,6 +410,9 @@ allOf: - const: core_mmss - const: pixel - const: core + required: + - assigned-clocks + - assigned-clock-parents unevaluatedProperties: false -- 2.45.2