[PATCH 0/5] sunxi: Various minor V3s clock/pinctrl fixes

[PATCH 0/5] sunxi: Various minor V3s clock/pinctrl fixes

[Paul Kocialkowski]

This is a mixed-bag of minor fixes for V3s clocks and pinctrl.

The last patch is a weak attempt at accomodating using both the display
engine and tcon along with the camera subsystem. The main issue is that
the tcon and de need to have the same clock parent, which may not be
the case depending on the pixel rate. Bringing the de block to the same
clock rate as the csi block helps in some cases.

Paul Kocialkowski (5):
  pinctrl: sunxi: v3s: Fix wrong comment about UART2 pinmux
  clk: sunxi-ng: v3s: Fix CSI SCLK clock name
  clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name
  clk: sunxi-ng: v3s: Fix TCON clock parents
  drm/sun4i: Run the mixer clock at 297 MHz on V3s

 .../bindings/media/allwinner,sun6i-a31-csi.yaml    |  2 +-
 .../bindings/media/allwinner,sun6i-a31-isp.yaml    |  2 +-
 .../media/allwinner,sun6i-a31-mipi-csi2.yaml       |  2 +-
 arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi         |  2 +-
 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c               | 14 +++++++-------
 drivers/gpu/drm/sun4i/sun8i_mixer.c                | 12 ++++++------
 drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c          |  2 +-
 include/dt-bindings/clock/sun8i-v3s-ccu.h          |  2 +-
 8 files changed, 19 insertions(+), 19 deletions(-)

-- 
2.49.0

[PATCH 1/5] pinctrl: sunxi: v3s: Fix wrong comment about UART2 pinmux

[Paul Kocialkowski]

The original comment doesn't match the pin attribution, probably due
to a hasty copy/paste.

Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
---
 drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
index 696d7dd8d87b..2e3bd36a4410 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
@@ -45,7 +45,7 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-		  SUNXI_FUNCTION(0x2, "uart2"),		/* D1 */
+		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */
 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),	/* PB_EINT3 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
-- 
2.49.0

Re: [PATCH 1/5] pinctrl: sunxi: v3s: Fix wrong comment about UART2 pinmux

[Icenowy Zheng]

在 2025-07-01星期二的 22:11 +0200，Paul Kocialkowski写道：
> The original comment doesn't match the pin attribution, probably due
> to a hasty copy/paste.
> 
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> ---
>  drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> index 696d7dd8d87b..2e3bd36a4410 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
> @@ -45,7 +45,7 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[]
> = {
>         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
>                   SUNXI_FUNCTION(0x0, "gpio_in"),
>                   SUNXI_FUNCTION(0x1, "gpio_out"),
> -                 SUNXI_FUNCTION(0x2, "uart2"),         /* D1 */
> +                 SUNXI_FUNCTION(0x2, "uart2"),         /* CTS */

LGTM. Blame to my ADHD ;-)

Reviewed-by: Icenowy Zheng <uwu@icenowy.me>

>                   SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PB_EINT3
> */
>         SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
>                   SUNXI_FUNCTION(0x0, "gpio_in"),

Re: [PATCH 1/5] pinctrl: sunxi: v3s: Fix wrong comment about UART2 pinmux

[Chen-Yu Tsai]

On Wed, Jul 2, 2025 at 4:13 AM Paul Kocialkowski <paulk@sys-base.io> wrote:
>
> The original comment doesn't match the pin attribution, probably due
> to a hasty copy/paste.
>
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>

Acked-by Chen-Yu Tsai <wens@csie.org>

Re: [PATCH 1/5] pinctrl: sunxi: v3s: Fix wrong comment about UART2 pinmux

[Linus Walleij]

On Tue, Jul 1, 2025 at 10:13 PM Paul Kocialkowski <paulk@sys-base.io> wrote:

> The original comment doesn't match the pin attribution, probably due
> to a hasty copy/paste.
>
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>

This patch 1/5 applied to the pin control tree.

Yours,
Linus Walleij

[PATCH 2/5] clk: sunxi-ng: v3s: Fix CSI SCLK clock name

[Paul Kocialkowski]

The CSI SCLK clock is incorrectly called CSI1 SCLK while it is used for
both the CSI0 and CSI1 interfaces and is called CSI SCLK all around the
documentation.

Fix the name in the driver, header and device-tree.

Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
---
 .../bindings/media/allwinner,sun6i-a31-csi.yaml        |  2 +-
 .../bindings/media/allwinner,sun6i-a31-isp.yaml        |  2 +-
 .../bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml  |  2 +-
 arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi             |  2 +-
 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c                   | 10 +++++-----
 include/dt-bindings/clock/sun8i-v3s-ccu.h              |  2 +-
 6 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
index b3d6db922693..1aa5775ba2bc 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
@@ -110,7 +110,7 @@ examples:
         reg = <0x01cb4000 0x1000>;
         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
         clocks = <&ccu CLK_BUS_CSI>,
-                 <&ccu CLK_CSI1_SCLK>,
+                 <&ccu CLK_CSI_SCLK>,
                  <&ccu CLK_DRAM_CSI>;
         clock-names = "bus",
                       "mod",
diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml
index a61a76bb611c..3ea4a4290f23 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml
@@ -79,7 +79,7 @@ examples:
         reg = <0x01cb8000 0x1000>;
         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
         clocks = <&ccu CLK_BUS_CSI>,
-             <&ccu CLK_CSI1_SCLK>,
+             <&ccu CLK_CSI_SCLK>,
              <&ccu CLK_DRAM_CSI>;
         clock-names = "bus", "mod", "ram";
         resets = <&ccu RST_BUS_CSI>;
diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
index 54e15ab8a7f5..627b28e94354 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
@@ -103,7 +103,7 @@ examples:
         reg = <0x01cb1000 0x1000>;
         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
         clocks = <&ccu CLK_BUS_CSI>,
-                 <&ccu CLK_CSI1_SCLK>;
+                 <&ccu CLK_CSI_SCLK>;
         clock-names = "bus", "mod";
         resets = <&ccu RST_BUS_CSI>;
 
diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
index f909b1d4dbca..e82cf312da25 100644
--- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
@@ -652,7 +652,7 @@ csi1: camera@1cb4000 {
 			reg = <0x01cb4000 0x3000>;
 			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_CSI>,
-				 <&ccu CLK_CSI1_SCLK>,
+				 <&ccu CLK_CSI_SCLK>,
 				 <&ccu CLK_DRAM_CSI>;
 			clock-names = "bus", "mod", "ram";
 			resets = <&ccu RST_BUS_CSI>;
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index 579a81bb46df..d12791b31a9d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -362,8 +362,8 @@ static const char * const csi_mclk_parents[] = { "osc24M", "pll-video",
 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
 				 0x130, 0, 5, 8, 3, BIT(15), 0);
 
-static const char * const csi1_sclk_parents[] = { "pll-video", "pll-isp" };
-static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk", csi1_sclk_parents,
+static const char * const csi_sclk_parents[] = { "pll-video", "pll-isp" };
+static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
 				 0x134, 16, 4, 24, 3, BIT(31), 0);
 
 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk", csi_mclk_parents,
@@ -452,7 +452,7 @@ static struct ccu_common *sun8i_v3s_ccu_clks[] = {
 	&tcon_clk.common,
 	&csi_misc_clk.common,
 	&csi0_mclk_clk.common,
-	&csi1_sclk_clk.common,
+	&csi_sclk_clk.common,
 	&csi1_mclk_clk.common,
 	&ve_clk.common,
 	&ac_dig_clk.common,
@@ -551,7 +551,7 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
 		[CLK_TCON0]		= &tcon_clk.common.hw,
 		[CLK_CSI_MISC]		= &csi_misc_clk.common.hw,
 		[CLK_CSI0_MCLK]		= &csi0_mclk_clk.common.hw,
-		[CLK_CSI1_SCLK]		= &csi1_sclk_clk.common.hw,
+		[CLK_CSI_SCLK]		= &csi_sclk_clk.common.hw,
 		[CLK_CSI1_MCLK]		= &csi1_mclk_clk.common.hw,
 		[CLK_VE]		= &ve_clk.common.hw,
 		[CLK_AC_DIG]		= &ac_dig_clk.common.hw,
@@ -633,7 +633,7 @@ static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
 		[CLK_TCON0]		= &tcon_clk.common.hw,
 		[CLK_CSI_MISC]		= &csi_misc_clk.common.hw,
 		[CLK_CSI0_MCLK]		= &csi0_mclk_clk.common.hw,
-		[CLK_CSI1_SCLK]		= &csi1_sclk_clk.common.hw,
+		[CLK_CSI_SCLK]		= &csi_sclk_clk.common.hw,
 		[CLK_CSI1_MCLK]		= &csi1_mclk_clk.common.hw,
 		[CLK_VE]		= &ve_clk.common.hw,
 		[CLK_AC_DIG]		= &ac_dig_clk.common.hw,
diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h
index 014ac6123d17..c4055629c9f9 100644
--- a/include/dt-bindings/clock/sun8i-v3s-ccu.h
+++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h
@@ -96,7 +96,7 @@
 #define CLK_TCON0		64
 #define CLK_CSI_MISC		65
 #define CLK_CSI0_MCLK		66
-#define CLK_CSI1_SCLK		67
+#define CLK_CSI_SCLK		67
 #define CLK_CSI1_MCLK		68
 #define CLK_VE			69
 #define CLK_AC_DIG		70
-- 
2.49.0

Re: [PATCH 2/5] clk: sunxi-ng: v3s: Fix CSI SCLK clock name

[Icenowy Zheng]

在 2025-07-01星期二的 22:11 +0200，Paul Kocialkowski写道：
> The CSI SCLK clock is incorrectly called CSI1 SCLK while it is used
> for
> both the CSI0 and CSI1 interfaces and is called CSI SCLK all around
> the
> documentation.
> 
> Fix the name in the driver, header and device-tree.
> 
> Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> ---
>  .../bindings/media/allwinner,sun6i-a31-csi.yaml        |  2 +-
>  .../bindings/media/allwinner,sun6i-a31-isp.yaml        |  2 +-
>  .../bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml  |  2 +-
>  arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi             |  2 +-
>  drivers/clk/sunxi-ng/ccu-sun8i-v3s.c                   | 10 +++++---
> --
>  include/dt-bindings/clock/sun8i-v3s-ccu.h              |  2 +-
>  6 files changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-
> a31-csi.yaml
> b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-
> csi.yaml
> index b3d6db922693..1aa5775ba2bc 100644
> --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-
> csi.yaml
> +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-
> csi.yaml
> @@ -110,7 +110,7 @@ examples:
>          reg = <0x01cb4000 0x1000>;
>          interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
>          clocks = <&ccu CLK_BUS_CSI>,
> -                 <&ccu CLK_CSI1_SCLK>,
> +                 <&ccu CLK_CSI_SCLK>,
>                   <&ccu CLK_DRAM_CSI>;
>          clock-names = "bus",
>                        "mod",
> diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-
> a31-isp.yaml
> b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-
> isp.yaml
> index a61a76bb611c..3ea4a4290f23 100644
> --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-
> isp.yaml
> +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-
> isp.yaml
> @@ -79,7 +79,7 @@ examples:
>          reg = <0x01cb8000 0x1000>;
>          interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>          clocks = <&ccu CLK_BUS_CSI>,
> -             <&ccu CLK_CSI1_SCLK>,
> +             <&ccu CLK_CSI_SCLK>,
>               <&ccu CLK_DRAM_CSI>;
>          clock-names = "bus", "mod", "ram";
>          resets = <&ccu RST_BUS_CSI>;
> diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-
> a31-mipi-csi2.yaml
> b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-
> csi2.yaml
> index 54e15ab8a7f5..627b28e94354 100644
> --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-
> mipi-csi2.yaml
> +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-
> mipi-csi2.yaml
> @@ -103,7 +103,7 @@ examples:
>          reg = <0x01cb1000 0x1000>;
>          interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
>          clocks = <&ccu CLK_BUS_CSI>,
> -                 <&ccu CLK_CSI1_SCLK>;
> +                 <&ccu CLK_CSI_SCLK>;
>          clock-names = "bus", "mod";
>          resets = <&ccu RST_BUS_CSI>;
>  
> diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> index f909b1d4dbca..e82cf312da25 100644
> --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> @@ -652,7 +652,7 @@ csi1: camera@1cb4000 {
>                         reg = <0x01cb4000 0x3000>;
>                         interrupts = <GIC_SPI 84
> IRQ_TYPE_LEVEL_HIGH>;
>                         clocks = <&ccu CLK_BUS_CSI>,
> -                                <&ccu CLK_CSI1_SCLK>,
> +                                <&ccu CLK_CSI_SCLK>,
>                                  <&ccu CLK_DRAM_CSI>;
>                         clock-names = "bus", "mod", "ram";
>                         resets = <&ccu RST_BUS_CSI>;
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> index 579a81bb46df..d12791b31a9d 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> @@ -362,8 +362,8 @@ static const char * const csi_mclk_parents[] = {
> "osc24M", "pll-video",
>  static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk",
> csi_mclk_parents,
>                                  0x130, 0, 5, 8, 3, BIT(15), 0);
>  
> -static const char * const csi1_sclk_parents[] = { "pll-video", "pll-
> isp" };
> -static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk",
> csi1_sclk_parents,
> +static const char * const csi_sclk_parents[] = { "pll-video", "pll-
> isp" };
> +static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk",
> csi_sclk_parents,

The document seems to call the gating bit "CSI_TOP_SCLK_GATING",
although the divider is "CSI_SCLK_DIV_M"; well at least the drop of 1
is desirable, so

Reviewed-By: Icenowy Zheng <uwu@icenowy.me>

P.S. This is the most weird clock register organization I have seen.

>                                  0x134, 16, 4, 24, 3, BIT(31), 0);
>  
>  static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk",
> csi_mclk_parents,
> @@ -452,7 +452,7 @@ static struct ccu_common *sun8i_v3s_ccu_clks[] =
> {
>         &tcon_clk.common,
>         &csi_misc_clk.common,
>         &csi0_mclk_clk.common,
> -       &csi1_sclk_clk.common,
> +       &csi_sclk_clk.common,
>         &csi1_mclk_clk.common,
>         &ve_clk.common,
>         &ac_dig_clk.common,
> @@ -551,7 +551,7 @@ static struct clk_hw_onecell_data
> sun8i_v3s_hw_clks = {
>                 [CLK_TCON0]             = &tcon_clk.common.hw,
>                 [CLK_CSI_MISC]          = &csi_misc_clk.common.hw,
>                 [CLK_CSI0_MCLK]         = &csi0_mclk_clk.common.hw,
> -               [CLK_CSI1_SCLK]         = &csi1_sclk_clk.common.hw,
> +               [CLK_CSI_SCLK]          = &csi_sclk_clk.common.hw,
>                 [CLK_CSI1_MCLK]         = &csi1_mclk_clk.common.hw,
>                 [CLK_VE]                = &ve_clk.common.hw,
>                 [CLK_AC_DIG]            = &ac_dig_clk.common.hw,
> @@ -633,7 +633,7 @@ static struct clk_hw_onecell_data
> sun8i_v3_hw_clks = {
>                 [CLK_TCON0]             = &tcon_clk.common.hw,
>                 [CLK_CSI_MISC]          = &csi_misc_clk.common.hw,
>                 [CLK_CSI0_MCLK]         = &csi0_mclk_clk.common.hw,
> -               [CLK_CSI1_SCLK]         = &csi1_sclk_clk.common.hw,
> +               [CLK_CSI_SCLK]          = &csi_sclk_clk.common.hw,
>                 [CLK_CSI1_MCLK]         = &csi1_mclk_clk.common.hw,
>                 [CLK_VE]                = &ve_clk.common.hw,
>                 [CLK_AC_DIG]            = &ac_dig_clk.common.hw,
> diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-
> bindings/clock/sun8i-v3s-ccu.h
> index 014ac6123d17..c4055629c9f9 100644
> --- a/include/dt-bindings/clock/sun8i-v3s-ccu.h
> +++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h
> @@ -96,7 +96,7 @@
>  #define CLK_TCON0              64
>  #define CLK_CSI_MISC           65
>  #define CLK_CSI0_MCLK          66
> -#define CLK_CSI1_SCLK          67
> +#define CLK_CSI_SCLK           67
>  #define CLK_CSI1_MCLK          68
>  #define CLK_VE                 69
>  #define CLK_AC_DIG             70

[PATCH 3/5] clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name

[Paul Kocialkowski]

The CSI1 MCLK clock is reported as "csi-mclk" while it is specific to
CSI1 as the name of the definition indicates. Fix it in the driver.

Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index d12791b31a9d..86d933d1ac72 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -366,7 +366,7 @@ static const char * const csi_sclk_parents[] = { "pll-video", "pll-isp" };
 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
 				 0x134, 16, 4, 24, 3, BIT(31), 0);
 
-static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk", csi_mclk_parents,
+static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents,
 				 0x134, 0, 5, 8, 3, BIT(15), 0);
 
 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
-- 
2.49.0

Re: [PATCH 3/5] clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name

[Icenowy Zheng]

在 2025-07-01星期二的 22:11 +0200，Paul Kocialkowski写道：
> The CSI1 MCLK clock is reported as "csi-mclk" while it is specific to
> CSI1 as the name of the definition indicates. Fix it in the driver.
> 
> Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> ---
>  drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> index d12791b31a9d..86d933d1ac72 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
> @@ -366,7 +366,7 @@ static const char * const csi_sclk_parents[] = {
> "pll-video", "pll-isp" };
>  static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk",
> csi_sclk_parents,
>                                  0x134, 16, 4, 24, 3, BIT(31), 0);
>  
> -static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk",
> csi_mclk_parents,
> +static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk",
> csi_mclk_parents,
>                                  0x134, 0, 5, 8, 3, BIT(15), 0);

Yes, there exists csi0-mclk.

Reviewed-By: Icenowy Zheng <uwu@icenowy.me>

>  
>  static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",

[PATCH 4/5] clk: sunxi-ng: v3s: Fix TCON clock parents

[Paul Kocialkowski]

The TCON clock can be parented to both the video PLL and the periph0 PLL.
Add the latter, which was missing from the list.

Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index 86d933d1ac72..52e4369664c5 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -350,7 +350,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
 				 0x104, 0, 4, 24, 2, BIT(31),
 				 CLK_SET_RATE_PARENT);
 
-static const char * const tcon_parents[] = { "pll-video" };
+static const char * const tcon_parents[] = { "pll-video", "pll-periph0" };
 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
 				 0x118, 0, 4, 24, 3, BIT(31), 0);
 
-- 
2.49.0

[PATCH 5/5] drm/sun4i: Run the mixer clock at 297 MHz on V3s

[Paul Kocialkowski]

The DE mixer clock is currently set to run at 150 MHz, while the
Allwinner BSP configures it at 300 MHz and other platforms typically
run at 297 MHz.

150 MHz appears to be enough given the restricted graphics capabilities
of the SoC (with a work area of only 1024x1024). However it typically
causes the DE clock to be parented to the periph0 pll instead of the
video PLL.

While this should generally not be a concern, it appears (based on
experimentation) that both the DE and TCON clocks need to be parented
to the same PLL for these units to work. While we cannot represent this
constraint in the clock driver, it appears that the TCON clock will
often get parented to the video pll (typically running at 297 MHz for
the CSI units needs), for instance when driving displays with a 33 MHz
pixel clock (33 being a natural divider of 297).

Running the DE clock at 297 MHz will typically result in parenting to
the video pll instead of the periph0 pll, thus making the display
output functional.

This is all a bit fragile but it solves the issue with displays running
at 33 Mhz and brings V3s to use the same frequency as other platforms,
making support more unified.

Also align and sort the fields of the v3s mixer config while at it.

Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
---
 drivers/gpu/drm/sun4i/sun8i_mixer.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 8b41d33baa30..35fdc2451060 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -670,12 +670,12 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
 };
 
 static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
-	.vi_num = 2,
-	.ui_num = 1,
-	.scaler_mask = 0x3,
-	.scanline_yuv = 2048,
-	.ccsc = CCSC_MIXER0_LAYOUT,
-	.mod_rate = 150000000,
+	.ccsc		= CCSC_MIXER0_LAYOUT,
+	.mod_rate	= 297000000,
+	.scaler_mask	= 0x3,
+	.scanline_yuv	= 2048,
+	.ui_num		= 1,
+	.vi_num		= 2,
 };
 
 static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = {
-- 
2.49.0

Re: [PATCH 5/5] drm/sun4i: Run the mixer clock at 297 MHz on V3s

[Icenowy Zheng]

在 2025-07-01星期二的 22:11 +0200，Paul Kocialkowski写道：
> The DE mixer clock is currently set to run at 150 MHz, while the
> Allwinner BSP configures it at 300 MHz and other platforms typically
> run at 297 MHz.
> 
> 150 MHz appears to be enough given the restricted graphics
> capabilities
> of the SoC (with a work area of only 1024x1024). However it typically
> causes the DE clock to be parented to the periph0 pll instead of the
> video PLL.
> 
> While this should generally not be a concern, it appears (based on
> experimentation) that both the DE and TCON clocks need to be parented
> to the same PLL for these units to work. While we cannot represent
> this
> constraint in the clock driver, it appears that the TCON clock will
> often get parented to the video pll (typically running at 297 MHz for

Ah I think pixel clocks are arbitary and nothing could be predicted
about it...

> the CSI units needs), for instance when driving displays with a 33
> MHz
> pixel clock (33 being a natural divider of 297).
> 
> Running the DE clock at 297 MHz will typically result in parenting to
> the video pll instead of the periph0 pll, thus making the display
> output functional.
> 
> This is all a bit fragile but it solves the issue with displays
> running
> at 33 Mhz and brings V3s to use the same frequency as other
> platforms,
> making support more unified.
> 
> Also align and sort the fields of the v3s mixer config while at it.
> 
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> ---
>  drivers/gpu/drm/sun4i/sun8i_mixer.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
> b/drivers/gpu/drm/sun4i/sun8i_mixer.c
> index 8b41d33baa30..35fdc2451060 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
> @@ -670,12 +670,12 @@ static const struct sun8i_mixer_cfg
> sun8i_r40_mixer1_cfg = {
>  };
>  
>  static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
> -       .vi_num = 2,
> -       .ui_num = 1,
> -       .scaler_mask = 0x3,
> -       .scanline_yuv = 2048,
> -       .ccsc = CCSC_MIXER0_LAYOUT,
> -       .mod_rate = 150000000,
> +       .ccsc           = CCSC_MIXER0_LAYOUT,
> +       .mod_rate       = 297000000,
> +       .scaler_mask    = 0x3,
> +       .scanline_yuv   = 2048,
> +       .ui_num         = 1,
> +       .vi_num         = 2,
>  };
>  
>  static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = {

Re: [PATCH 5/5] drm/sun4i: Run the mixer clock at 297 MHz on V3s

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1702 bytes --]

On Tue, Jul 01, 2025 at 10:11:24PM +0200, Paul Kocialkowski wrote:
> The DE mixer clock is currently set to run at 150 MHz, while the
> Allwinner BSP configures it at 300 MHz and other platforms typically
> run at 297 MHz.
> 
> 150 MHz appears to be enough given the restricted graphics capabilities
> of the SoC (with a work area of only 1024x1024). However it typically
> causes the DE clock to be parented to the periph0 pll instead of the
> video PLL.
> 
> While this should generally not be a concern, it appears (based on
> experimentation) that both the DE and TCON clocks need to be parented
> to the same PLL for these units to work. While we cannot represent this
> constraint in the clock driver, it appears that the TCON clock will
> often get parented to the video pll (typically running at 297 MHz for
> the CSI units needs), for instance when driving displays with a 33 MHz
> pixel clock (33 being a natural divider of 297).
> 
> Running the DE clock at 297 MHz will typically result in parenting to
> the video pll instead of the periph0 pll, thus making the display
> output functional.
> 
> This is all a bit fragile but it solves the issue with displays running
> at 33 Mhz and brings V3s to use the same frequency as other platforms,
> making support more unified.

It's beyond fragile, and doesn't have anything to do with the DRM driver.

You should set up the clock tree properly in the clock driver, and then
add NO_REPARENT to the DE clock to make sure it stays that way.

And then, you can change the clock rate if you want to, but at least you
don't set a rate and hope that the side effects work your way, and won't
happen again.

Maxime

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Re: [PATCH 5/5] drm/sun4i: Run the mixer clock at 297 MHz on V3s

[Paul Kocialkowski]

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Hi Maxime,

Le Wed 02 Jul 25, 13:36, Maxime Ripard a écrit :
> On Tue, Jul 01, 2025 at 10:11:24PM +0200, Paul Kocialkowski wrote:
> > The DE mixer clock is currently set to run at 150 MHz, while the
> > Allwinner BSP configures it at 300 MHz and other platforms typically
> > run at 297 MHz.
> > 
> > 150 MHz appears to be enough given the restricted graphics capabilities
> > of the SoC (with a work area of only 1024x1024). However it typically
> > causes the DE clock to be parented to the periph0 pll instead of the
> > video PLL.
> > 
> > While this should generally not be a concern, it appears (based on
> > experimentation) that both the DE and TCON clocks need to be parented
> > to the same PLL for these units to work. While we cannot represent this
> > constraint in the clock driver, it appears that the TCON clock will
> > often get parented to the video pll (typically running at 297 MHz for
> > the CSI units needs), for instance when driving displays with a 33 MHz
> > pixel clock (33 being a natural divider of 297).
> > 
> > Running the DE clock at 297 MHz will typically result in parenting to
> > the video pll instead of the periph0 pll, thus making the display
> > output functional.
> > 
> > This is all a bit fragile but it solves the issue with displays running
> > at 33 Mhz and brings V3s to use the same frequency as other platforms,
> > making support more unified.
> 
> It's beyond fragile, and doesn't have anything to do with the DRM driver.
> 
> You should set up the clock tree properly in the clock driver, and then
> add NO_REPARENT to the DE clock to make sure it stays that way.

Thanks for the suggestion! I wasn't aware there was a flag to avoid
reparenting, sounds like the most reasonable way to solve this issue then.

I'll send another iteration reworking the clock tree then.

> And then, you can change the clock rate if you want to, but at least you
> don't set a rate and hope that the side effects work your way, and won't
> happen again.

We might as well still change it. To be honest I don't really see why it was
set to 150 MHz in the first place.

Cheers,

Paul

-- 
Paul Kocialkowski,

Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/

Expert in multimedia, graphics and embedded hardware support with Linux.

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Re: (subset) [PATCH 0/5] sunxi: Various minor V3s clock/pinctrl fixes

[Chen-Yu Tsai]

On Tue, 01 Jul 2025 22:11:19 +0200, Paul Kocialkowski wrote:
> This is a mixed-bag of minor fixes for V3s clocks and pinctrl.
> 
> The last patch is a weak attempt at accomodating using both the display
> engine and tcon along with the camera subsystem. The main issue is that
> the tcon and de need to have the same clock parent, which may not be
> the case depending on the pixel rate. Bringing the de block to the same
> clock rate as the csi block helps in some cases.
> 
> [...]

Applied to sunxi/clk-fixes-for-6.16 in local tree, thanks!

[2/5] clk: sunxi-ng: v3s: Fix CSI SCLK clock name
      commit: f45b2949b1a235881255132a119b8cc8c3738bd5
[3/5] clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name
      commit: 2b73328629396d32e41ca1f023653b07abf2b42f
[4/5] clk: sunxi-ng: v3s: Fix TCON clock parents
      commit: 01fdcbc7e5a56c9cba521e0f237cb5c3fd162432

Best regards,
-- 
Chen-Yu Tsai <wens@csie.org>