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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
	dri-devel@lists.freedesktop.org
Cc: chaitanya.kumar.borah@intel.com, ville.syrjala@linux.intel.com,
	pekka.paalanen@collabora.com, contact@emersion.fr,
	harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
	sebastian.wick@redhat.com, shashank.sharma@amd.com,
	swati2.sharma@intel.com, alex.hung@amd.com,
	Uma Shankar <uma.shankar@intel.com>
Subject: [v5 23/24] drm/i915/color: Create color pipeline with multisegmented LUT
Date: Wed,  2 Jul 2025 14:49:35 +0530	[thread overview]
Message-ID: <20250702091936.3004854-24-uma.shankar@intel.com> (raw)
In-Reply-To: <20250702091936.3004854-1-uma.shankar@intel.com>

From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

Add a color pipeline with three colorops in the sequence

	1D LUT MULTSEG - CTM - 1D LUT MULTSEG

This pipeline can be used to do any color space conversion or HDR
tone mapping

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 185 +++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_color.h |   1 +
 2 files changed, 186 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 689bc4f4ce25..cf2e1e3653b2 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -4311,6 +4311,139 @@ static const struct intel_color_funcs ilk_color_funcs = {
 	.get_config = ilk_get_config,
 };
 
+static const struct drm_color_lut_range xelpd_degamma_hdr[] = {
+	/* segment 1 */
+	{
+		.flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+			  DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+		.count = 128,
+		.start = 0, .end = (1 << 24) - 1,
+		.norm_factor = (1 << 24),
+		.precision = {
+			.intp = 0,
+			.fracp = 24,
+		},
+	},
+	/* segment 2 */
+	{
+		.flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+			  DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+		.count = 1,
+		.start = (1 << 24), .end = (1 << 24),
+		.norm_factor = (1 << 24),
+		.precision = {
+			.intp = 3,
+			.fracp = 24,
+		},
+	},
+	/* Segment 3 */
+	{
+		.flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+			  DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+		.count = 1,
+		.start = 3 * (1 << 24), .end = 3 * (1 << 24),
+		.norm_factor = (1 << 24),
+		.precision = {
+			.intp = 3,
+			.fracp = 24,
+		},
+	},
+	/* Segment 4 */
+	{
+		.flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+			  DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+		.count = 1,
+		.start = 7 * (1 << 24), .end = 7 * (1 << 24),
+		.norm_factor = (1 << 24),
+		.precision = {
+			.intp = 3,
+			.fracp = 24,
+		},
+	}
+};
+
+/* FIXME input bpc? */
+static const struct drm_color_lut_range xelpd_gamma_hdr[] = {
+	/* segment 1 */
+	{
+		.flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+			  DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+		.count = 9,
+		.start = 0, .end = 8,
+		.norm_factor = 8 * 32,
+		.precision = {
+			.intp = 0,
+			.fracp = 24,
+		},
+	},
+	/* segment 2 */
+	{
+		.flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+			  DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+		.count = 30,
+		.start = 8 * 2, .end = 8 * (32 - 1),
+		.norm_factor = 8 * 32,
+		.precision = {
+			.intp = 0,
+			.fracp = 24,
+		},
+	},
+	/* segment 3 */
+	{
+		.flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+			  DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+		.count = 1,
+		.start = 8 * 32, .end = 8 * 32,
+		.norm_factor = 8 * 32,
+		.precision = {
+			.intp = 3,
+			.fracp = 24,
+		},
+	},
+	/* segment 4 */
+	{
+		.flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+			  DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+		.count = 1,
+		.start = 3 * 8 * 32, .end = 3 * 8 * 32,
+		.norm_factor = 8 * 32,
+		.precision = {
+			.intp = 3,
+			.fracp = 24,
+		},
+	},
+	/* segment 5 */
+	{
+		.flags = (DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE |
+			  DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL |
+			  DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING),
+		.count = 1,
+		.start = 7 * 8 * 32, .end = 7 * 8 * 32,
+		.norm_factor = 8 * 32,
+		.precision = {
+			.intp = 3,
+			.fracp = 24,
+		},
+	},
+};
+
 /* TODO: Move to another file */
 static void
 intel_color_load_plane_csc_matrix(struct intel_dsb *dsb,
@@ -4424,6 +4557,52 @@ int intel_plane_tf_pipeline_init(struct drm_plane *plane, struct drm_prop_enum_l
 	return 0;
 }
 
+int intel_plane_tf_multseg_pipeline_init(struct drm_plane *plane, struct drm_prop_enum_list *list)
+{
+	struct intel_plane_colorop *colorop;
+	struct drm_device *dev = plane->dev;
+	int ret;
+	struct drm_colorop *prev_op;
+
+	colorop = intel_plane_colorop_create(CB_PLANE_PRE_CSC_LUT);
+
+	ret = drm_plane_colorop_curve_1d_lut_multseg_init(dev, &colorop->base,
+							  plane, xelpd_degamma_hdr,
+							  sizeof(xelpd_degamma_hdr),
+							  DRM_COLOROP_FLAG_ALLOW_BYPASS);
+	if (ret)
+		return ret;
+
+	list->type = colorop->base.base.id;
+	list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", colorop->base.base.id);
+
+	/* TODO: handle failures and clean up*/
+	prev_op = &colorop->base;
+
+	colorop = intel_plane_colorop_create(CB_PLANE_CSC);
+
+	ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
+					     DRM_COLOROP_FLAG_ALLOW_BYPASS);
+	if (ret)
+		return ret;
+
+	drm_colorop_set_next_property(prev_op, &colorop->base);
+
+	prev_op = &colorop->base;
+
+	colorop = intel_plane_colorop_create(CB_PLANE_POST_CSC_LUT);
+	ret = drm_plane_colorop_curve_1d_lut_multseg_init(dev, &colorop->base,
+							  plane, xelpd_gamma_hdr,
+							  sizeof(xelpd_gamma_hdr),
+							  DRM_COLOROP_FLAG_ALLOW_BYPASS);
+	if (ret)
+		return ret;
+
+	drm_colorop_set_next_property(prev_op, &colorop->base);
+
+	return 0;
+}
+
 int intel_plane_color_init(struct drm_plane *plane)
 {
 	struct drm_device *dev = plane->dev;
@@ -4448,6 +4627,12 @@ int intel_plane_color_init(struct drm_plane *plane)
 		return ret;
 	len++;
 
+	/* Create Pipeline with Multi-segmented LUT */
+	ret = intel_plane_tf_multseg_pipeline_init(plane, &pipelines[len]);
+	if (ret)
+		return ret;
+	len++;
+
 	/* Create COLOR_PIPELINE property and attach */
 	prop = drm_property_create_enum(dev, DRM_MODE_PROP_ATOMIC,
 					"COLOR_PIPELINE",
diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h
index 420d596dbbae..1808b64a6903 100644
--- a/drivers/gpu/drm/i915/display/intel_color.h
+++ b/drivers/gpu/drm/i915/display/intel_color.h
@@ -52,4 +52,5 @@ int intel_plane_tf_pipeline_init(struct drm_plane *plane, struct drm_prop_enum_l
 int intel_plane_color_init(struct drm_plane *plane);
 void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
 					const struct intel_plane_state *plane_state);
+int intel_plane_tf_multseg_pipeline_init(struct drm_plane *plane, struct drm_prop_enum_list *list);
 #endif /* __INTEL_COLOR_H__ */
-- 
2.42.0


  parent reply	other threads:[~2025-07-02  9:09 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-02  9:19 [v5 00/24] Plane Color Pipeline support for Intel platforms Uma Shankar
2025-07-02  9:19 ` [v5 01/24] [NOT FOR REVIEW] drm: AMD series squashed Uma Shankar
2025-07-02  9:19 ` [v5 02/24] drm: Add Color lut range attributes Uma Shankar
2025-10-23  5:25   ` Kandpal, Suraj
2025-07-02  9:19 ` [v5 03/24] drm: Add Color ops capability property Uma Shankar
2025-10-28  5:31   ` Kandpal, Suraj
2025-07-02  9:19 ` [v5 04/24] drm: Add 1D LUT multi-segmented color op Uma Shankar
2025-10-23  8:11   ` Kandpal, Suraj
2025-07-02  9:19 ` [v5 05/24] drm: Define helper to initialize segmented 1D LUT Uma Shankar
2025-10-23  8:27   ` Kandpal, Suraj
2025-07-02  9:19 ` [v5 06/24] drm: Add helper to extract lut from struct drm_color_lut_32 Uma Shankar
2025-10-24  4:29   ` Kandpal, Suraj
2025-07-02  9:19 ` [v5 07/24] drm/i915: Add identifiers for intel color blocks Uma Shankar
2025-07-04 12:35   ` Jani Nikula
2025-10-23  6:04   ` Kandpal, Suraj
2025-07-02  9:19 ` [v5 08/24] drm/i915: Add intel_color_op Uma Shankar
2025-07-04 12:36   ` Jani Nikula
2025-11-05 12:24     ` Borah, Chaitanya Kumar
2025-07-02  9:19 ` [v5 09/24] drm/i915/color: Add helper to create intel colorop Uma Shankar
2025-07-04 12:37   ` Jani Nikula
2025-10-27  9:38   ` Kandpal, Suraj
2025-07-02  9:19 ` [v5 10/24] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2025-07-04 12:39   ` Jani Nikula
2025-10-28  4:59   ` Kandpal, Suraj
2025-07-02  9:19 ` [v5 11/24] drm/i915/color: Add and attach COLORPIPELINE plane property Uma Shankar
2025-07-04 12:41   ` Jani Nikula
2025-10-28  5:13   ` Kandpal, Suraj
2025-11-05 12:25     ` Borah, Chaitanya Kumar
2025-07-02  9:19 ` [v5 12/24] drm/i915/color: Add framework to program CSC Uma Shankar
2025-10-28  8:09   ` Kandpal, Suraj
2025-10-28  8:12     ` Kandpal, Suraj
2025-11-05 12:25       ` Borah, Chaitanya Kumar
2025-11-05 12:25     ` Borah, Chaitanya Kumar
2025-07-02  9:19 ` [v5 13/24] drm/i915/color: Add callbacks to set plane CTM Uma Shankar
2025-07-04 12:42   ` Jani Nikula
2025-07-02  9:19 ` [v5 14/24] drm/i915/color: Add new color callbacks for Xelpd Uma Shankar
2025-07-02  9:19 ` [v5 15/24] drm/i915/color: Preserve sign bit when int_bits is Zero Uma Shankar
2025-07-02  9:19 ` [v5 16/24] drm/i915/color: Add plane CTM callback for D13 and beyond Uma Shankar
2025-10-28  8:16   ` Kandpal, Suraj
2025-07-02  9:19 ` [v5 17/24] drm/i915: Add register definitions for Plane Degamma Uma Shankar
2025-10-23  6:22   ` Kandpal, Suraj
2025-07-02  9:19 ` [v5 18/24] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
2025-07-02  9:19 ` [v5 19/24] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2025-10-23  6:25   ` Kandpal, Suraj
2025-07-02  9:19 ` [v5 20/24] drm/i915/color: Program Pre-CSC registers Uma Shankar
2025-10-23  6:28   ` Kandpal, Suraj
2025-11-05 12:26     ` Borah, Chaitanya Kumar
2025-10-28  8:25   ` Kandpal, Suraj
2025-07-02  9:19 ` [v5 21/24] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2025-10-28  8:29   ` Kandpal, Suraj
2025-07-02  9:19 ` [v5 22/24] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2025-07-02  9:19 ` Uma Shankar [this message]
2025-10-28  8:31   ` [v5 23/24] drm/i915/color: Create color pipeline with multisegmented LUT Kandpal, Suraj
2025-07-02  9:19 ` [v5 24/24] drm/doc/rfc: Add documentation for multi-segmented 1D LUT Uma Shankar

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