From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BFE7CA0EE6 for ; Tue, 19 Aug 2025 20:30:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D164910E668; Tue, 19 Aug 2025 20:30:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="evk13QPM"; dkim-atps=neutral Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4F88B10E21B for ; Tue, 19 Aug 2025 20:30:10 +0000 (UTC) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 21B3A5C5BD5; Tue, 19 Aug 2025 20:30:09 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8E42CC4CEF1; Tue, 19 Aug 2025 20:30:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755635408; bh=ZR2C8Q08ABDZQ88UJtSosGwmMAl53VIxN5VzyU/juXw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=evk13QPMGD+oT9KokhawGFp/+Z/Fucf/SyvYEV+8YhumHAA2weEBBUVoDt5tAdcvM nVR88XBOqLRsTVhXJeEwhZf5F376YoLKPmmGxTY+XL2Yo1L2XZYgaOlIJVEkXJ42Qt 3uNLB/DiIZgCXR+zTJY+R68PcSkExfyNNdZdV798hpROEhq3Q5l085149ns0eHc8Tj ambGWSAuR6X9ytxpfCBxxh8wDfwgIgb348eqoWqJ0CHjsnuxmmQjqOityJJVWfyVEk jqOYh6XPR1hxOVJAiAPHOM8mvB+cm/KO/KGtKxAWaTxEGK2GUmYm6KeD1iX8mUGzcH FaVJSYdn2jGsQ== Date: Tue, 19 Aug 2025 15:30:07 -0500 From: Rob Herring To: Svyatoslav Ryhel Cc: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Dmitry Osipenko , Charan Pedumuru , linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: Re: [PATCH v1 17/19] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI Message-ID: <20250819203007.GA1266319-robh@kernel.org> References: <20250819121631.84280-1-clamor95@gmail.com> <20250819121631.84280-18-clamor95@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250819121631.84280-18-clamor95@gmail.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Tue, Aug 19, 2025 at 03:16:29PM +0300, Svyatoslav Ryhel wrote: > Document CSI hw block found in Tegra20 and Tegra30 SoC. > > Signed-off-by: Svyatoslav Ryhel > --- > .../display/tegra/nvidia,tegra210-csi.yaml | 78 +++++++++++++++---- > 1 file changed, 63 insertions(+), 15 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml > index fa07a40d1004..a5669447a33b 100644 > --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml > @@ -16,30 +16,78 @@ properties: > > compatible: > enum: > + - nvidia,tegra20-csi > + - nvidia,tegra30-csi > - nvidia,tegra210-csi > > reg: > maxItems: 1 > > - clocks: > - items: > - - description: module clock > - - description: A/B lanes clock > - - description: C/D lanes clock > - - description: E lane clock > - - description: test pattern generator clock > - > - clock-names: > - items: > - - const: csi > - - const: cilab > - - const: cilcd > - - const: cile > - - const: csi_tpg > + clocks: true > + clock-names: true > > power-domains: > maxItems: 1 > > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - nvidia,tegra20-csi > + then: > + properties: > + clocks: > + items: > + - description: module clock > + > + clock-names: > + items: > + - const: csi > + - if: > + properties: > + compatible: > + contains: > + enum: > + - nvidia,tegra30-csi > + then: > + properties: > + clocks: > + items: > + - description: module clock > + - description: PAD A clock > + - description: PAD B clock > + > + clock-names: > + items: > + - const: csi > + - const: csia_pad > + - const: csib_pad > + - if: > + properties: > + compatible: > + contains: > + enum: > + - nvidia,tegra210-csi > + then: > + properties: > + clocks: > + items: > + - description: module clock > + - description: A/B lanes clock > + - description: C/D lanes clock > + - description: E lane clock > + - description: test pattern generator clock > + > + clock-names: > + items: > + - const: csi > + - const: cilab > + - const: cilcd > + - const: cile > + - const: csi_tpg > + This is longer that what's the same. I think this should be a separate schema doc. Rob