From: Maxime Ripard <mripard@kernel.org>
To: Jyri Sarha <jyri.sarha@iki.fi>,
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>,
Simona Vetter <simona@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Maxime Ripard <mripard@kernel.org>
Subject: [PATCH v2 03/14] drm/tidss: dispc: Switch to GENMASK instead of FLD_MASK
Date: Wed, 20 Aug 2025 16:01:43 +0200 [thread overview]
Message-ID: <20250820-drm-tidss-field-api-v2-3-43cab671c648@kernel.org> (raw)
In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org>
The dispc FLD_MASK function is an exact equivalent of the GENMASK macro.
Let's convert the dispc driver to the latter.
Signed-off-by: Maxime Ripard <mripard@kernel.org>
---
drivers/gpu/drm/tidss/tidss_dispc.c | 13 +++----------
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index 10fbc99621c149f4e119ef4a45867c369ca5df0b..929c9e3ac1174df68937afd86f13bda4e3a66394 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -607,35 +607,28 @@ void tidss_disable_oldi(struct tidss_device *tidss, u32 hw_videoport)
/*
* TRM gives bitfields as start:end, where start is the higher bit
* number. For example 7:0
*/
-#define FLD_MASK(start, end) \
- ({ \
- int _end_inner = (end); \
- u32 _mask = ((1 << ((start) - _end_inner + 1)) - 1) << _end_inner; \
- _mask; \
- })
-
#define FLD_VAL(val, start, end) \
({ \
int _end_inner = (end); \
- u32 _new_val = ((val) << _end_inner) & FLD_MASK((start), _end_inner); \
+ u32 _new_val = ((val) << _end_inner) & GENMASK((start), _end_inner); \
_new_val; \
})
#define FLD_GET(val, start, end) \
({ \
int _end = (end); \
- u32 _ret_val = ((val) & FLD_MASK((start), _end)) >> _end; \
+ u32 _ret_val = ((val) & GENMASK((start), _end)) >> _end; \
_ret_val; \
})
#define FLD_MOD(orig, val, start, end) \
({ \
int _start = (start), _end = (end); \
- u32 _masked_val = (orig) & ~FLD_MASK(_start, _end); \
+ u32 _masked_val = (orig) & ~GENMASK(_start, _end); \
u32 _new_val = _masked_val | FLD_VAL((val), _start, _end); \
_new_val; \
})
#define REG_GET(dispc, idx, start, end) \
--
2.50.1
next prev parent reply other threads:[~2025-08-20 14:02 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-20 14:01 [PATCH v2 00/14] drm/tidss: dispc: Convert to FIELD_* API Maxime Ripard
2025-08-20 14:01 ` [PATCH v2 01/14] drm/tidss: dispc: Remove unused OVR_REG_GET Maxime Ripard
2025-08-20 14:01 ` [PATCH v2 02/14] drm/tidss: dispc: Convert accessors to macros Maxime Ripard
2025-08-20 14:01 ` Maxime Ripard [this message]
2025-08-20 14:01 ` [PATCH v2 04/14] drm/tidss: dispc: Get rid of FLD_VAL Maxime Ripard
2025-08-20 14:01 ` [PATCH v2 05/14] drm/tidss: dispc: Get rid of FLD_GET Maxime Ripard
2025-08-20 14:01 ` [PATCH v2 06/14] drm/tidss: dispc: Get rid of FLD_MOD Maxime Ripard
2025-08-21 15:19 ` kernel test robot
2025-08-20 14:01 ` [PATCH v2 07/14] drm/tidss: dispc: Switch REG_GET to using a mask Maxime Ripard
2025-08-20 14:01 ` [PATCH v2 08/14] drm/tidss: dispc: Switch REG_FLD_MOD " Maxime Ripard
2025-08-20 14:01 ` [PATCH v2 09/14] drm/tidss: dispc: Switch VID_REG_GET " Maxime Ripard
2025-08-20 14:01 ` [PATCH v2 10/14] drm/tidss: dispc: Switch VID_REG_FLD_MOD " Maxime Ripard
2025-08-20 14:01 ` [PATCH v2 11/14] drm/tidss: dispc: Switch VP_REG_GET " Maxime Ripard
2025-08-20 14:01 ` [PATCH v2 12/14] drm/tidss: dispc: Switch VP_REG_FLD_MOD " Maxime Ripard
2025-08-20 14:01 ` [PATCH v2 13/14] drm/tidss: dispc: Switch OVR_REG_FLD_MOD " Maxime Ripard
2025-08-20 14:01 ` [PATCH v2 14/14] drm/tidss: dispc: Define field masks being used Maxime Ripard
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