From: Rob Herring <robh@kernel.org>
To: Svyatoslav Ryhel <clamor95@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>,
Thierry Reding <treding@nvidia.com>,
Mikko Perttunen <mperttunen@nvidia.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Sowjanya Komatineni <skomatineni@nvidia.com>,
Luca Ceresoli <luca.ceresoli@bootlin.com>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Dmitry Osipenko <digetx@gmail.com>,
Charan Pedumuru <charan.pedumuru@gmail.com>,
linux-media@vger.kernel.org, linux-tegra@vger.kernel.org,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-staging@lists.linux.dev
Subject: Re: [PATCH v1 02/19] dt-bindings: clock: tegra20: Add IDs for CSI PAD clocks
Date: Fri, 22 Aug 2025 08:59:46 -0500 [thread overview]
Message-ID: <20250822135946.GA3492270-robh@kernel.org> (raw)
In-Reply-To: <20250819121631.84280-3-clamor95@gmail.com>
On Tue, Aug 19, 2025 at 03:16:14PM +0300, Svyatoslav Ryhel wrote:
> Tegra30 has CSI PAD clock enable bits embedded into PLLD/PLLD2 registers.
> Add ids for these clocks.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
> include/dt-bindings/clock/tegra30-car.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
> index f193663e6f28..14b83e90a0fc 100644
> --- a/include/dt-bindings/clock/tegra30-car.h
> +++ b/include/dt-bindings/clock/tegra30-car.h
> @@ -271,6 +271,8 @@
> #define TEGRA30_CLK_AUDIO3_MUX 306
> #define TEGRA30_CLK_AUDIO4_MUX 307
> #define TEGRA30_CLK_SPDIF_MUX 308
> -#define TEGRA30_CLK_CLK_MAX 309
> +#define TEGRA30_CLK_CSIA_PAD 309
> +#define TEGRA30_CLK_CSIB_PAD 310
> +#define TEGRA30_CLK_CLK_MAX 311
Please drop the MAX. This header is ABI and if a define can change, then
it's not ABI.
Rob
next prev parent reply other threads:[~2025-08-22 13:59 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-19 12:16 [PATCH v1 00/19] tegra-video: add CSI support for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 01/19] clk: tegra: init CSUS clock " Svyatoslav Ryhel
2025-08-27 4:09 ` Mikko Perttunen
2025-08-27 4:32 ` Svyatoslav
2025-08-27 10:36 ` Mikko Perttunen
2025-08-27 10:45 ` Svyatoslav Ryhel
2025-08-28 8:13 ` Mikko Perttunen
2025-08-28 8:28 ` Svyatoslav Ryhel
2025-08-28 10:15 ` Mikko Perttunen
2025-08-28 10:23 ` Svyatoslav Ryhel
2025-08-29 0:29 ` Mikko Perttunen
2025-08-29 7:05 ` Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 02/19] dt-bindings: clock: tegra20: Add IDs for CSI PAD clocks Svyatoslav Ryhel
2025-08-22 13:59 ` Rob Herring [this message]
2025-08-27 4:19 ` Mikko Perttunen
2025-08-27 4:28 ` Svyatoslav
2025-08-27 10:27 ` Mikko Perttunen
2025-08-29 6:54 ` Krzysztof Kozlowski
2025-08-19 12:16 ` [PATCH v1 03/19] clk: tegra30: add CSI PAD clock gates Svyatoslav Ryhel
2025-08-27 4:26 ` Mikko Perttunen
2025-08-29 0:44 ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 04/19] dt-bindings: display: tegra: document Tegra30 VIP Svyatoslav Ryhel
2025-08-19 20:27 ` Rob Herring
2025-08-20 5:36 ` Svyatoslav Ryhel
2025-08-29 6:42 ` Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 05/19] staging: media: tegra-video: expand VI and VIP support to Tegra30 Svyatoslav Ryhel
2025-08-27 4:29 ` Mikko Perttunen
2025-08-27 4:47 ` Svyatoslav
2025-08-29 0:56 ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 06/19] staging: media: tegra-video: csi: move CSI helpers to header Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 07/19] staging: media: tegra-video: csi: parametrize MIPI calibration device presence Svyatoslav Ryhel
2025-09-02 0:46 ` Mikko Perttunen
2025-09-02 5:05 ` Svyatoslav Ryhel
2025-09-02 6:35 ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 08/19] staging: media: tegra-video: vi: adjust get_selection op check Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 09/19] staging: media: tegra-video: vi: add flip controls only if no source controls are provided Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 10/19] staging: media: tegra-video: tegra20: set correct maximum width and height Svyatoslav Ryhel
2025-09-02 0:51 ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 11/19] staging: media: tegra-video: tegra20: add support for second output of VI Svyatoslav Ryhel
2025-09-02 1:00 ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 12/19] staging: media: tegra-video: tegra20: simplify format align calculations Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 13/19] staging: media: tegra-video: tegra20: set VI HW revision Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 14/19] staging: media: tegra-video: tegra20: increase maximum VI clock frequency Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 15/19] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422 1X16 Svyatoslav Ryhel
2025-09-02 1:09 ` Mikko Perttunen
2025-09-02 5:11 ` Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 16/19] staging: media: tegra-video: tegra20: adjust luma buffer stride Svyatoslav Ryhel
2025-09-02 1:16 ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 17/19] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI Svyatoslav Ryhel
2025-08-19 20:30 ` Rob Herring
2025-08-20 5:39 ` Svyatoslav Ryhel
2025-08-22 14:06 ` Rob Herring
2025-08-19 12:16 ` [PATCH v1 18/19] ARM: tegra: add CSI binding for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 19/19] staging: media: tegra-video: add CSI support " Svyatoslav Ryhel
2025-09-02 2:38 ` Mikko Perttunen
2025-09-02 5:51 ` Svyatoslav Ryhel
2025-09-02 6:17 ` Mikko Perttunen
2025-09-02 6:21 ` Svyatoslav Ryhel
2025-09-02 7:11 ` Dan Carpenter
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