Re: [PATCH v2 09/11] drm/mediatek: mtk_dp: Add support for HotPlug Detection in DP AUX

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Unconditionally unmasking legacy DP_TRANS HPD interrupts while failing to clear them when `aux_hpd_supported` is true causes an unhandled IRQ storm.
- [Medium] Missing `mtk_dp->legacy_regoff` offset when polling the `MTK_DP_AUX_P0_364C` register via `regmap_read_poll_timeout()`.
--

--- Patch [9]: [PATCH v2 09/11] drm/mediatek: mtk_dp: Add support for HotPlug Detection in DP AUX ---
commit 804af7d08e6512ddf93b2634e3ded89904e4b43b
Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Subject: drm/mediatek: mtk_dp: Add support for HotPlug Detection in DP AUX

Newer MediaTek DisplayPort IPs can finally use the AUX to perform hotplug
detection without having to power up the entire eDP or DP IP. This commit
enables support for configuring and performing HPD in AUX, checking the
correct HPD strategy with a new platform data variable.

> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
> --- a/drivers/gpu/drm/mediatek/mtk_dp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c

[ ... ]

> @@ -1086,8 +1086,28 @@ static u32 mtk_dp_hwirq_get_clear(struct mtk_dp *mtk_dp)
>  	return irq_status;
>  }
>  
> +static inline u32 mtk_dp_hwirq_get_clear(struct mtk_dp *mtk_dp)
> +{
> +	if (mtk_dp->data->aux_hpd_supported)
> +		return mtk_dp_aux_hwirq_get_clear(mtk_dp);
> +
> +	return mtk_dp_trans_hwirq_get_clear(mtk_dp);
> +}

[Severity: High]
If aux_hpd_supported is true, this function only clears the AUX interrupts.
Could the unmasked DP_TRANS interrupts trigger an interrupt storm since they
are never cleared here?

>  static void mtk_dp_hwirq_enable(struct mtk_dp *mtk_dp, bool enable)
>  {
> +	u32 mask, val;
> +
> +	/* Valid only for SoCs with working AUX HPD, this register is ignored on the others */
> +	if (enable) {
> +		mask = HPD_CONNECT_EVENT | HPD_INTERRUPT_EVENT | HPD_DISCONNECT_EVENT;
> +		val = 0;
> +	} else {
> +		mask = DP_TX_AUX_INT_MASK;
> +		val = DP_TX_AUX_INT_MASK;
> +	}
> +	mtk_dp_update_bits(mtk_dp, MTK_DP_TX_AUX_INT_MASKING, val, mask);
> +
>  	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3418,
>  			   enable ? 0 :
>  			   IRQ_MASK_DP_TRANS_P0_DISC_IRQ |
>  			   IRQ_MASK_DP_TRANS_P0_CONN_IRQ |
>  			   IRQ_MASK_DP_TRANS_P0_INT_IRQ,
>  			   IRQ_MASK_DP_TRANS_P0_MASK);
>  }

[Severity: High]
Is it intended to unconditionally unmask the legacy DP_TRANS HPD interrupts
here, even when aux_hpd_supported is true?

If a DP_TRANS interrupt fires when aux_hpd_supported is true,
mtk_dp_hwirq_get_clear() will skip clearing it, which might lead to an
unhandled irq loop.

[ ... ]

> @@ -2113,10 +2191,15 @@ static int mtk_dp_wait_hpd_asserted(struct drm_dp_aux *mtk_aux, unsigned long wa
>  	u32 val;
>  	int ret;
>  
> -	ret = regmap_read_poll_timeout(mtk_dp->regs,
> -				       MTK_DP_TRANS_P0_3414 + mtk_dp->legacy_regoff,
> -				       val, !!(val & HPD_DB_DP_TRANS_P0_MASK),
> -				       wait_us / 100, wait_us);
> +	if (mtk_dp->data->aux_hpd_supported)
> +		ret = regmap_read_poll_timeout(mtk_dp->regs, MTK_DP_AUX_P0_364C,
> +					       val, !!(val & HPD_STATUS_DP_AUX_TX_P0_MASK),
> +					       wait_us / 100, wait_us);

[Severity: Medium]
Does this regmap_read_poll_timeout() call need to include the
mtk_dp->legacy_regoff offset for the MTK_DP_AUX_P0_364C register?

Other register accesses seem to consistently add this offset. Missing it
here might lead to polling the wrong physical memory address and timing out
if legacy_regoff happens to be non-zero on the hardware.

> +	else
> +		ret = regmap_read_poll_timeout(mtk_dp->regs,
> +					       MTK_DP_TRANS_P0_3414 + mtk_dp->legacy_regoff,
> +					       val, !!(val & HPD_DB_DP_TRANS_P0_MASK),
> +					       wait_us / 100, wait_us);
>  	if (ret) {
>  		mtk_dp->train_info.cable_plugged_in = false;
>  		return ret;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260709100617.42583-1-angelogioacchino.delregno@collabora.com?part=9